th

14 International Conference LOW POWER HIGH SPEED SWITCHED CURRENT COMPARATOR

Y. SUN, Y.S WANG, F.C. LAI

HARBIN INSTITUTE OF TECHNOLOGY, CHINA
MIXED DESIGN

MIXDES 2007 KEYWORDS: SI comparator, Low power, Current mode, Class AB

Ciechocinek, POLAND
21 – 23 June 2007

ABSTRACT: Current mode implementation provides an alternative to high speed data conversion systems for low
voltage applications. The pursuing of speed and accuracy of data conversion makes comparator critical. This paper
presents a novel switched current (SI) comparator which achieves high speed without sacrificing either accuracy or
power dissipation. Employing a class AB current mirror as the input stage, the desired accuracy is attained and a
dynamic class AB latched comparator is used to achieve high operation speed. Both of the input stage and the latched
comparator are low power blocks and the average supply current is only 85µA during comparison. The proposed
comparator is designed and simulated in TSMC 0.25µm CMOS process with 1.8V supply voltage. The proposed SI
comparator achieves a current sensitivity up to 0.2µA and a sampling frequency up to 100MHz, with only 153µW of
total power consumption.

INTRODUCTION performance current comparators have been proposed.

Current mode signal processing implemented in CMOS
technology has received increasing interest in the past
decades [1-3]. The circuit implemented in current mode
technique occupies small area, consumes less power
dissipation and achieves high operation speed.
Moreover, many sensors in SoC such as temperature
sensors, photo sensors provide current signal. In these
applications and high speed data converters such as RF
A/D D/A converters, oscillators, et al., where the
function of comparison is a limiting component for
accuracy, noise and power consumption reasons, the
introduction of current mode solutions is highly
desirable.
The current comparison process is injecting one or two
current flowing into the comparator and distinguishing
the current (or the difference of two current) is positive
or negative. The output nodal voltage generated by the
output current is used conveniently to indicate the
result of the comparison. The comparison process is
relatively simple, but the implementation of the current
comparator is not piddling. Low input impedance,
which is required by current mode circuits, should be
considered first. Secondly, a quick time response is
demanded by the current comparator. The main
limitation to the time response usually comes from the
initial balance of the output branches that often leads to
the triode region some output transistors. Finally,
accuracy is a crucial parameter for comparator, and it
depends on the offset caused by the mismatch of
transistors. Many good implementations have been
reported in the past decades [4-7], many of them
emphasis on one or several aspects at the cost of
deterioration in other characteristics.
D. Freitas and K. Current first proposed a CMOS
current comparator in [4]. Then many high
H. Träff presented a simple and high-speed current
comparator in [5], but the output swing of Träff’s
comparator could not reach the power supply rails. It is
more suitable to use Träff’s comparator as an input
stage rather than a comparator. G. Palmisano and G.
Palumbo proposed an offset compensated current
comparator in [6], which compensated the offset-
current due to process mismatch. However, the
capacitors for compensation employed in their design
reduced the operation speed, and the adoption of
capacitors increased the manufacture cost. V.
Boonsobhak, A. Worapishet and J.B. Hughes gave a
switched current comparator in [7], the comparator
operated at over 100MHz sampling frequency, and
achieved 7.5bits resolution, but the power efficiency
was low compared to the small input range, and the
offset was not considered.
In this paper, a low power SI comparator is proposed.
Employing a class AB current mirror as an input stage
and a CMOS latched comparator; the switched current
achieves high speed and sensitivity up to 200nA, while
the input current range is ±80µA.
This paper is organized as follows: the architecture of
the proposed comparator is presented in Section II.
Section III describes the single blocks in details and the
simulation results are shown in section IV.
PROPOSED SI COMPARATOR
ARCHITECHTURE
For a current comparator, the input signal is current
mode and the result is voltage mode. Actually, a current
comparator can be treated as a nonlinear current-to-
voltage converter.

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 A. Class AB Input Current Stage
The input stage is a class AB current mirror illustrated
Class AB in Fig.2. The current sources IB1=IB2=IB, and the
Latched Output voltage at the input node is defined by the voltage bias
Comparator
Vbias, which is 800mV in this work.
For brevity, assuming that all the current mirrors
provide 1:1 copy of the input current, and transistors
Mn1, Mn2, Mp1 and Mp2 have the same conductance
Clock coefficient, the input current is expressed as:
Generator

Fig.1 Block diagram of the proposed comparator ⎧ Iin = In − I p

⎪
The block diagram of the proposed SI comparator is ⎪ 4I B + Iin 2
⎨ In = ( ) (1)
illustrated in Fig.1. A class AB current buffer is used ⎪ 4 IB
for current offset aware topology. The input impedance ⎪⎩ 4I − I
of the current comparator is relatively low, thus the I p = ( B in )2
transmission error caused by finite transconductance is 4 IB
minimized. The input current flows into current buffer for |Iin| < 4IB. When the input current exceeds 4IB, the
and generates a voltage variation according to the current mirror operates in class B mode, and one of In
polarity of the input current. This difference of the and Ip reduce to 0, while the other equals to Iin.
buffer output voltage is then amplified by the CMOS Although the input range is over 4IB, for constant input
regenerative latched comparator driven by two impedance, the input current should be constrained
complementary clock phase. Then the comparator within 4IB [8].
generates comparison results at the output nodes.
For current comparator, the accuracy depends on offset
The basic idea of this topology is to deal the input errors, while the application of class AB current mirror
current in two steps: can reduce the offset errors greatly, and a high accuracy
Step 1: In this step, the input current generates a is achieved.
voltage variation as the input signals of the preceding The simple drain characteristic of NMOS in saturation
latched comparator, and the latched comparator reset to region is given by Id=Kn·(Vgs-VTn)2, where Kn is
the initial conditions; conductance coefficient, Vgs is the gate-source voltage,
Step 2: This step begins with a regeneration process, and VTn is the threshold voltage respectively. The
after reset phase, the voltage variation from the input variation of the drain current due to the mismatch of
stage works as the input of the latched comparator, the NMOS is given by:
according to this voltage variation, the latched
comparator begins regeneration and generates the σ K2
σ I2 = n
⋅ I d2 + 4 K n I d ⋅ σ V2 (2)
comparison results.
K n2
d Tn

As mentioned in Section I, the accuracy, speed and

where x is the mean value of x, and σ x is the variance
2
power dissipation are critical for comparators, and in
this comparator, these are realized in the input stage of x, refer to [9-10].
block and the latched comparator separately. In the
input stage, by the application of class AB current For input current |Iin| < 4IB, the input signal distributes
mirror, the offset is minimized, and the input between Mn3 and Mp3, and Iin=IDn3-IDp3, Iout=IDn4-IDp4.
impedance reduction is achieved as well. The high Thus the offset is attributed to the mismatch between
speed is achieved by the dynamic latched comparator; Mn3/Mn4 and Mp3/Mp4.
also the class AB structure of the input stage and the
latched comparator reduced the power dissipation 1:1
IB1 Mp3 Mp4
without sacrificing speed and accuracy.
Ip
SINGLE BLOCKS OF PROPOSED SI Mn1 Mn2
1:1
COMPARATOR VBias Input Output
1:1
Mp1 Mp2
The proposed current comparator consists of two blocks
(excluding clock generator): input stage and latched In
comparator. Mn3 Mn4
IB2 1:1
In this section, these two blocks are depicted in details
and the accuracy, speed and power dissipation for each
block are analyzed. Fig.2 Class AB current mirror

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 All mismatches affect the conductance coefficient K Vdd
and the threshold voltage of transistors VT, and the M4a M3a M3b M4b
analysis on offset caused by mismatches could be M5a M5b
focused on conductance mismatch and threshold Latch Latch
voltage mismatch. The mismatch models are based on Out1 Out2
the Gaussian propagation of variance, and the M2a M2b
simplistic drain current model is used for calculation.
Input P Input N
M1a M1b
I D = K ⋅ (Vgs − Vt ) 2 (3)
Subscribing formula (3) into formula (1), and noting
the relationship Iout=IDn4-IDp4, the output current can be Latch
M6
derived as: Gnd

I out = K n 4 ⋅ (Vgsn 4 − VTn 4 ) 2 − K p 4 ⋅ (Vgsp 4 − VTp 4 ) 2 (4) Fig. 3 Dynamic Class AB Latched Comparator
the cross coupled inverters begin regeneration, one of
For given independent variables p1, p2… and dependent
the branches, M2a/ M3a or M2b/M3b, conducts more
variable y=g (p1, p2…), the propagation of the variance
current, and determines the final output state.
of y is defined as:
After regeneration finishes, one of the output nodes is
2
⎛ ∂y ⎞ at Vdd, and the other output and both drains of the
σ y2 = ∑ ⎜ 2
⎟ ⋅ σ pi (5) differential pair is at Gnd. There is no supply current
i ⎝ ∂pi ⎠
flow through the comparator either. For one whole
Then the variance of Iout can be calculated as: period of operation, there is supply current only during
regeneration, which maximizes the power efficiency.
σK2
σI2 2 2 The dynamic latched comparator exhibits highest speed
= ⋅ Idn4 + 4Kn4Idn4 ⋅σV
n4

Kn24 and power efficiency, but causes more kickback noise.

out Tn4

This increasing kickback noise originates from the rail-

σK2 to-rail excursion at the drains of M1a/M1b. In reset
2 2
+ ⋅ Idp4 + 4Kp4Idp4 ⋅σV
p4
(6) phase, there is no supply current, and the drains of
K2p4
Tp4
M1a/M1b are set to be Vdd by M5a/M5b. At the
⎛σ2 σ K2 ⎞ beginning of the regeneration, the current starts to flow
⎜
=⎜
Kn4
+
⎜ Kn4 Kp4 ⎟
2 2
p4 ⎟ 2
( 2 2
⎟ ⋅ IB + 4IB ⋅ Kn4 ⋅σVTn4 + K p4 ⋅σVTp4 ) through M1a/M1b, these two transistors enter
saturation from cut-off. When the comparison
⎝ ⎠ completes, the drains of M1a/M1b go down to 0-V. The
Theoretically, the offset current decided by formula (6) voltage variation form Vdd to 0-V couples through
is the minimal detectable current of the proposed SI gate-drain capacitance and causes input voltage
comparator. In practice, the offset is usually given by variation.
Monte Carlo analysis. A Monte Carlo Analysis is also SIMULATION RESULTS
performed in this paper and the results are illustrated in
the preceding sections. The proposed switched current comparator is designed
in TSMC 0.25µm CMOS process and simulated with
B. Class AB Latched Comparator
Hspice program. The average power dissipation is
Considering power dissipation, speed and kickback 153µW under 1.8V single supply voltage. This
noise, a dynamic class AB latched comparator is used. comparator operates well under 100MSamples/s at
The schematic of the latched comparator is illustrated 8.6bits and 200MSamples/s at 7.5bits. The simulation
in Fig.3. results for ±20µA current input sampled and compared
at 100MHz sampling frequency is illustrated in Fig. 4.
M1a and M1b are input transistors, M2a-M3a, M2b-
M3b compose a latch structure, and M6 is used for According to Fig.4, during reset phase, the voltage at
power reduction, while the other transistors are used for output node is 1.8V, after regeneration has started
reset. The comparator is controlled by a single clock (clock goes low), one of the output node voltage
phase Latch. regenerates quickly to 0V. It can be observed that at the
beginning of the reset phase and regeneration, there is
When Latch is low (reset phase), transistors M4a, M4b tiny voltage surge at the input node of the proposed
and M5a, M5b reset nodes Out1 and Out2 and the comparator.
drain terminals of the differential pair M1a/M1b to Vdd.
M6 is cut off, thus there is no supply current flow The comparator performance was conducted via Monte-
through the comparator. When Latch is high, all the Carlo simulations. Taking geometric mismatch and
reset transistors cut off, the current starts to flow in M6 threshold voltage mismatch into account, the
and the differential pair. According to the input voltage, simulation based on 100runs indicate that the proposed

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 Comp. Comp. Comp. Comp. The high operating speed and low power dissipation
Reset Reset Reset Reset
50u
features of the proposed SI comparator enable the
Current (A)

20u implementation of high performance current mode

0 pipeline ADCs with digital error correction at more
-20u
-50u
than 10 bits of resolution and more than 100MHz
conversion speed. Also the low power dissipation
2 out1
Voltage (v)

characteristic is quite suitable for portable and battery

1 input
supplied electronics devices.

0
out2
980n 990n
Time (s)
Fig. 4 Transient response of the proposed SI comparator
comparator offset has a standard deviation of 182nA at
100MS/s for 2% geometric mismatch and 20%
threshold voltage mismatch, when the geometric
mismatch goes up to 5%, the standard deviation of
offset is 395nA. Considering the input range is ±80µA,
the effective resolution of the proposed comparator is at
8.6 bits. The simulation result of Monte Carlo analysis
for 2% geometric mismatch and 20% threshold voltage
mismatch is shown in Fig.5.
Table 1 compares performance of the proposed
comparator with other conventional topologies.
TABLE 1 SI comparator performance
Fs Resolution
[6] <30M — —
[7] 100M 7.5bits
This
100M 8.6bits
work
CONCLUSION
A high speed low power switched current comparator is
proposed in this paper. For speed and accuracy
enhanced SI comparator, the two-step topology is
employed. Combining class AB current mirror and
dynamic class AB latched comparator; low power
dissipation is achieved without sacrificing other
performance. Designed and simulated in TSMC
0.25µm CMOS process, the proposed SI comparator
works well when sampled at 100MHz and 8.6bits
effective resolution is guaranteed.
200n
100n
Current (A)
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1µ 1.01µ 1.02µ
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-200n
0 20 40 60 80 100

Fig. 5 Monte Carlo simulation for 2% geometric and 20%

threshold voltage mismatch at 100runs

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