Experiment with FPGA (Field Programmable Gate Array)

Ans 1 :
`timescale 1ns / 1ps
module mult(out, x, y, clk);
input [1:0] x;
input[1:0] y;
input clk;
output reg [3:0] out;
always@(x or y)
begin
assign {out} = x*y;
end
endmodule
Timing Diagram:

2-bit multiplier

Ans 2:
`timescale 1ns / 1ps
module counter1( q,ip,clk);
input clk;
input [3:0]ip;
output [3:0] q;
reg [3:0] q;
integer count;
//wire [3:0] d_cntr;
initial begin
q[3:0] = 4'b0000;
count = 0;
end
always @ (posedge clk)
begin
count<=count+1;
if ((count%2)== 0)
begin
//count<=0;
if ( q[3:0] == ip)
q<=4'b0000;
else
//q <= d_cntr;
q<= q+1;
end
end
endmodule
Timing Diagram:

Divide Counter

Ans 3:

State Transition

`timescale 1ns / 1ps

module std1(out,f,r,clk );
input f;
input r;
input clk;
output reg [2:0] out;
reg [2:0] current;
initial begin
current[2:0] = 3'b000;
end
always @(posedge clk) begin
if((current[2:0] == 3'b000)&&(f==1)&&(r==0)) begin
out = 3'b001;
current = out;
end else if((current[2:0] == 3'b000)&&(r==1)) begin
out = 3'b110;
current = out;
end else if((current[2:0] == 3'b001)&&(f==1)&&(r==0)) begin
out = 3'b010;
current = out;
end else if((current[2:0] == 3'b001)&&(r==1)) begin
out = 3'b000;
current = out;
end else if((current[2:0] == 3'b010)&&(f==1)&&(r==0)) begin
out = 3'b011;
current = out;
end else if((current[2:0] == 3'b010)&&(r==1)) begin
out = 3'b001;
current = out;
end else if((current[2:0] == 3'b011)&&(f==1)&&(r==0)) begin
out = 3'b101;
current = out;
end else if((current[2:0] == 3'b011)&&(r==1)) begin
out = 3'b010;
current = out;
end else if((current[2:0] == 3'b101)&&(f==1)&&(r==0)) begin
out = 3'b110;
current = out;
end else if((current[2:0] == 3'b101)&&(r==1)) begin
out = 3'b011;
current = out;

end else if((current[2:0] == 3'b110)&&(f==1)&&(r==0)) begin

out = 3'b000;
current = out;
end else if((current[2:0] == 3'b110)&&(r==1)) begin
out = 3'b101;
current = out;
end end
endmodule
Timing Diagram: