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  • Ieee IEEE - STD - LOGIC - 1164 Ieee - STD - Logic - Arith Ieee - STD - Logic - Unsigned STD - Logic STD - Logic STD - Logic STD - Logic

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    Bisz Beta
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    This document defines an entity called "motores" with 4 inputs (a,b,c,d) and 4 outputs (w,x,y,z). It declares AND, OR logic components and instantiates them to implement the logic functions of the inputs and assign the outputs. Specifically, it maps the inputs to 3-input AND gates to assign w, x, and y, and combines other gates to assign z based on the input conditions.

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    e Structural

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    This document defines an entity called "motores" with 4 inputs (a,b,c,d) and 4 outputs (w,x,y,z). It declares AND, OR logic components and instantiates them to implement the logic functions of the inputs and assign the outputs. Specifically, it maps the inputs to 3-input AND gates to assign w, x, and y, and combines other gates to assign z based on the input conditions.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    20 views5 pages

    Ieee IEEE - STD - LOGIC - 1164 Ieee - STD - Logic - Arith Ieee - STD - Logic - Unsigned STD - Logic STD - Logic STD - Logic STD - Logic

    Uploaded by

    Bisz Beta
    This document defines an entity called "motores" with 4 inputs (a,b,c,d) and 4 outputs (w,x,y,z). It declares AND, OR logic components and instantiates them to implement the logic functions of the inputs and assign the outputs. Specifically, it maps the inputs to 3-input AND gates to assign w, x, and y, and combines other gates to assign z based on the input conditions.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    of 5

    library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    entity motores is
    Port ( a,b,c,d : in STD_LOGIC;
    w,x,y,z : out STD_LOGIC);
    end motores;
    architecture structural of motores is
    signal n1,n2 : std_logic;
    ----------------------------------------------------------declaro compuerta
    -----------------------------------------------------component and_2
    port (f,g: in std_logic;
    j: out std_logic);
    end component;
    ---------------------------------------------------declaro compuerta
    -------------------------------------------------component and_3
    port (f,g,h: in std_logic;
    j: out std_logic);
    end component;

    ---------------------------------------------------declaro compuerta
    -------------------------------------------------component or_2
    port (f,g: in std_logic;
    j: out std_logic);
    end component;
    -------------------------------------------------declaro las entradas y salidas para cada
    caso
    ---------------------------------------------begin
    U0:and_3 port map (a,b,(not d),w);
    U1:and_3 port map (a,b,(not d),x);
    U2:and_2 port map (c,(not d),y);
    U3:and_3 port map ((not a),(not c),d,n1);
    U4:and_3 port map ((not b),(not c),d,n2);
    U5:or_2 port map (n1,n2,z)
    end structural;

    Despus de haber sintetizado cada compuerta me dirijo al link:

    Asigno pines y sintetizo el proyecto

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