EXPERIMENT NO.

7
Aim
To implement VHDL code for Tristate Buffer.

Tool required
Mentor Graphics FPGA advantage 8.1ps Model sim 6.3a

Theory
In digital electronics a tri-state logic allows an output port to assume a high impedance state in addition to the 0 and 1 logic levels, effectively removing the output from the circuit. This allows multiple circuits to share the same output line or lines. The whole concept of the third state (Hi-Z) is to effectively remove the device's influence from the rest of the circuit. If more than one device is electrically connected, putting an output into the Hi-Z state is often used to prevent short circuits, or one device driving high (logical 1) against another device driving low (logical 0).

Fig.(7.1)

Truth Table Input C X 0 0 1 1 0 1 0 1 output Z z z 0 1

Table(7.1a) In this case, when the output is Z, that means it's high impedance, neither 0, nor 1, i.e., no current.

VHDL code for Tristate Buffer

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY TRI_STATE IS PORT (I: IN STD_LOGIC_VECTOR (0 TO 7); E: IN STD_LOGIC; Y: OUT STD_LOGIC_VECTOR(0 TO 7)); END ENTITY TRI_STATE; -ARCHITECTURE TS OF TRI_STATE IS BEGIN PROCESS(E,I) BEGIN IF(E='0') THEN Y<="ZZZZZZZZ"; ELSE Y<=I; END IF; END PROCESS; END ARCHITECTURE TS;

Output:

Result Window of Tristate Buffer

Result
The VHDL code for Tristate Buffer were implemented and simulated successfully.