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    It DLD

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    Karunakar Ella
    This document contains an internal question paper for the first semester B.Tech students of NRI Institute of Technology. The paper tests students' knowledge of digital logic design concepts through 4 questions. Question 1 has parts on binary, octal, and hexadecimal conversions. Question 2 covers basic logic gates and universal gates, as well as Boolean logic. Question 3 involves designing a logic circuit to detect binary numbers that are powers of 2. Question 4 requires explaining and designing half and full adders with truth tables and logic gates. The paper tests students on essential digital logic design topics over 120 minutes for a total of 40 marks.

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    It DLD

    Uploaded by

    Karunakar Ella
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    This document contains an internal question paper for the first semester B.Tech students of NRI Institute of Technology. The paper tests students' knowledge of digital logic design concepts through 4 questions. Question 1 has parts on binary, octal, and hexadecimal conversions. Question 2 covers basic logic gates and universal gates, as well as Boolean logic. Question 3 involves designing a logic circuit to detect binary numbers that are powers of 2. Question 4 requires explaining and designing half and full adders with truth tables and logic gates. The paper tests students on essential digital logic design topics over 120 minutes for a total of 40 marks.

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    IT DLD

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    This document contains an internal question paper for the first semester B.Tech students of NRI Institute of Technology. The paper tests students' knowledge of digital logic design concepts through 4 questions. Question 1 has parts on binary, octal, and hexadecimal conversions. Question 2 covers basic logic gates and universal gates, as well as Boolean logic. Question 3 involves designing a logic circuit to detect binary numbers that are powers of 2. Question 4 requires explaining and designing half and full adders with truth tables and logic gates. The paper tests students on essential digital logic design topics over 120 minutes for a total of 40 marks.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
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    4 views1 page

    It DLD

    Uploaded by

    Karunakar Ella
    This document contains an internal question paper for the first semester B.Tech students of NRI Institute of Technology. The paper tests students' knowledge of digital logic design concepts through 4 questions. Question 1 has parts on binary, octal, and hexadecimal conversions. Question 2 covers basic logic gates and universal gates, as well as Boolean logic. Question 3 involves designing a logic circuit to detect binary numbers that are powers of 2. Question 4 requires explaining and designing half and full adders with truth tables and logic gates. The paper tests students on essential digital logic design topics over 120 minutes for a total of 40 marks.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
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    NRI INSTITUTE OF TECHNOLOGY

    (APPROVED BY AICTE, AFFILIATED TO JNTU KAKINADA)

    POTHAVARAPPADU (V), VIA NUNNA, AGIRIPALLI (M), KRISHNA (DT), A.P. PIN 512 212 INTERNAL QUESTION PAPERS st CLASS : II/IV B.Tech. 1 Semester ACADEMIC YEAR : 2012 13 DATE : 31 08 2012

    SUBJECTIVE TEST I BRANCH : IT SUBJECT : DLD N.B. : 1. Answer the following questions. 2. ALL questions carry EQUAL marks. Max. Time : 120 MINUTES Max. Marks : 40 Marks

    1. a) Perform the Following: (i) ABCD16 = ( )10 = ( )2 (ii) 110011112 = ( )10 = ( )16 (iii) 55510 = ( )16 [2M + 2M + 1M] b) Encode 1101, 7 bit hamming code using a Even parity. [5M] 2. a) Explain all Basic Logic Gates and Universal Gates with Truth Tables. [4M] b) Find the complement of the following and show that and . ( ( [3M + 3M] 3. (a) Construct a logic circuit with 4 inputs ( X0, X1, X2, X3) with X0 as MSB and signal output Z. The circuit output should be 1 if and only if the inputs represents a number that is either 0 or power of 2. [7M] (b) Reduce the following Boolean expression using K Map F(A, B, C) = m(0, 1, 3, 7) + d(2, 5). [3M] 4. Explain and Design Half Adder and Full Adder with Truth Tables and Logic Gates. [10M]

    *****

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