1.

2-to-1 multiplexer design

GATE LEVEL
module mux2_gt(out,i0,i1,s0);
output out;
input i0,i1,s0;
wire sbar,y1,y2;
not g1(sbar,s0);
and g2(y1,i0,sbar);
and g3(y2,i1,s0);
or g4(out,y1,y2);
endmodule

BEHAVIORAL LEVEL
module mux21_bh (din_0, din_0,s0, y);
input din_0;
input din_1;
input s0;
output y;
reg y;
wire s0;
always@(sel or din_0 or din_1)
begin
if(sel==1b0)
begin
y=din_0;
else
y=din_1;
end
end
endmodule

DATA FLOW LEVEL

module mux2_dt(out,in0,in1,select);
output out;
input in0,in1,select;
wire out=(in0&(~select))|(in1&select);
endmodule

SWITCH LEVEL
module mux(out, in, sel);
output out;
input[1:0]in;
input sel;
wire sel_b;
supply1 pwr;
supply2 gnd;
pmos(sel_b, pwr, sel);
nmos(sel_b, gnd, sel);
cmos(out, in[0], sel_b, sel);
cmos(out, in[1], sel, sel_b);
endmodule

2. 4-to-1 multiplexer design

GATE LEVEL
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3;
input s1, s0;
wire s1n, s0n;
wire y0, y1, y2, y3;
not (s1n, s1);
not (s0n, s0);
and (y0, i0, s1n, s0n);
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);
or (out, y0, y1, y2, y3);
endmodule

DATA FLOW
`resetall
`timescale 1ns/1ps
module mux41data (din,s,y);
input [0:3] din;
input[0:1]s;
output out;
assign out=din[s];
endmodule

BEHAVIORAL
`resetall
`timescale 1ns/1ps
module mux42beh(din, s0, s1, y);
input [0:3] din;
input s0;
input s1;
output y;
reg y;
wire s0,s1;
always@(s0 or s1) begin
case({s0,s1})
2'b00:y=din[0];
2'b01:y=din[1];
2'b10:y=din[2];
2'b11:y=din[3];
default:y=1'b1;
endcase
end
endmodule

3. 3-to-8 decoder design

GATE LEVEL
module decoder(Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,A,B,C);
output Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7;
input A,B,C;
wire s0,s1,s2;
not (s0,A);
not (s1,B);
not (s2,C);
and (Q0,s0,s1,s2);
and (Q1,A,s1,s2);
and (Q2,s0,B,s2);
and (Q3,A,B,s2);
and (Q4,s0,s1,C);
and (Q5,A,s1,C);
and (Q6,s0,B,C);
and (Q7,A,B,C);
endmodule

DATA FLOW
`resetall`
timescale 1ns/1ps
module dec38data (a,b,c,dout);
input a,b,c;
output [0:7]dout;
assign dout[0]=(~a)&(~b)&(~c);
assign dout[1]=(~a)&(~b)&c;
assign dout[2]=(~a)&b&(~c);

assign
assign
assign
assign
assign
endmodule

dout[3]=(~a)&b&c;
dout[4]=a&(~b)&(~c);
dout[5]=a&(~b)&c;
dout[6]=a&b&(~c);
dout[7]=a&b&c;

BEHAVIORAL MODELING
`resetall`
timescale 1ns/1ps
module decoder38beh(a, b, c, y);
input a;
input b;
input c;
output [0:7] y;
reg [0:7]y;
// wire a,b,c;
always@(a or b or c)
begin
case({a,b,c})
3'b000:begin y=8'b10000000; end
3'b001:begin y=8'b01000000; end
3'b010:begin y=8'b00100000; end
3'b011:begin y=8'b00010000; end
3'b100:begin y=8'b00001000; end
3'b101:begin y=8'b00000100; end
3'b110:begin y=8'b00000010; end
3'b111:begin y=8'b00000001; end
default :begin y=8'b00000000; end
endcase
end
endmodule

4. 1-bit full adder design

GATE LEVEL
//define a 1bit fulladder
module fulladd(sum, c_out, a, b, c_in);output sum, c_out;
input a, b, c_in;
wire s1, c1, c2;
xor (s1, a, b);
and (c1, a, b);
xor (sum, s1, c_in);
and (c2, s1, c_in);
or (c_out, c2, c1);
endmodule

DATA FLOW
module full_adder
(input a,
input b,
input c,
output sum,
output carry);
assign sum = a & ~b & ~c | ~a & b & ~c | ~a & ~b & c | a & b & c;
assign carry = a & b | a & c | b & c;
endmodule

5. 4-bits full adder design

GATE LEVEL
module fulladd4(sum, c out, a, b, c_in);
output [3:0] sum;
output c_out;
input[3:0] a, b;
input c_in;
wire c1, c2, c3;
fulladd fa0(sum[0], c1, a[0], b[0], c_in);
fulladd fa1(sum[1], c2, a[1], b[1], c1);
fulladd fa2(sum[2], c3, a[2], b[2], c2);
fulladd fa3(sum[3], c_out, a[3], b[3], c3);
endmodule
DATA FLOW
module adder (sum, a, b);
input [3:0] a, b;
output [4:0] sum;
wire [4:0] sum;
assign sum = a + b; // assign p=a*b;
endmodule

6. 8-to-1 multiplexer
DATA FLOW
module mux81data1(s,din,y);
input [0:2]s;
input [0:7]din;
output y;wire [0:7]t;
assign t[0]=(~s[0])&(~s[1])&(~s[2]&i[0]);
assign t[1]=(~s[0])&(~s[1])&(s[2]&i[1]);
assign t[2]=(~s[0])&(s[1])&(~s[2]&i[2]);

assign
assign
assign
assign
assign
assign
endmodule

t[3]=(~s[0])&(s[1])&(s[2]&i[3]);
t[4]=(s[0])&(~s[1])&(~s[2]&i[4]);
t[5]=(s[0])&(~s[1])&(s[2]&i[5]);
t[6]=(s[0])&(s[1])&(~s[2]&i[6]);
t[7]=(s[0])&(s[1])&(s[2]&i[7]);
y=t[0]|t[1]|t[2]|t[3]|t[4]|t[5]|t[6]|t[7];

BEHAVIORAL
module mux81bh(i,s,o);
input [0:7]i;i
nput [0:2]s;
output o;
wire [0:7]i;
wire [0:2]s;
wire [0:7]y;
reg o;
always@(s)
begin
case(s)
3'b000: o=i[0];
3'b001: o=i[1];
3'b010: o=i[2];
3'b011: o=i[3];
3'b100: o=i[4];
3'b101: o=i[5];
3'b110: o=i[6];
3'b111: o=i[7];
endcase
end
endmodule
7. 4-to-2 line encoder
BEHAVIORAL
module encoder42beh(din,
input [0:3] din;
output a;
output b;
reg a;
reg b;
always@(din)
begin
case({din})
4'b1000:begin
4'b0100:begin
4'b0010:begin

a, b);

a=1'b0; b=1'b0; end

a=1'b0; b=1'b1; end
a=1'b1; b=1'b0; end

4'b0001:begin a=1'b1; b=1'b1; end

endcase
end
endmodule
DATA FLOW
module encoder42data(din,a,b);
input [0:3]din;
output a,b;
assign a=(din[2])|(din[3]);
assign b=(din[1])|(din[3]);
endmodule
GATE LEVEL
module encoder_4to2_gates (i0,i1,i2,i3,y);
input i0,i1,i2,i3;
output [1:0] y;
or o1 (y[0],i1,i3);
or o2 (y[1],i2,i3);
endmodule

8. 8-TO-3 line encoder

DATA FLOW
module encoder83df(din, a, b, c);
input [0:7] din;
output a;
output b;output c;
assign a=din[4] | din[5] | din[6] | din[7];
assign b=din[2] | din[3] | din[6] | din[7];
assign c=din[2] | din[4] | din[6] | din[7];
endmodule

BEHAVIORAL
module encodr83bh (din,a,b,c);
input [0:7]din;
output a,b,c;
reg a,b,c;
always@(din)
begin
case(din)
8'b10000000:begin a=1'b0;b=1'b0,c=1'b0;end
8'b01000000:begin a=1'b0;b=1'b0;c=1'b1;end
8'b00100000:begin a=1'b0;b=1'b1;c=1'b0;end
8'b00010000:begin a=1'b0;b=1'b1;c=1'b1;end
8'b10001000:begin a=1'b1;b=1'b0,c=1'b0;end
8'b10000100:begin a=1'b1;b=1'b0,c=1'b1;end

8'b10000010:begin a=1'b1;b=1'b1,c=1'b0;end
8'b10000001:begin a=1'b1;b=1'b1,c=1'b1;end
default :begin a=1'bz;b=1'bz;c= 1'b1;end
endcase
end

9. Shift Register
BEHAVIORAL
module shiftReg
(input CLK,
input reset,
// initialize registers
input shift,
input [7:0] Din, // Data input for load
output [7:0] Dout);
reg [7:0] D0, D1, D2, D3;
assign Dout = D0;
always @(posedge CLK) begin
if (reset) begin
D0 <= 0; D1 <= 0; D2 <= 0; D3 <= 0;
end else if (shift) begin
D3 <= Din; D2 <= D3; D1 <= D2; D0 <= D1;
end
end
endmodule

10. 2-to-4 line decoder

DATA FLOW
`resetall
`timescale 1ns/1ps
module decoder24df(a, b, y);
input a;input b;output [0:3] y;
wire a,b;
assign
assign
assign
assign
endmodule

y[0]=(~a) & (~b);

y[1]=(~a)& (b);
y[2]=(a) & (~b);
y[3]= a & b;

BEHAVIORAL
module Decd2to4(i0, i1, out0, out1, out2, out3);
input i0;
input i1;
output out0;
output out1;
output out2;

output out3;
reg out0,out1,out2,out3;
always@(i0,i1)
case({i0,i1})
2'b00: {out0,out1,out2,out3}=4'b1000;
2'b01: {out0,out1,out2,out3}=4'b0100;
2'b10: {out0,out1,out2,out3}=4'b0010;
2'b11: {out0,out1,out2,out3}=4'b0001;
default: $display("Invalid");
endcase
endmodule

GATE LEVEL
module decoder_2x4_gates (D, A, B, enable);
output [0: 3] D;`
input A, B;
input enable;
wire A_not, B_not, enable_not;
not
G1
G2
G3

(A_not, A),
(B_not, B),
(enable_not, enable);

G4
G5
G6
G7

(D[0],
(D[1],
(D[2],
(D[3],

nand

endmodule

A_not, B_not, enable_not),

A_not, B, enable_not),
A, B_not, enable_not),
A, B, enable_not);