DOC/LP/01/28.02.

02

LAB PLAN
EC 2207-DIGITAL ELECTRONICS LAB
Branch(Student) : EC Semester: III

LP- EC2207 Revision No:02 Date: 02/07/12 Page 1 of 3 0 0 3 100

EC2207 DIGITAL ELECTRONICS LAB 1. Design and implementation of Adder and Subtractor using logic gates. 2. Design and implementation of code converters using logic gates (i) BCD to excess-3 code and vice versa (ii) Binary to gray and vice-versa

3.Design and implementation of 4 bit binary Adder/ subtractor and BCD adder using IC 7483 4. Design and implementation of 2 bit Magnitude Comparator using logic gates 8 Bit Magnitude Comparator using IC 7485 5. Design and implementation of 16 bit odd/even parity checker generator using IC74180. 6. Design and implementation of Multiplexer and De-multiplexer using logic gates and study of IC74150 and IC 74154 7. Design and implementation of encoder and decoder using logic gates and study of IC7445 and IC74147 8. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters 9. Design and implementation of 3-bit synchronous up/down counter 10. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops 11. Design of experiments 1, 6, 8 and 10 using Verilog Hardware Description Language

DOC/LP/01/28.02.02

LAB PLAN
EC 2207-DIGITAL ELECTRONICS LAB
Branch(Student) : EC Semester: III

LP- EC2207 Revision No:02 Date: 02/07/12 Page 2 of 3

LP- EC2207 Revision No:01 Date: 28/06/10 Page 2 of 3

Digital Electronics Lab Objective: To Design Combinational and Sequential logic Circuits using logic gates, make a study of various ICs and study using Verilog Hardware Description Language.
1Batch 6Batch 7Batch 11Batch Ses. No 12Batch 5 6 7 8 9 2 3 4 11 12 13 14 10 2Batch 3Batch 4Batch 5Batch 8Batch 9Batch 2 3 4 5 6 7 8 9 13 14 10 11 12 10Batch 3 4 5 6 7 8 9 2 14 10 11 12 13

INTRODUCTION & Exp no. 1

2 3 4 5 6 7 8 9 10 11 12 13 14 15

2 3 4 5 6 7 8 9 10 11 12 13 14

3 4 5 6 7 8 9 2 11 12 13 14 10

4 5 6 7 8 9 2 3 12 13 14 10 11

5 6 7 8 9 2 3 4 13 14 10 11 12

6 7 8 9 2 3 4 5 14 10 11 12 13

7 8 9 2 3 4 5 6 10 11 12 13 14

8 9 2 3 4 5 6 7 11 12 13 14 10

9 2 3 4 5 6 7 8 12 13 14 10 11

4 5 6 7 8 9 2 3 10 11 12 13 14

MODEL EXAM

DOC/LP/01/28.02.02

LAB PLAN
EC 2207-DIGITAL ELECTRONICS LAB
Branch(Student) : EC Semester: III

LP- EC2207 Revision No:02 Date: 02/07/12 Page 3 of 3

LP- EC2207 Revision No:01 Date: 28/06/10 Page 3 of 3

List of Experiments:
S. No 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Title Adders and Subtractors using logic gates BCD to excess-3 code converter and vice versa using logic gates Binary to gray code converter and vice-versa using logic gates 4 bit binary Adder/ Subtractor using IC7483 2-Bit Magnitude Comparator using logic gates BCD adder using IC 7483 and 8-Bit Magnitude Comparator using IC7485 16-bit odd/even parity checker/ generator using IC74180 Mux and De-mux using logic gates and study of IC74150, IC 74155 Encoder and decoder using logic gates and study of IC74155, IC74147 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters 3-bit synchronous up/down counter SISO, SIPO, PISO and PIPO shift registers using Flip-flops Design of adder , subtractor, multiplexer, demultiplexer using Verilog Hardware Description Language Design of counters and shift registers using Verilog Hardware Description Language 11 11 Cross reference as per syllabus 1 2 (i) 2 (ii) 3 4 3 &4 5 6 7 8 9 10

Prepared by Signature Name Designation Date P.Jothilakshmi/ M.Athappan T.J.Jeyaprabha/L.Anju Assistant Professors 02/07/12

Approved by

Dr. S.Ganesh Vaidyanathan HOD/EC 02/07/12