II

- VHDL


....................................................................................

VHDL 2 ......................................
3 ....................................................................................
6 .........................................................................
8 .....................................................................
? 9 .......................................................................
13 ......................................................................................................
:1 ................................................................

15

................................................................................
* .................................................................
.......................................... Design Entry
................................. Design Flows
* ................................................
...........................................................................
............................................................... VHDL
................................................................................
..................................................................................................
..................................................... ModelSim
.............................................................. ModelSim
.................................................... ModelSim
.............................................. ModelSim
script ................................................. ModelSim
Test Bench * ......................
................................................. Riviera-PRO
.......................................................... Riviera-PRO
............................................... Riviera-PRO
.......................................... Riviera-PRO
script ............................................. Riviera-PRO
....................................................................................
.........................................................
RTL ................................... Gate-Level
* ...........................................
................................................ Quartus
* ..........................................................................
....................................................... * Quartus
)/( ....................... * DE2

16
17
20
22
26
29
33
35
35
37
39
41
43
44
47
48
50
53
56
57
60
60
66
69
73
80
87
92

- VHDL

III

 :2 ................................................................

101

................................................................................
........................................................................
........................................................................................... VHDL
................................................................... VHDL
............................................................
..............................................................................
.................................................................. VHDL
......................................................................
......................................................................................... entity -
................................................................... architecture -
port - ......................................
.........................................................
Test Bench * ......................
..................................................................
* ...............................................................................
....................................................................................
............................................................................
......................................................................................
........................................................
...........................................................
............................................................................ Enumerated
) ( ..............................................................
bit_vector - ............................................. string
...........................................................................................
- ...............................
................................................. * VHDL-2008 -
- ..............
- ) (slice ...........................
bit - bit_vector ..............................................
.............................................................................................
.........................................................................
...................................................
- .........................................................
...........................................................................
..................................... * VHDL-2008 -
...................................................
................................................................................... package -
..................................................................................... use
* ............................................................
.....................................................................
.................................................................
......................................................... std_logic_1164

101
102
102
104
106
107
107
110
110
112
115
120
124
125
129
132
132
134
137
143
145
146
148
149
152
153
155
158
160
161
162
167
171
171
174
175
175
178
181
182
183
186

IV

- VHDL

 std_logic_unsigned 193 .................. std_logic_signed

) 199 .................................... (VHDL-2008
- 200 ..........................................................
- * 202 .........................................................
- * 204 .........................................................
210 ................................ * VHDL-2008 -
211 ................... * VHDL-2008 -
217 ................................................... * VHDL-2008 -
context - 227 ............................ * VHDL-2008 -
VHDL-2008 - * 228 .................................................
:3 .....................................................

231

................................................................................
...................................................................
.........................................................................
...................
..................................................
...................................................................
.....................................................
.........................................................................................
............ wait
.............................................................
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.............................................
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- .................................................... if
if VHDL ...........................................
if "??" * ..........................................................
- ............................................... case
case VHDL .......................................
case ..............................
Matching-Case ................................................ * VHDL-2008 -
if case ...................... * VHDL-2008 -
......................................................................................................
..................................................................................... for
......................................................................... for
for ....................................................
............................................................................
..........................................................................................

232
233
233
236
242
244
245
249
250
254
255
255
260
267
270
272
275
277
279
280
281
283
283
284
288
291
296

- VHDL

 :4 301 .....................................................
................................................................................
..................................
..........................
.........................................................
..............................................................
..........
..........................................................................
AHDL - ................................................. * VHDL
................................................................................
.........................................................................................
..............................................
Tri-State .................................................................. Open Drain
Latch ......................................................................
Tri-State ..................

302
303
306
307
308
312
313
320
322
330
333
334
342
345

:5 351 ..................................................
................................................................................
.................................................................................
........................................................
.................................................. bit
....................................................................................
.......................................
..................................................................................
Template - - ......................................... I
Template - - ........................................ II
..........................................................
...................................................
.......................................................
..........................................................................................
.....................................................
...................................................................
- .............................................
- .....................
..........................................................................................
.............................................................................
- .....................................
- ..........................................
..............................

VI

- VHDL

352
353
353
360
364
369
371
378
381
386
390
392
402
402
408
412
414
419
431
435
439
444

 :6 447 ............................................................
................................................................................
................................................................................
.............................................. assert
.............................................................. assert
.......................................
* .............................................................
................................... * VHDL-2008 -
............................................................................................. wait
........................................................................... wait
........................................................................................ wait on
...................................................................................... wait until
- wait ................................................................... on + until
......................................................................................... wait for
................................................................. wait
.......................................................................................
.............................................................................................
........................................................... wait
..................................................................................................
......................................................
.............................................................................................
......................................................................
................................................................
* .......................................................................................
...............................................................................
* .........................................................
* .......................................................................
* ....................................................................
.......................................... * real

448
449
449
450
454
456
457
460
460
461
463
465
467
468
470
471
472
475
475
478
478
480
483
483
484
488
490
491

:7 ........................................................

493

................................................................................
..........................................................................
.....................................................
....................................................... ? Component
Top-to-Bottom ............................................. Bottom-Up
...............................................................
...................................................
..........................................................................................
.......................................................
)..................................................... (Named Association

491
499
504
506
508
511
513
517
518
519

- VHDL

VII

 ...................................................................................
.............................................................................................
............................................................................................
- ................................
........................................................................
) .................. (VHDL-2002
...........................................................
.............................................................................. BUS -
Test-Bench ........................................................................
? ..............................................
........................................................................ Test-Bench
Template - ......................................... Test-Bench
Test Bench - .......................................
Test Bench - .................................................................
Modelsim ............... Riviera
................................
..........................................................................................
............................................................................

521
522
524
527
528
529
530
534
535
535
537
543
544
546
552
556
560
564

:8 .......................................................

565

................................................................................
..........................................................
................................................
..........................................................................
................................................
.......................................
................................................................................
.......................................................... LPMs -
........................................................
.............................................................
- ........................................
......................................... generate
......................... generate
............................................ generate
.............................................................................
generate - ........................................................................
if-generate ? ..............................................
..........................................................
.........................................................................
generate ................................... * VHDL-2008 -
.......................................................................................... * Alias
)........................................ * (VHDL-2008

566
567
567
567
570
573
575
576
580
583
584
584
585
587
588
592
595
596
598
599
601
602

VIII

- VHDL

 )...................................... * (VHDL-2008
* .................................................................
* ........................................................
* ..........................................................................
) ( * .........................................
* ........................................................
* ........................................
* ................................
*
* ..............................................................................
* ...........................................................
* ..................................................
................................................ * configuration specifications -
................................................... * configuration declarations -
* ...........................................................
.......................................... * VHDL-93 -
* ..........................................................
.......................................................... * LPM
............................................. * LPMs
.................. * LPMs
- * ...........................................
...................................... * Quartus
Altera * ....
LPM * ........
....................................................................... * Mega-Wizard -

603
605
605
605
607
608
609
611
612
615
619
619
621
623
626
629
632
632
634
636
638
643
644
648
653

:9 ......................................

657

................................................................................
........................................................................
enumerated type ........... type
.................................. * type
............................................ * subtype
* ...................................................................................
) (attributes * ................
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* .............
...........................................................................................
...............................................................
................................................................................
........................................................
...............................................................
.....................................................

658
659
659
662
664
668
671
674
676
677
677
682
684
691
698

- VHDL

IX

? ..............................................
................................................................
.....................
present_state ...........................

702
703
708
711

:10 .........................................

719

................................................................................
............................................................................
..............................................................................
......................................................................
..........................................
....................................................
................................................................................
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* .................................................................................................
.........................
- ...................................................................
.......................................................................
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..................................

720
721
721
722
724
725
733
738
741
747
747
753
756
760

:11 .......................................

767

................................................
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)............................................................... (function call
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* .......................................................
......................................................................... Procedures -
.....................................................................................
..........................................................................
.....................
.................................................................. BFM
....................................................................... * std_logic_1164
............................................................. * std_logic_1164
std_logic * ..............................................................
* ...........................................

768
768
771
773
777
778
779
781
783
785
786
786
789
790
793
795
795
798
805

- VHDL

 signed 805 ............................ * unsigned

signed 815 ...................................................... * unsigned
unsigned 818 .... * signed
std_logic_vector * 819 .........
:12 825 .....................................................................
................................................................................
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bit ........................................................ bit_vector
boolean enumerated data type ..................
.................................. VHDL 93
............................................... * VHDL 87
ROM ..........................................................
..........................................................................................

826
826
829
832
834
835
839
841
844
847
847
847
848
849
851
852
853
855
856
860

867 .................................................................................
VHDL 868 ....................................
Modelsim GUI - 873 .................................................
881 ...........................................................................................

- VHDL

XI

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- VHDL

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- VHDL