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Digital Logic and Families
Digital Logic and Families
1. 2. 3. 4. 5. 6.
Resistor Transistor Logic (RTL) Direct Coupled Transistor Logic (DCTL) Integrated Injection logic (I2L) Diode Transistor Logic (DTL) Transistor Transistor Logic (TTL) High Threshold Logic (HTL)
Non-saturated family
Uni-polar logic
family
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
1. Speed of operation (propagation delay, tpLH and tpHL) 2. power dissipation (power consumption under static condition,
0,1; during the switching intervals or dynamic conditions)
5. Fan-out (No. of gates that gate in HIGH output state can feed without
voltage dropping by more than the allowable noise margin (NM)H)
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
Limitations: - RTL gates cannot switch at the high speeds used by today's computers - These are not designed for linear operation - low noise margin
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
VinA VinB
Vo
L L H H
L H L H
H L L L
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
Transistor to be saturated. Either transistor saturated will cause the output to go low, to 0.2 volts. In figure, the circuit with one of the transistors cutoff, although both saturated would produce the same result. To determining the minimum input current that will keep the transistor in saturation.
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
The output voltage is 5 Volts because the transistor has been shown to be cutoff. VO = 5.0 Volts
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
I3 = (5-0.2)/2.2K = 2.182 mA this current is much less than the maximum saturation current and with no load, the transistor will, indeed, be in saturation. In fact, there is excess capacity in collector saturation current. This excess capacity can be used to sink external load current. This current is called Io or load current. The maximum load current this gate can sink is IoLmax = 12.00 mA - 2.182 mA = 9.818 mA Note that this current is entering the terminal of the gate, hence, is positive.
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
IinL = - 0.82 mA
IinH = 0
Fanout = 11
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
DTL OR gate
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
One of the series diodes is replaced by Q1, providing more base drive for Q2 and improving the fan-out (Nmax= 45)
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
Figure 1
Figure 2
The diode D2 from DTL circuit can be replaced by a transistor whose collector is pulled up to the power supply; transistor Q2 in Figure1. The p-n junction of D2 is replaced by the BE junction of Q2 and with the current gain of the transistor, the current going into the base of Q3 is greatly increased, increasing the fanout.
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
- input diodes and D1 are replaced by the multi-emitter NPN transistor, Q1, - additional modifications to this circuit to improve its performance further. - The analysis of this circuit follows very much the same path as the analysis of the DTL gate. - input transistor, Q1, to act just like two diodes. The transistor Q2, however, will operate in all three regions. The treatment of the output voltages and currents will be treated the same as the DTL gate and Q3 will either be cutoff or saturated, corresponding to an output high and an output low, respectively.
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
Figure 3
ANALYSIS WITH ONE OR MORE INPUTS LOW - With an input low, Q3 should be cutoff. - If Q2 is cutoff, then there can be no current coming out of the collector of Q1, hence its base-collector junction can be modeled as an open circuit. - The base-emitter junction of Q1 will be conducting. The circuit with these models substituted for the transistors (in Figure 3). - Note the similarity to the DTL circuit under the same conditions. The two unused inputs are assumed to be high, and are thus, modeled as open. - VoH = 5 volts with no load, and IinL = -I1 = -(5-0.9)/4K = -1.025 mA
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
ANALYSIS WITH ONE OR MORE INPUTS LOW To finding VInLmax. Vin will be considered as a low as long as Q3 is kept cutoff. If the base voltage for Q3 can be raised to 0.5 Volts without turning it on, then there will be 0.5 mA current in the 1K resistor. This current can only come from Q2, which means it must be conducting. Assuming all this 0.5 mA comes through the collector of Q2, the voltage drop across the 1.4 K resistor will be 0.7 Volts, not enough to cause the transistor to saturate. Thus, the active model for Q2 is appropriate as shown in Figure 4. If =30, base current in Q2 is
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
ANALYSIS WITH ONE OR MORE INPUTS LOW Because this current is coming out of the collector of Q1, the basecollector junction of Q1 is on, and is modeled as a diode in Figure 4. The voltage at B1, the base of Q1, is VB1 = 0.5 + 0.7 + 0.7 = 1.9 Volts
The current coming down through the 4 K resistor, I1, is I1= (5.0-1.9) / 4K = 0.775mA
This is considerably more than is going into the base of Q2, therefore, the input BE junction of Q1 will also still be conducting. The maximum voltage at the input is VinLmax = 1.9 - 0.7 = 1.2 Volts
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
CALCULATIONS WITH INPUT HIGH Both Q2 and Q3 are modeled as saturated, an assumption that must be verified. With the inputs high, Q1 is modeled as two diodes with the B-E diodes cutoff, and B-C diode conducting. The voltage at the base of Q1 is VB1 = 0.8 + 0.8 + 0.7 = 2.3 Volts. The current down through the 4 K resistor, I1 = (5.0-2.3) / 4K = 0.675mA
Figure 5 TTL gate circuit model with all inputs high
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
CALCULATIONS WITH INPUT HIGH All this current goes into the base of Q2. IB2 = 0.675 mA
If Q2 is saturated, voltage at its collector terminal is VC2 = 0.8 + 0.2 = 1.0 Volts And the collector current is IC2 = I2 = (5.0 1.0) / 1.4K = 2.857mA
If = 30, B2 > IC2 , and, therefore, Q2 is saturated.
The current coming out of the emitter of Q2 is the sum of the base and collector currents. Part of this current will go down through the 1 K resistor to ground and the rest will enter the base of Q3. IB3 = IB2 + IC2 - I3 = 0.675 + 2.857 - 0.8 = 2.732 mA
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
The maximum collector current that Q3 can carry and still be in saturation is IB3 = 81.96 mA, assuming =30. The maximum current the gate can sink when the output is low IoLmax = ICsatmax - I4 = 81.96 - 1.2 = 80.76 mA
The input voltage to be high as long as no current goes out the input terminal. Thus, to keep the input voltage high enough so that the B-E p-n junction of Q1 does not turn on. Thus, VinHmin = 2.3 - 0.6 = 1.7 Volts
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
TTL FAMILIES As the designers of TTL gates became more sophisticated, they developed modifications which would provide special characteristics. The original series of TTL was designated as 74XX, where the XX is replaced by logic function ( 00 is a quadruple 2input NAND, 04 is a hex inverter, etc.) The 74LXX series is a low power family. 74HXX is a high speed family. 74SXX is a family based on Schottky diodes and transistors. 74LSXX is a family of low power Schottky. A 54xXX is also provided as a companion family to the 74xXX families. The 54... families are identical to the 74... families, except for operating temperature range and tolerance on power supply voltage.
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
Fanout
Standard Low-power High-speed Schottky Low-power Schottky Advanced Schottky Advanced low-power Schottky
10 20 10 10 20
40 20
10 1 22 19 2
10 1
9 33 6 3 9.5
1.5 4
90 33 132 57 19
15 4
Department of Electronics and Computer Engineering Pulchowk Campus, Institute of Engineering, T.U.
Emitter Coupled Logic (ECL) ECL gates use differential amplifier configurations at the input stage. A bias configuration supplies a constant voltage at the midrange of the low and high logic levels to the differential amplifier, so that the appropriate logical function of the input voltages will control the amplifier and the base of the output transistor. The propagation time for this arrangement can be less than a nanosecond, making it for many years the fastest logic family. ECL family include the fact that the large current requirement is approximately constant, and does not depend significantly on the state of the circuit. This means that ECL circuits generate relatively little power noise, unlike many other logic types which typically draw far more current when switching than quiescent, for which power noise can become problematic. In an ALU - where a lot of switching occurs - ECL can draw lower mean current than CMOS.
introduced it had speed comparable to TTL yet was almost as low power as
CMOS, making it ideal for use in VLSI (and larger) integrated circuits. The logic voltage levels are very close (High: 0.7V, Low: 0.2V), I2L has high noise immunity because it operates by current instead of voltage. I2L, sometimes also called Merged Transistor Logic (MTL), is relatively
Integrated Injection Logic (I2L) Important features are: - The circuit uses BJTs, both pnp and npn. Therefore operating speed is quite high. - The circuit is similar to RTL, except that there are no base resistors used. This minimizes the circuit area and simplifies the circuit layout. - All the gate transistors are operated in the inverted mode. Not only does this facilitate the use of low voltage supply for the circuit. - The circuit requires no isolation unlike the previous digital ICs. This facilitates higher packing density and also reduces the fabrication cost, as fewer masks (e.g. only four) are required for the complete process. - Parasitics in the circuit are greatly reduced. This also improves the operating speed of the IC.