entity alu is

port(a,b:in bit_vector(3 downto 0);z:out bit_vector(3 downto 0));

end alu;
--entity mux2x1 is
-- port(m,n:in bit_vector(3 downto 0);o:out bit_vector(3 downto 0));
--end mux2x1;
architecture alu_arch of alu is
component mux
port(p,q:in bit_vector(3 downto 0);ctrl:in bit;z:out bit_vector(3 downto 0));
end component;
--signal s1,s2:bit_vector(3 downto 0);
begin
process(a,b)
variable s1,s2:bit_vector(3 downto 0);
s1(0):= a(0) and b(0);
s1(1):= a(1) and b(1);
s1(2):= a(2) and b(2);
s1(3):= a(3) and b(3);
s2(0):= a(0) or b(0);
s2(1):= a(1) or b(1);
s2(2):= a(2) or b(2);
s2(3):= a(3) or b(3);
m1:mux port map(s1,s2,ctrl,z);
end process;
end alu_arch;