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    AIM: To Design and Simulate VHDL Code For 4:2 Encoder

    Uploaded by

    Nitesh Arora
    The document describes a VHDL code for a 4:2 priority encoder. The code defines an entity with a 4-bit input and 2-bit output and an enable bit. It uses a case statement to assign the output based on the priority of the input bits, with '1' taking highest priority. A testbench is also defined to simulate and test the encoder by applying different inputs over time.

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    AIM: To Design and Simulate VHDL Code For 4:2 Encoder

    Uploaded by

    Nitesh Arora
    37 views5 pages
    The document describes a VHDL code for a 4:2 priority encoder. The code defines an entity with a 4-bit input and 2-bit output and an enable bit. It uses a case statement to assign the output based on the priority of the input bits, with '1' taking highest priority. A testbench is also defined to simulate and test the encoder by applying different inputs over time.

    Original Description:

    Original Title

    VHDL 9,10

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    The document describes a VHDL code for a 4:2 priority encoder. The code defines an entity with a 4-bit input and 2-bit output and an enable bit. It uses a case statement to assign the output based on the priority of the input bits, with '1' taking highest priority. A testbench is also defined to simulate and test the encoder by applying different inputs over time.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    37 views5 pages

    AIM: To Design and Simulate VHDL Code For 4:2 Encoder

    Uploaded by

    Nitesh Arora
    The document describes a VHDL code for a 4:2 priority encoder. The code defines an entity with a 4-bit input and 2-bit output and an enable bit. It uses a case statement to assign the output based on the priority of the input bits, with '1' taking highest priority. A testbench is also defined to simulate and test the encoder by applying different inputs over time.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    of 5

    AIM: To design and simulate VHDL code for 4:2 encoder.

    CODE:
    library ieee;
    use ieee.std_logic_1164.all;
    entity en is
    port(y:in bit_vector(3 downto 0);x:out bit_vector(1 downto 0);v:out bit);
    end entity;
    architecture en1 of en is
    begin
    process(y)
    begin
    case y is
    when "1000" => x<="11" ; v<='1';
    when "0100" => x<="10" ; v<='1';
    when "0010" => x<="01" ; v<='1';
    when "0001" => x<="00" ; v<='1';
    when "0000" => x<="00" ; v<='0';
    when others =>NULL;
    end case;
    end process;
    end architecture;
    entity testbench is
    end entity;
    architecture tb of testbench is
    signal y1:bit_vector(3 downto 0);
    signal x1:bit_vector(1 downto 0);
    signal v1:bit;
    begin
    process
    begin
    y1<="1000";
    wait for 100ns;
    y1<="0100";
    wait for 100ns;
    y1<="0010";
    wait for 100ns;
    y1<="0001";
    wait for 100ns;

    y1<="0000";
    wait for 100ns;
    end process;
    p1:entity work.en port map(y1,x1,v1);
    end;

    OUTPUT:

    AIM: To design and simulate VHDL code for 4:2 priority encoder.
    CODE:
    library ieee;
    use ieee.std_logic_1164.all;
    entity en is
    port(y:in bit_vector(3 downto 0);x:out bit_vector(1 downto 0);v:out bit);
    end entity;
    architecture en1 of en is
    begin
    process(y)
    begin
    if (y(3)='1') then
    x<="11" ; v<='1';
    elsif (y(2)='1') then
    x<="10" ; v<='1';
    elsif (y(1)='1') then
    x<="01" ; v<='1';
    elsif (y(0)='1') then
    x<="00" ; v<='1';
    elsif (y(0)='0') then
    x<="00" ; v<='0';
    end if;
    end process;
    end architecture;

    entity testbench is
    end entity;
    architecture tb of testbench is
    signal y1:bit_vector(3 downto 0);
    signal x1:bit_vector(1 downto 0);
    signal v1:bit;
    begin
    process
    begin

    y1<="0000";
    wait for 100ns;
    y1<="0001";
    wait for 100ns;
    y1<="0010";
    wait for 100ns;
    y1<="0011";
    wait for 100ns;
    y1<="0100";
    wait for 100ns;
    y1<="0101";
    wait for 100 ns;
    y1<="0110";
    wait for 100 ns;
    y1<="0111";
    wait for 100ns;
    y1<="1000";
    wait for 100 ns;
    y1<="1001";
    wait for 100 ns;
    y1<="1010";
    wait for 100 ns;
    y1<="1011";
    wait for 100 ns;
    y1<="1100";
    wait for 100 ns;
    y1<="1101";
    wait for 100 ns;
    y1<="1110";
    wait for 100 ns;
    y1<="1111";
    wait for 100ns;
    end process;
    p1:entity work.en port map(y1,x1,v1);
    end;

    OUTPUT:

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