module reg_piso

(data_in, load, shift, rl, reset_n, clk, data_out, data_valid, data, eoc, cnt);

input input input input input input output output output output output reg reg reg reg reg

[7:0]data_in; load; shift; rl; reset_n; clk; data_out; data_valid; eoc; [7:0]data; [3:0]cnt;

data_out; data_valid; eoc; [7:0]data; [3:0]cnt;

always@(posedge clk or negedge reset_n) begin if(reset_n==0) begin data_out<=0; data_valid<=0; eoc=0; end else if (load==1) begin data<=data_in; data_out<=0; data_valid<=0; eoc<=0; cnt<=4'b1000; end else if(shift==1&&cnt!=0) begin data<=rl?data>>1:data<<1; data_out<=rl?data[0]:data[7]; data_valid<=1; eoc<=0; cnt<=cnt-1'b1; end

else if(shift==1&&cnt==0) begin data_out<=0; data_valid<=0; eoc<=1; end else ; end endmodule