module systemtask (d,clk,q,reset_n,q_n); input d,clk,reset_n; output q,q_n; reg q,q_n; always@(posedge clk,negedge reset_n) begin if (reset_n==0) begin

q<=0; q_n<=1; end else begin q<=d; q_n<=!d; end end endmodule