module systemtask_tb;

reg clk,reset_n,d;
wire q,q_n;
systemtask a1 (d,clk,q,reset_n,q_n);
initial
begin
clk=1'b0;
reset_n=1'b0;
d=1'b0;
end
always
#10 clk=~clk;
initial
begin
#10
reset_n=1'b1;
d=1'b1;
#20
$monitor($time,"the value of d=%b",d,"the value of reset_n=%b",reset_n,"q=%b",
q);
#20
reset_n=1'b1;
d=1'b0;
#20
reset_n=1'b0;
d=1'b1;
#20
$stop;
end
endmodule