B.

Tech V Semester MOS-LSI LAB

Lab Assignment Sheet

Assignment.5 Consider a CMOS NAND gate with following parameter KP = KN = 100 A/V2 VTN = 1 V and VTP = -1.0 There are three cases 1) Two input switching simultaneously 2) Top NMOS switching while the bottom NMOS is tied to VDD 3) Top NMOS is tied to VDD and bottom NMOS is switching a) c) Drive an analytical expression for VTH for first case and find the value of VTH with VDD = 5 V b) Determine the value of VTH for all cases using SPICE For CLOAD = 0.2 pf calculate 50% delay P . For an ideal input signals assuming that the CLOAD includes all of the internal parasitic capacitance verify the result with SPICE

Assignment.6 Calculate the VTH using SPICE for a two input NOR gate fabricated with CMOS technology parameter of NMOS and PMOS are follows (W/L)N = 4 (W/L)P = 1

VTN = 0.7 V and VTP = -0.7 V n COX = 40 A/V2 p COX = 20 A/V2 VDD = 5 V Case 1. Both NMOS and PMOS switches Case 2. Lower PMOS tied to 0 Case 3. Upper PMOS tied to 0