Data flow & Behavioral Modeling

DATA FLOW MODELING

Continuous assignment: wire c,a,b; assign c=a + b; Implicit continuous assignment: wire c = a & b; Delays: //regular delay assignment wire c,a,b; assign #5 c = a + b; // Implicit continuous assignment delay wire #5 c = a + b; // net declaration delay wire #5 c; // delay specified on net. assign c = a + b;

Expressions,operators,operands
describes system in terms of expressions instead of primitive gates. Expression formed using operands & operators. Operands are data types used in expression.they are : constant,parameter,net,register,bit select,part select,memory element. eg., c= a+ b => a, b,c operands Operators act on operand to produce desired result.

LOGICAL OPERATORS
&& logical AND || logical OR ! logical NOT Operands evaluated to ONE bit value: 0, 1 or x Result is ONE bit value: 0, 1 or x
A = 6; B = 0; C = x; A && B A || !B C || B 1 && 0 1 || 1 x || 0 0 1 x but C&&B=0

BITWISE OPERATORS (I)

& bitwise AND | bitwise OR ~ bitwise NOT ^ bitwise XOR ~^ or ^~ bitwise XNOR Operation on bit by bit basis

Bitwise Operators (ii)

c = ~a; c = a & b;

a = 4b1010; b = 4b1100;
c = a ^ b;

a = 4b1010; b = 2b11;

REDUCTION OPERATORS
& | ^ ~& ~| ~^ or ^~
AND

OR
XOR NAND NOR XNOR

One multi-bit operand

One single-bit result

a = 4b1001; .. c = |a; // c = 1|0|0|1 = 1

SHIFT OPERATORS
>> <<
shift right shift left

Result is same size as first operand, always

zero filled
a = 4b1010; ... d = a >> 2; // d = 0010 c = a << 1; // c = 0100

CONCATENATION OPERATOR
{op1, op2, ..} concatenates op1, op2, .. to single number Operands must be sized !!
reg a; reg [2:0] b, c; .. a = 1b 1; b = 3b 010; c = 3b 101; catx = {a, b, c}; caty = {b, 2b11, a}; catz = {b, 1}; Replication .. catr = {4{a}, b, 2{c}};

// catx = 1_010_101 // caty = 010_11_1 // WRONG !! // catr = 1111_010_101101

RELATIONAL OPERATORS
> < >= <=
greater than less than greater or equal than less or equal than

Result is one bit value: 0, 1 or x

1 > 0

b1x1 <= 0
10 < z

1 x x

EQUALITY OPERATORS
== != === !==

logical equality logical inequality case equality case inequality

Return 0, 1 or x Return 0 or 1

4b 1z0x == 4b 1z0x 4b 1z0x != 4b 1z0x 4b 1z0x === 4b 1z0x 4b 1z0x !== 4b 1z0x

x x 1 0

CONDITIONAL OPERATOR
cond_expr ? true_expr : false_expr

Like a 2-to-1 mux ..

A B 1 0 Y

Y = (sel)? A : B;

se l

Arithmetic Operators (i)

Arithmetic Operators (ii)

Arithmetic Operators (iii)

Arithmetic Operators (iv)

Operator Precedence

Use parentheses to enforce your priority

CONTINUOUS ASSIGNEMENTS A
CLOSER LOOK

Syntax:
assign #del <id> = <expr>;
option al net type !!

Where to write them:

inside a module outside procedures

Properties:
they all execute in parallel are order independent are continuously active

Example: Half Adder

A B C wire S, C, A, B; S module half_adder(S, C, A, B); output S, C; input A, B;

A
B Half Adder

S
C

assign S = A ^ B; assign C = A & B; endmodule

Multiplexer

BEHAVIORAL MODEL PROCEDURES (I)

Procedures = sections of code that we know they execute sequentially Procedural statements = statements inside a procedure (they execute sequentially) e.g. another 2-to-1 mux implem:
Executio n Flow

begin if (sel == 0) Procedural Y = B; assignments: Y must be reg !! else Y = A; end

BEHAVIORAL MODEL PROCEDURES (II)

Modules can contain any number of procedures
Procedures execute in parallel (in respect to each other) and .. .. can be expressed in two types of blocks:
initial
always finishes)

they execute only once

they execute for ever (until simulation

INITIAL BLOCKS
Start execution at sim time zero and finish when their last statement executes
module nothing; initial $display(Im first); initial begin #50; $display(Really?); end endmodule

Will be displayed at sim time 0

Will be displayed at sim time 50

ALWAYS BLOCKS
Start execution at sim time zero and continue until sim finishes

EVENTS (I)
@
always @(signal1 or signal2 or ..) begin execution triggers .. end every

always @(posedge clk) begin .. end

time any signal changes execution triggers every time clk changes from 0 to 1 execution triggers every time clk changes from 1 to 0

always @(negedge clk) begin .. end

Examples
3rd half adder implem
module half_adder(S, C, A,
B); output S, C; input A, B;

Behavioral edge-triggered DFF implem

module dff(Q, D, Clk); output Q; input D, Clk;
reg Q; wire D, Clk; always @(posedge Clk) Q = D; endmodule

reg S,C; wire A, B; always @(A or B) begin S = A ^ B; C = A && B; end endmodule

EVENTS (II)
wait (expr)
always begin wait (ctrl) execution loops every #10 cnt = cnt + 1; time ctrl = 1 (level #10 cnt2 = cnt2 + 2;
end

sensitive timing control)

e.g. Level triggered DFF ?

Example
re s Y always @(res or posedge clk) begin if (res) begin Y = 0; W = 0; end else begin Y = a & b; W = ~c; end end

a b

c clk

Timing (i)
d

initial begin #5 c = 1; #5 b = 0; #5 d = c; end

c b 0 5 Time 1 0 1 5

Each assignment is blocked by its previous one

Timing (ii)
d initial begin fork #5 c = 1; #5 b = 0; #5 d = c; join end Assignments are not blocked here c b 0 5 Time 1 0 1 5

PROCEDURAL ASSIGNMENT
Assignment statement within an initial or an always statement . 2 kinds :i)blocking assignments (ii)non-blocking Blocking: = operator is used. statements executed in they order they are specified. reg a = 2b 11; reg b = reg a Non-blocking: <= operator used allows scheduling without blocking execution of statements in sequential block. always @ (posedge clk) begin reg1 <= in1; reg2 <= reg 1;//old value of reg1 end

TIMING CONTROLS
Provides simulation time at which procedural statements execute. 3 forms:1)delay based(2)event(3)level sensitive Delay : i)regular :time between when statement is encountered and when executed. # 3 a=2b11; ii)intra-assignment :assignment to right x = 0;z=0; y = #10 x+z; iii)zero delay : statement executed last # 0 x=1; Level sensitive: waits for certain condition to be true before statement wait(enable) # 20 c=c+1;

CONTD.,
Event based timing control: change in value on reg or net.
Regular event: @(clk) q=d; Event or control:-transition on any one of multiple signals. always @ ( rst or clk or d) - Named event : declared by keyword event, triggered by symbol.

BLOCK STATEMENTS
Used to group multiple statement to act together. Sequential block: begin and end executed sequentially. Parallel block : fork and join executed concurrently. ordering controlled by delay. reg x,y; reg[1:0]z,w; initial fork x=1b0; #5 y=1b1; # 10 z = {x,y}; # 20 w = {y,x}; join

Procedural Statements: if
E.g. 4-to-1 mux:

if (expr1) true_stmt1; else if (expr2) true_stmt2; .. else def_stmt;

module mux4_1(out, in, sel); output out; input [3:0] in; input [1:0] sel; reg out; wire [3:0] in; wire [1:0] sel;

always @(in or sel) if (sel == 0) out = in[0]; else if (sel == 1) out = in[1]; else if (sel == 2) out = in[2]; else out = in[3]; endmodule

Procedural Statements: case

E.g. 4-to-1 mux:

case (expr) item_1, .., item_n: stmt1; item_n+1, .., item_m: stmt2; .. default: def_stmt; endcase

module mux4_1(out, in, sel); output out; input [3:0] in; input [1:0] sel; reg out; wire [3:0] in; wire [1:0] sel; always @(in or sel) case (sel) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcase endmodule

Procedural Statements: for

for (init_assignment; cond; step_assignment) stmt;
E.g.
module count(Y, start); output [3:0] Y; input start; reg [3:0] Y; wire start; integer i;

initial
Y = 0; always @(posedge start) for (i = 0; i < 3; i = i + 1) #10 Y = Y + 1; endmodule

Procedural Statements: while

E.g.
module count(Y, start); output [3:0] Y; input start; reg [3:0] Y; wire start; integer i;

while (expr) stmt;

initial Y = 0; always @(posedge start) begin i = 0; while (i < 3) begin #10 Y = Y + 1; i = i + 1; end end endmodule

Procedural Statements: repeat

E.g.
module count(Y, start); output [3:0] Y; input start; reg [3:0] Y; wire start; initial

repeat (times) stmt;

Can be either an integer or a variable

Y = 0; always @(posedge start) repeat (4) #10 Y = Y + 1; endmodule

Procedural Statements: forever

Typical example: clock generation in test modules
module test; reg clk;

Tclk = 20 time units

forever stmt;
Executes until sim finishes

initial begin clk = 0; forever #10 clk = ~clk; end

other_module1 o1(clk, ..); other_module2 o2(.., clk, ..); endmodule

Mixed Model
Code that contains various both structure and behavioral styles
module simple(Y, c, clk, res); output Y; input c, clk, res;

re s c clk n Y

reg Y; wire c, clk, res; wire n;

not(n, c); // gate-level always @(res or posedge clk) if (res) Y = 0; else Y = n; endmodule