Combining two 2-4 decoders to form one 3-8 decoder using enable switch

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module dec38(o,i); output [7:0]o; input [2:0]i; wire x; inv u1(x,i[2]); decoder24 u2(o[3:0],i[1],i[0],x); decoder24 u3(o[7:4],i[1],i[0],i[2]); endmodule Dataflow model in vhdl entity decod1 is Port ( I0 : in STD_LOGIC; I1 : in STD_LOGIC; En : in STD_LOGIC; Y : out STD_LOGIC_VECTOR (3 downto 0)); end decod1; architecture Behavioral of decod1 is begin process(I0,I1,En) begin if(En='1') then Y(0)<=(not I0) and (not I1); Y(1)<=(not I0) and I1; Y(2)<=I0 and (not I1); Y(3)<=I0 and I1; else Y<="0000"; end if; end process; end Behavioral; Write a VHDL Program to generate Mod- 10 up counter.libraryIEEE;useIEEE.STD_LOGI C_1164. ALL; ENTITYCounter IS PORT(clk:in std_logic; reset:in std_logic; q:out std_logic_vec tor (3downto0)); ENDCounter; ARCHITECTURECounter OFCounter IS BEGIN PROCESS(clk,reset) VARIABLEqtemp:std_logic_vector (3downto0); BEGIN IFreset='1'THEN qtemp:="0000"; ELSEif clk'eventandclk='1'then if qtemp<9then qtemp:=qtemp+1;e lseqtemp:="0000"; end if ; end if ;

q<=qtemp; END IF; END PROCESS;ENDCounter; EXPERIMENT:Write a VHDL Program to implement a 4 bit addition/subtraction . libraryIEEE;useIEEE.STD_LOGIC_1164.ALL; useIEEE.STD_LOGIC_ARITH.ALL; useIEEE.STD _LOGIC_UNSIGNED.ALL; PACKAGEmy_packageIS CONSTANT ADDER _WIDTH :integer:= 5; CO NSTANT RESULT _WIDTH :integer:= 6; SUBTYPEADDER_VALUEIS integer RANGE0TO2 ** ADD ER_WIDTH - 1; SUBTYPERESULT_VALUEIS integer RANGE0TO2 ** RESULT_WIDTH - 1; ENDmy _package;LIBRARYieee;USEieee.std_logic_1164.ALL; USEwork.my_package.ALL; ENTITYa ddsubIS PORT(a:INADDER_VALUE; b:INADDER_VALUE;addnsub:IN STD_LOGIC; result:OUTR ESULT_VALUE );ENDaddsub;ARCHITECTURErtlOFaddsubIS BEGINPROCESS(a, b, addnsub)BE GINIF(addnsub = '1')THEN result <= a + b;ELSEresult <= a - b;END IF; END PROCES S; ENDrtl;