H8SX 1582 Tiếng Việt

I HC QUC GIA TP.
HCM TRNG I HC BCH KHOA KHOA KHOA HC V K THUT MY TNH ------------------
VI IU KHIN H8SX/1582
TP.H CH MINH,THNG 12 - 2007
MC LC NI DUNG
Chng 1 Tng quan ........................................................................................................... 1 1.1 Cc tnh cht ................................................................................................................ 1 1.2 S khi .................................................................................................................... 1 1.3 Chn ca H8SX/1582 ................................................................................................. 2 Chng 2 CPU ................................................................................................................... 19 2.1 Cc tnh nng ............................................................................................................. 19 2.2 Cc ch hot ng ca CPU ................................................................................. 21 2.3 c lnh ..................................................................................................................... 26 2.4 Khng gian a ch ..................................................................................................... 26 2.5 Cc thanh ghi ............................................................................................................. 26 2.6 nh dng d liu ...................................................................................................... 31 2.7 Tp lnh ..................................................................................................................... 33 Chng 3 Cc ch hot ng ca MCU ..................................................................... 61 3.1 Chn la ch hot ng ........................................................................................ 61 3.2 c t Thanh ghi........................................................................................................ 61 3.3 Cc c t ch hot ng ...................................................................................... 65 3.4 nh x a ch ............................................................................................................ 65 Chng 4 X l ngoi l.................................................................................................... 67 4.1 Cc kiu x l ngoi l v u tin ........................................................................ 67 4.2 Ngun ngoi l v bng vector x l ngoi l ........................................................... 67 4.3 Reset .......................................................................................................................... 69 4.4 Theo di ..................................................................................................................... 71 4.5 Sai a ch .................................................................................................................. 71 4.6 Ngt qung ................................................................................................................. 73 4.7 X l ngoi l cu lnh .............................................................................................. 74 4.8 Trng thi stack sau khi x l ngoi l ...................................................................... 76 4.9 Ch khi s dng ...................................................................................................... 76 Chng 5 B iu khin ngt qung ............................................................................... 78 5.1 Cc c tnh ............................................................................................................... 78 5.2 Cc chn xut/nhp .................................................................................................... 79 5.3 Cc m t thanh ghi ................................................................................................... 79 5.4 Ngun ngt qung ...................................................................................................... 90 5.5 Bng vector x l ngt qung ................................................................................... 91 5.6 Cc ch iu khin ngt qung v tc v ngt qung ........................................... 96 5.8 Ch khi s dng .................................................................................................... 107 Chng 6 Cc cng xut nhp ....................................................................................... 109 6.1 c t cc thanh ghi................................................................................................. 116 6.2 iu khin buffer xut ............................................................................................. 121 6.3 B iu khin chc nng ca cng .......................................................................... 147 6.4 Cc ch cch s dng ........................................................................................... 152 Chng 7 B nh thi 16-bit (TPU) ............................................................................. 154 7.1 Cc tnh cht ............................................................................................................ 154 7.2 Cc chn xut nhp .................................................................................................. 162 7.3 c t thanh ghi ....................................................................................................... 166 7.4 Hot ng ................................................................................................................ 204 7.5 Cc ngun ngt qung ............................................................................................. 226
7.6 S kch hot DTC .................................................................................................... 230 7.7 S kch hot b iu kin DMA (DMAC) .............................................................. 230 7.8 S kch hot trnh chuyn i A/D .......................................................................... 230 7.9 Operation Timing (nh gi cc hot ng) ............................................................ 230 7.10 Ch cch s dng ............................................................................................... 236 Chng 8 B chuyn tun t - s (A/D) ........................................................................ 243 8.1 Cc c im ........................................................................................................... 243 8.2 Cc chn nhp/xut .................................................................................................. 245 8.3 M t thanh ghi ........................................................................................................ 246 8.4 Hot ng ................................................................................................................ 252 8.5 Ngun ngt qung .................................................................................................... 256 8.6 nh ngha chnh xc vic chuyn A/D .............................................................. 256 8.7 Chc nng pull-down ca port tng t .................................................................. 258 8.8 Ch khi s dng .................................................................................................... 258 Chng 9 B iu khin DMA (DMAC) ....................................................................... 262 9.1 Cc tnh cht ............................................................................................................ 262 9.2 Cc c t thanh ghi................................................................................................. 264 9.3 Cc ch chuyn d liu ....................................................................................... 281 9.4 Cc hot ng .......................................................................................................... 282 9.5 Kt thc truyn DMA .............................................................................................. 314 9.6 Mi quan h gia DMAC v cc thnh phn s dng bus khc ............................. 316 9.7 Cc ngun ngt ........................................................................................................ 317 9.8 Ch s dng .......................................................................................................... 320 Chng 10 B iu khin truyn d liu DTC ............................................................. 322 10.1 Cc tnh nng ......................................................................................................... 322 10.2 c t thanh ghi ..................................................................................................... 323 10.3 Cc ngun kch hot .............................................................................................. 331 10.4 V tr ca thng tin truyn ti v bng vector DTC ............................................... 331 10.5 Hot ng .............................................................................................................. 335 10.6 Quy trnh s dng DTC ......................................................................................... 348 10.7 V d s dng DTC ............................................................................................... 349 10.8 Ngun ngt ............................................................................................................ 352 10.9 Ch s dng ........................................................................................................ 352 Chng 11 B pht sinh xung clock kh lp trnh (PPG) ........................................... 354 11.1 Cc tnh cht .......................................................................................................... 354 11.2 Cc chn xut/nhp ................................................................................................ 354 11.3 Cc c t thanh ghi............................................................................................... 355 11.4 Hot ng .............................................................................................................. 362 11.5 Ch s dng ........................................................................................................ 369 Chng 12 Giao din giao tip tun t (SCI) ............................................................... 370 12.1 c im ................................................................................................................ 370 12.2 Cc chn xut/nhp ................................................................................................ 371 12.3 M t thanh ghi ...................................................................................................... 371 12.4 Hot ng trong ch bt ng b...................................................................... 391 12.5 Chc nng giao tip a x l ................................................................................. 401 12.6 Hot ng trong ch ng b clock .................................................................. 405 12.7 Hot ng trong ch giao din smart card ........................................................ 411 12.8 Ngun ngt qung .................................................................................................. 420 12.9 Ch s dng ........................................................................................................ 422
Chng 13 B giao tip tun t ng b (SSU) .......................................................... 427 13.1 c im ................................................................................................................ 427 13.2 Cc chn xut nhp ................................................................................................ 428 13.3 M t thanh ghi ...................................................................................................... 429 13.4 Hot ng .............................................................................................................. 440 13.5 Yu cu ngt qung ............................................................................................... 456 13.6 Ch s dng ........................................................................................................ 458 Chng 14 B iu khin bus (BSC) ............................................................................. 459 14.1 Cc c im ......................................................................................................... 459 14.2 M t thanh ghi ...................................................................................................... 459 14.3 Cu hnh bus .......................................................................................................... 460 14.4 Chc nng multi-clock .......................................................................................... 461 14.5 Bus ni ................................................................................................................... 462 14.6 Hot ng b m d liu ghi ............................................................................... 463 14.7 Phn quyn bus ...................................................................................................... 463 14.8 Hot ng ca b iu khin bus trong khi Reset ................................................. 465 14.9 Ch s dng ........................................................................................................ 465 Chng 15 RAM .............................................................................................................. 466 Chng 16 B nh Flash................................................................................................. 467 16.1 Cc tnh cht .......................................................................................................... 467 16.2 S chuyn ch .............................................................................................. 468 16.3 Cu hnh vng b nh MAT .................................................................................. 470 16.4 Cu trc ca cc khi (block) ................................................................................ 471 16.5 Giao din Lp trnh/xa ......................................................................................... 472 16.6 Cc chn xut/nhp ................................................................................................ 474 16.7 c t thanh ghi ..................................................................................................... 474 16.8 Ch lp trnh on-board ...................................................................................... 493 16.9 Bo v .................................................................................................................... 513 16. 10 M phng b nh flash s dng RAM ............................................................... 515 16.11 Vic chuyn i gia vng user MAT v user boot MAT .................................. 517 16.12 Ch programmer ............................................................................................. 518 16.13 c im k thut chun giao din giao tip tun t cho ch boot ................ 518 16.14 Ch s dng ...................................................................................................... 542 Chng 17 B nh thi watchdog (WDT) ................................................................... 544 17.1 c im ................................................................................................................ 544 17.2 c t thanh ghi ..................................................................................................... 544 17.3 Hot ng .............................................................................................................. 547 17.4 Ngun ngt qung .................................................................................................. 549 17.5 Ch s dng ........................................................................................................ 549
MC LC HNH
Hnh 1.1 S khi ca H8SX/1582 ........................................................................................ 2 Hnh 1.2 Cc Chn ca H8SX/1582 .......................................................................................... 3 Hnh 2.1 Cc ch hot ng ca CPU ................................................................................ 21 Hnh 2.2 Bng vector ngoi l (Ch bnh thng) ............................................................. 22 Hnh 2.3 Cu trc Stack (Ch bnh thng) ....................................................................... 22 Hnh 2.4 Bng vector ngoi l ( ch nng cao v trung bnh) .......................................... 24 Hnh 2.5 Cu trc ca Stack (Ch trung bnh v nng cao) ............................................... 24 Hnh 2.6 Bng vector ngoi l (ch ti a) ......................................................................... 25 Hnh 2.7 Cu trc Stack (Ch ti a).................................................................................. 25 Hnh 2.8 Bn b nh ........................................................................................................... 26 Hnh 2.9 Cc thanh ghi ca CPU ............................................................................................. 27 Hnh 2.10 Cch s dng cc thanh ghi .................................................................................... 28 Hnh 2.11 Stack ....................................................................................................................... 28 Hnh 2.12 nh dng d liu thanh ghi a dng ..................................................................... 32 Hnh 2.13 nh dng d liu b nh ....................................................................................... 33 Hnh 2.14 nh dng cu lnh ................................................................................................. 52 Hnh 2.15 c t a ch r nhnh trong b nh ...................................................................... 57 Hnh 2.16 S chuyn i trng thi ......................................................................................... 60 Hnh 3.1 trnh by Bn a ch ............................................................................................ 66 Hnh 4.1 Chui hnh ng khi reset ........................................................................................ 71 Hnh 4.2 Trng thi stack sau khi x l ngoi l ..................................................................... 76 Hnh 4.3 Tc v xy ra khi gi tr SP l s l .......................................................................... 77 Hnh 5.1 S khi ca b x l ngt qung ......................................................................... 79 Hnh 5.2 S khi ca cc ngt qung IRQn ....................................................................... 91 Hnh 5.3 lu ca th tc chp nhn ngt qung trong ....................................................... 98 Hnh 5.4 S dng chy ca th tc chp nhn ngt qung trong ch iu khin ngt qung 0 .................................................................................................................................. 100 Hnh 5.5 Qu trnh x l ngt qung ..................................................................................... 100 Hnh 5.6 S khi ca DMAC v b iu khin ngt qung ............................................. 103 Hnh 5.7 Xung t gia to v cm ngt qung .................................................................... 107 Hnh 6.1 S khi ............................................................................................................... 117 Hnh 7.1 S khi ca TPU (b nh thi 0)...................................................................... 161 Hnh 7.2 S khi ca TPU (b nh thi 1)...................................................................... 162 Hnh 7.3 V d ca qu trnh thit lp hot ng m........................................................... 205 Hnh 7.4 Hot ng m t do .............................................................................................. 206 Hnh 7.5 Hot ng m tun hon ....................................................................................... 206 Hnh 7.6 V d ca mt qu trnh thit lp cho mt dng sng xut thng qua mt compare match ..................................................................................................................................... 207 Hnh 7.7 V d v hot ng xut 0 v xut 1 ....................................................................... 207 Hnh 7.8 V d v hot ng o tn hiu xut ...................................................................... 208 Hnh 7.9 V d v qu trnh thit lp cho hot ng input capture. ...................................... 208 Hnh 7.10 V d v hot ng input capture.......................................................................... 209 Hnh 7.11 V d v qu trnh thit lp hot ng ng b .................................................... 210 Hnh 7.12 V d v hot ng ng b.................................................................................. 211 Hnh 7.13 Hot ng compare match buffer ......................................................................... 212
Hnh 7.14 Hot ng input capture buffer ............................................................................. 212 Hnh 7.15 V d v qu trnh thit lp hot ng buffer. ...................................................... 212 Hnh 7.16 V d ca hot ng buffer (1) ............................................................................. 213 Hnh 7.17 V d ca hot ng buffer (2) ............................................................................. 214 Hnh 7.18 V d v qu trnh thit lp hot ng cascaded ................................................... 215 Hnh 7.19 V d v hot ng cascaded (1) .......................................................................... 215 Hnh 7.20 V d v hot ng cascaded (2) .......................................................................... 216 Hnh 7.21 V d v qu trnh thit lp ch PWM. ............................................................ 218 Hnh 7.22 V d hot ng ca ch PWM (1) .................................................................. 219 Hnh 7.23 V d hot ng ca ch PWM (2) .................................................................. 219 Hnh 7.24 V d hot ng ca ch PWM (3) .................................................................. 220 Hnh 7.25 V d ca qu trnh thit lp ch m phase. ................................................... 221 Hnh 7.26 V d ca hot ng m phase 1 ......................................................................... 222 Hnh 7.27 V d ca hot ng m phase 2 ......................................................................... 223 Hnh 7.28 V d ca hot ng m phase 3 ......................................................................... 224 Hnh 7.29 V d ca hot ng m phase 4 ......................................................................... 225 Hnh 7.30 V d v vic ng dng ch m phase ........................................................... 226 Hnh 7.31 Tng quan v mt thi gian trong hot ng m vi xung clock trong ........... 231 Hnh 7.32 Tng quan v mt thi gian trong hot ng m vi xung clock ngoi. .......... 231 Hnh 7.33 Tng quan v thi gian trong hot ng xut output compare. ......................... 232 Hnh 7.34 Tng quan v mt thi gian ca cc tn hiu trong hot ng input capture. .... 232 Hnh 7.35 Phn tch thi gian hot ng xa b m (compare match) ............................... 232 Hnh 7.36 Phn tch thi gian hot ng xa b m (input capture) ................................... 232 Hnh 7.37 Phn tch thi gian hot ng buffer (compare match) ........................................ 233 Hnh 7.38 Phn tch thi gian hot ng buffer (input capture) ............................................ 233 Hnh 7.39 Phn tch thi gian hot ng ngt TGI (compare match) ................................... 234 Hnh 7.40 Phn tch thi gian hot ng ngt TGI (input capture) ..................................... 234 Hnh 7.41 Phn tch thi gain ca hot ng ngt TCIV .................................................... 234 Hnh 7.42 Phn tch thi gain ca hot ng ngt TCIU .................................................... 235 Hnh 7.43 Phn tch thi gian ca hot ng xa c trng thi bi CPU .............................. 235 Hnh 7.44 Phn tch thi gian cho hot ng xa c trng thi bi s kch hot DMAC (1)236 Hnh 7.45 Phn tch thi gian cho hot ng xa c trng thi bi s kch hot DMAC (2)236 Hnh 7.46 Phase khc (Phase Difference), phase trng (Overlap) v rng xung (Pulse Width) trong ch m phase ............................................................................................. 237 Hnh 7.47 Mu thun gia hot ng ghi TCNT v hot ng xa b m ......................... 237 Hnh 7.48 Mu thun gia hot ng ghi TCNT v hot ng tng b m ........................ 238 Hnh 7.49 Mu thun gia hot ng ghi TGR v hot ng compare match ...................... 238 Hnh 7.50 Mu thun gia hot ng ghi vo thanh ghi buffer v hot ng compare match ............................................................................................................................................... 239 Hnh 7.51 Mu thun gia hot ng c TGR v hot ng input capture ......................... 239 Hnh 7.52 Mu thun gia hot ng ghi vo TGR v hot ng input capture .................. 240 Hnh 7.53 Mu thun gia hot ng ghi vo thanh ghi buffer v hot ng input capture . 240 Hnh 7.54 Mu thun gia hot ng trn v hot ng xa b m ................................... 241 Hnh 7.55 Mu thun gia hot ng ghi vo TCNT v hot ng trn ............................... 241 Hnh 8.1 S khi ca b chuyn A/D ............................................................................... 244 Hnh 8.2 S khi ca b chuyn A/D ............................................................................... 245 Hnh 8.3 V d hot ng ca b chuyn A/D .................................................................... 253 Hnh 8.4 V d vic chuyn A/D ......................................................................................... 254 Hnh 8.5 A/D Thi gian chuyn i .................................................................................... 255
Hnh 8.6 nh thi ng nhp ngoi ..................................................................................... 256 Hnh 8.7 Cc nh ngha chnh xc vic chuyn A/D .................................................... 257 Hnh 8.8 Cc nh ngha chnh xc vic chuyn A/D .................................................... 258 Hnh 8.9 S ca chc nng pull-down port tng t ....................................................... 258 Hnh 8.10 V d mch nhp tun t..................................................................................... 259 Hnh 8.11 V d v mch bo v ng nhp tun t .............................................................. 260 Hnh 8.12 Mch tng ng ng nhp tun t ................................................................. 261 Hnh 9.1 S khi ca DMAC ........................................................................................... 264 Hnh 9.2 V d v gin xung tn hiu trong ch a ch i......................................... 283 Hnh 9.3 Hot ng trong ch a ch i......................................................................... 283 Hnh 9.4 Dng d liu trong ch a ch n ................................................................... 284 Hnh 9.5 V d v gin tn hiu trong ch a ch n................................................. 285 Hnh 9.6 Cc hot ng trong ch a ch n ................................................................. 285 Hnh 9.7 V d v gin thi gian trong ch truyn bnh thng .................................. 286 Hnh 9.8 Cc hot ng trong ch bnh thng................................................................ 286 Hnh 9.9 Hot ng trong ch truyn lp ......................................................................... 287 Hnh 9.10 Cc hot ng trong ch truyn khi ............................................................... 288 Hnh 9.11 Hot ng trong ch a ch n trong ch truyn khi ............................. 288 Hnh 9.12 Hot ng trong ch a ch i trong ch truyn khi .............................. 289 Hnh 9.13 V d gin thi gian ca ch Cycle stealing ............................................... 292 Hnh 9.14 V d ca gin thi gian trong ch burst..................................................... 292 Hnh 9.15 V d ca hot ng vng lp m rng ................................................................ 293 Hnh 9.16 V d v chc nng vng lp m rng trong ch truyn khi ......................... 294 Hnh 9.17 Phng thc cp nht a ch ............................................................................... 295 Hnh 9.18 Hot ng cng offset........................................................................................... 296 Hnh 9.19 i chiu XY s dng vic cng offset trong ch truyn lp ......................... 297 Hnh 9.20 Lc i chiu XY s dng cng offset trong ch truyn lp ................... 298 Hnh 9.21 Tin trnh thay i thit lp thanh ghi cho knh ang truyn. .............................. 301 Hnh 9.22 V d v s iu ho u tin ca knh............................................................. 303 Hnh 9.23 V d v gin thi gian bus ca b truyn DMA ............................................. 304 Hnh 9.24 V d v truyn d liu trong ch truyn bnh thng bi chu k stealing ..... 304 Hnh 9.25 V d ca truyn d liu trong ch bnh thng bi chu k stealing .............. 305 Hnh 9.26 V d ca truyn d liu trong ch bnh thng bi chu k stealing .............. 305 Hnh 9.27 V d truyn d liu trong ch truyn bnh thng bi cch truy xut burst .. 306 Hnh 9.28 v d v truyn d liu trong ch truyn khi .................................................. 306 Hnh 9.29 V d v truyn d liu trong ch truyn bnh thng c kch hot bi cnh xung ca DREQ ................................................................................................................. 307 Hnh 9.30 V d truyn d liu trong ch truyn bnh thng c kch hot bi mc thp ca tn hiu DREQ ................................................................................................................ 308 Hnh 9.31 v d ca truyn d liu trong ch truyn khi c kch hot bi mc thp ca tn hiu DREQ ..................................................................................................................... 309 Hnh 9.32 V d truyn d liu trong ch truyn d liu bnh thng c kch hot bi mc thp tn hiu DREQ vi NRD = 1 ................................................................................ 310 Hnh 9.33 V d v truyn d liu trong ch a ch n ................................................. 310 Hnh 9.34 V d v truyn d liu trong ch a ch n ................................................. 311 Hnh 9.35 V d v truyn d liu trong ch a ch n c kch hot bi cnh xung ca DREQ ............................................................................................................................ 312
Hnh 9.36 V d v truyn d liu trong ch a ch n c kch hot bi mc thp ca DREQ .................................................................................................................................. 313 Hnh 9.37 V d v truyn d liu trong ch a ch n c kch hot bi mc thp ca tn hiu DREQ vi NRD = 1 ................................................................................................ 314 Hnh 9.38 Ngt qung v cc ngun ngt qung ................................................................... 320 Hnh 9.39 V d tin trnh ca vic phc hi truyn bi vic xo ngun ngt qung ........... 320 Hnh 10.1 S khi ca DTC ............................................................................................. 323 Hnh 10.2 Thng tin truyn ti trong vng d liu ................................................................ 331 Hnh 10.3 S tng ng gia a ch bng vector DTC v thng tin truyn ti ................... 332 Hnh 10.4 Lu ca hot ng DTC .................................................................................. 336 Hnh 10.5 V d v chu k bus .............................................................................................. 339 Hnh 10.6 Gin thi gian hot ng b c thng tin truyn ........................................... 340 Hnh 10.7 Bn a ch trong ch truyn bnh thng. ................................................. 341 Hnh 10.8 B nh trong ch truyn lp ............................................................................ 342 Hnh 10.9 Bn b nh trong ch truyn khi .............................................................. 343 Hnh 10.10 Hot ng ca truyn chui ................................................................................ 344 Hnh 10.11 iu chnh hot ng ca DTC .......................................................................... 344 Hnh 10.12 iu chnh hot ng ca DTC .......................................................................... 345 Hnh 10.13 iu chnh hot ng ca DTC .......................................................................... 345 Hnh 10.14 iu chnh hot ng DTC ................................................................................. 345 Hnh 10.16 Truyn chui khi Counter = 0............................................................................. 351 Hnh 11.1 S khi ca PPG .............................................................................................. 354 Hnh 11.2 Gin khi ca PPG .......................................................................................... 363 Hnh 11.3 Gin thi gian ca truyn v xut ni dung ca NDR ..................................... 363 Hnh 11.4 Tin trnh thit lp cho xung xut ch bnh thng......................................... 364 Hnh 11.5 V d v xung xut bnh thng ........................................................................... 364 Hnh 11.6 Xut xung trong ch non-overlapping ............................................................. 365 Hnh 11.7 Hot ng non-overlapping v gin ghi NDR ................................................. 366 Hnh 11.8 Qu trnh thit lp xung xut non-overlapping ..................................................... 366 Hnh 11.9 V d xung xut non-overlapping ......................................................................... 367 Hnh 11.10 o xung xut ..................................................................................................... 368 Hnh 11.11 Xung xut c trigger bi tn hiu input capture ............................................. 369 Hnh 12.1 S khi ca SCI ............................................................................................... 371 Hnh 12.2 nh dng d liu trong giao tip bt ng b ................................................... 392 Hnh 12.3 nh thi mu d liu nhn trong ch bt ng b ....................................... 394 Hnh 12.4 Mi quan h v pha gia Clock xut v D liu truyn ....................................... 395 Hnh 12.5 Lu khi to SCI mu ..................................................................................... 395 Hnh 12.6 V d v hot ng truyn trong Ch bt ng b........................................... 397 Hnh 12.7 Lu truyn tun t mu ................................................................................... 397 Hnh 12.8 V d v hot ng nhn trong Ch bt ng b ............................................. 399 Hnh 12.9 Lu mu nhn tun t ...................................................................................... 400 Hnh 12.10 V d v Giao tip s dng nh dng a x l ................................................. 401 Hnh 12.11 Lu mu truyn d liu tun t a x l ..................................................... 402 Hnh 12.12 V d hot ng nhn ca SCI .......................................................................... 403 Hnh 12.13 Lu d mu qu trnh nhn tun t a x l .................................................... 404 Hnh 12.14 nh dng d liu trong giao tip ng b clock ............................................. 405 Hnh 12.15 Lu mu qu trnh khi to SCI .................................................................. 406 Hnh 12.16 V d hot ng truyn trong Ch ng b clock........................................ 407
Hnh 12.17 Lu mu qu trnh truyn d liu tun t ...................................................... 408 Hnh 12.18 V d v hot ng nhn trong Ch ng b clock ..................................... 409 Hnh 12.19 Lu mu qu trnh nhn tun t .................................................................... 409 Hnh 12.20 Lu mu cho vic truyn nhn ng thi ...................................................... 411 Hnh 12.21 Kt ni chn cho giao din smart card ............................................................... 412 Hnh 12.22 nh dng d liu trong Ch giao din smart card ...................................... 412 Hnh 12.23 Quy c thun (SDIR = SINV = O/E = 0) ....................................................... 413 Hnh 12.24 Quy c nghch (SDIR = SINV = O/E = 1) ....................................................... 413 Hnh 12.25 nh thi ly mu d liu nhn trong Ch giao din smart card ................. 414 Hnh 12.26 Hot ng truyn li d liu trong ch truyn SCI ...................................... 416 Hnh 12.27 nh thi lp c TEND trong qu trnh truyn ................................................ 416 Hnh 12.28 Lu mu qu trnh truyn ............................................................................ 417 Hnh 12.29 Hot ng truyn li d liu trong ch nhn SCI ........................................ 418 Hnh 12.30 Lu mu qu trnh nhn............................................................................... 419 Hnh 12.31 nh thi c nh xut clock ............................................................................ 419 Hnh 12.32 Dng clock v th tc restart .............................................................................. 420 Hnh 12.33 Qu trnh truyn mu s dng DTC/DMAC trong Ch ng b clock ........ 423 Hnh 12.34 Lu mu vic chuyn ch trong qu trnh truyn ................................... 424 Hnh 12.35 Trng thi chn port trong qu trnh chuyn ...................................................... 425 Hnh 12.36 Trng thi chn port trong qu trnh chuyn ...................................................... 425 Hnh 12.37 Lu mu vic chuyn ch trong qu trnh nhn ..................................... 426 Hnh 13.1 S khi ca SSU ....................................................................................... 428 Hnh 13.2 Mi quan h ca cc, pha clock v d liu truyn ............................................. 441 Hnh 13.3 Mi quan h gia cc chn nhp/xut d liu v thanh ghi dch ....................... 442 Hnh 13.4 V d v thit lp ban u trong ch SSU...................................................... 444 Hnh 13.5 V d ca hot ng truyn................................................................................. 446 Hnh 13.6 Lu v d ca qu trnh truyn d liu .......................................................... 447 Hnh 13.7 V d ca hot ng nhn d liu ....................................................................... 448 Hnh 13.8 Lu v d ca qu trnh nhn d liu ............................................................. 449 Hnh 13.9 Lu v d ca qu trnh truyn nhn d liu ng thi ................................. 450 Hnh 13.10 Thi gian xc nh Arbitration ......................................................................... 451 Hnh 13.10 Thi gian xc nh Arbitration ......................................................................... 451 Hnh 13.12 V d ca qu trnh thit lp ban u ................................................................ 452 Hnh 13.13 V d ca hot ng truyn............................................................................... 453 Hnh 13.14 Lu v d ca qu trnh truyn d liu ........................................................ 453 Hnh 13.15 V d ca hot ng nhn d liu ..................................................................... 454 Hnh 13.16 Lu v d ca qu trnh nhn d liu ........................................................... 455 Hnh 13.17 Lu v d ca qu trnh truyn nhn d liu ng thi ............................... 456 Hnh 14.1 S khi b iu khin bus ............................................................................... 459 Hnh 14.2 Cu hnh bus ni ................................................................................................... 461 Hnh 14.3 V d vic nh thi khi chc nng buffer ghi d liu c bt........................... 463 Hnh 16.1 S khi ca b nh flash ................................................................................. 468 Hnh 16.2 S chuyn ch ca b nh flash ...................................................................... 469 Hnh 16.3 Cu hnh b nh MAT .......................................................................................... 471 Hnh 16.4 Cu trc khi ca User MAT ............................................................................... 472 Hnh 16.5 Tin trnh to ra mt chng trnh lp trnh. ................................................... 473 Hnh 16.6 Cu hnh h thng trong ch boot. ................................................................... 493 Hnh 16.7 Hot ng iu chnh tc bit t ng .............................................................. 494 Hnh 16.8 S khi hot ng chuyn trng thi ch boot ........................................... 495
Hnh 16.9 Quy trnh lp trnh/xa ......................................................................................... 496 Hnh 16.10 Bn RAM khi hot ng lp trnh/xa ang c thc thi. .......................... 497 Hnh 16.11 Quy trnh lp trnh trong ch user program. .................................................. 497 Hnh 16.12 Tin trnh xa trong ch User Program ......................................................... 502 Hnh 16.13 Tin trnh lp ca hot ng xa, lp trnh, v m phng RAM trong ch User Program ................................................................................................................................. 504 Hnh 16.14 Tin trnh cho vic lp trnh user MAT trong ch user boot ......................... 505 Hnh 16.15 Tin trnh xa vng user MAT trong ch user Boot. ................................ 506 Hnh 16.16 S chuyn i n trng thi bo v li ............................................................. 515 Hnh 16.17 Tin trnh m phng RAM ................................................................................. 516 Hnh 16.18 Bn a ch ca vng RAM b ph ................................................................ 516 Hnh 16.19 Lp trnh turned data........................................................................................... 517 Hnh 16.20 Chuyn i gia user MAT v user boot MAT.................................................. 518 Hnh 16.21 Cc trng thi chng trnh boot ........................................................................ 520 Hnh 16.22 Chui iu chnh tc bit................................................................................. 520 Hnh 16.23 nh dng giao thc giao tip. ............................................................................ 521 Hnh 16.24 Chui la chn tc bit mi ............................................................................ 531 Hnh 16.25 Chui lp trnh .................................................................................................... 534 Hnh 16.26 Chui xa............................................................................................................ 534 Hnh 17.1 S khi ca WDT ............................................................................................ 544 Hnh 17.2 Hot ng trong ch nh thi watchdog ........................................................ 548 Hnh 17.3 Hot ng trong ch nh thi ngt khong .................................................... 549 Hnh 17.4 Ghi vo TCNT, TCSR v RSTCSR ..................................................................... 550 Hnh 17.5 Xung t gia vic tng v ghi b m TCNT ................................................ 550
MC LC BNG
Bng 1.1 Cu hnh chn trong mi ch ................................................................................ 3 Bng 1.2 Cc chc nng ca chn ............................................................................................. 8 Bng 2.1 Phn loi cu lnh .................................................................................................... 33 Bng 2.2 S kt hp ca cc cu lnh v cc ch nh a ch (1) .................................... 35 Bng 2.2 S kt hp cc cu lnh v cc ch nh a ch (2) ........................................... 40 Bng 2.3 K hiu cc php ton .............................................................................................. 41 Bng 2.4 Cc lnh chuyn d liu..................................................................................... 42 Bng 2.5 Cc lnh chuyn khi d liu ........................................................................... 43 Bng 2.6 Cc lnh v php ton s hc ............................................................................. 43 Bng 2.7 Cc cu lnh php ton lun l .......................................................................... 46 Bng 2.8 Cc cu lnh ca php ton dch ....................................................................... 46 Bng 2.9 Cc cu lnh thao tc bit.................................................................................... 47 Bng 2.10 Cc cu lnh r nhnh ...................................................................................... 49 Bng 2.11 Cc lnh iu khin h thng ........................................................................... 50 Bng 2.13 Vng truy xut ca a ch tuyt i ...................................................................... 55 Bng 2.14 Tnh ton a ch hiu dng cho cc cu lnh chuyn d liu v cc php tnh .... 58 Bng 2.15 Tnh ton a ch hiu dng cho cc cu lnh r nhnh ......................................... 58 Bng 3.1 Thit lp ch hot ng MCU ............................................................................. 61 Bng 3.2 Thit lp cc bit t MSD3 n MSD0 ..................................................................... 63 Bng 4.1 Cc loi ngoi l v u tin ................................................................................. 67 Bng 4.2 Bng vector x l ngoi l ....................................................................................... 68 Bng 4.3 Phng php tnh ca a ch bng vector x l ngoi l ........................................ 69 Bng 4.4 Trng thi ca CCR v EXR sau khi x l ngoi l theo di .................................. 71 Bng 4.5 Chu k bus v sai a ch.......................................................................................... 71 Bng 4.6 Trng thi ca CCR v EXR sau khi x l li sai a ch ........................................ 73 Bng 4.7 Cc ngun ngt qung .............................................................................................. 74 Bng 4.8 Trng thi ca CCR v EXR sau khi thc thi chng trnh x l lnh by............. 75 Bng 4.9 Trng thi ca CCR v EXR sau khi x l lnh khng hp l ................................ 75 Bng 5.1 Cu hnh chn ........................................................................................................... 79 Bng 5.2 Ngun ngt qung, a ch offset cc vector v u tin ngt qung ................... 91 Bng 5.3 Cc ch iu khin ngt qung............................................................................ 96 Bng 5.4 Thi gian p ng ngt qung................................................................................ 101 Bng 5.5 S lng trng thi thc thi trong chng trnh con phc v ngt qung ............. 101 Bng 5.6 iu khin chn/xa ngun ngt qung ................................................................. 104 Bng 5.7 iu khin u tin CPU .................................................................................... 105 Bng 5.8 V d ca vic thit lp chc nng iu khin u tin v trng thi iu khin 106 Bng 6.1 Cc chc nng ca cc cng .................................................................................. 109 Bng 6.2 Cc thanh ghi ca mi port .................................................................................... 116 Bng 6.3 Trng thi pull-up MOS nhp ................................................................................ 119 Bng 7.1 Cu hnh b m cho mi sn phm ...................................................................... 154 Bng 7.2 Cc chc nng ca TPU (b nh thi 1) ............................................................... 157 Bng 7.3 Cu hnh cc chn .................................................................................................. 162 Bng 7.5 CCLR2 n CCLR0 (i vi knh 0 v 3)............................................................. 171 Bng 7.6 CCLR2 n CCLR0 (i vi knh 1, 2, 4 v 5)..................................................... 172 Bng 7.7 La chn cnh xung ng h nhp ........................................................................ 172 Bng 7.8 TPSC2 n TPSC0 (knh 0) .................................................................................. 173 Bng 7.9 TPSC2 n TPSC0 (knh 1) .................................................................................. 173
Bng 7.10 TPSC2 n TPSC0 (knh 2) ................................................................................ 174 Bng 7.11 TPSC2 n TPSC0 (knh 3) ................................................................................ 174 Bng 7.12 TPSC2 n TPSC0 (knh 4) ................................................................................ 175 Bng 7.13 TPSC2 n TPSC0 (knh 5) ................................................................................ 175 Bng 7.14 MD3 n MD0 ..................................................................................................... 177 Bng 7.15 TIORH_0.............................................................................................................. 179 Bng 7.16 TIORL_0 .............................................................................................................. 180 Bng 7.17 TIOR_1 ................................................................................................................ 181 Bng 7.18 TIOR_2 ................................................................................................................ 182 Bng 7.19 TIORH_3.............................................................................................................. 183 Bng 7.20 TIORL_3 .............................................................................................................. 184 Bng 7.21 TIOR_4 ................................................................................................................ 186 Bng 7.22 TIOR_5 ................................................................................................................ 187 Bng 7.23 TIORH_0.............................................................................................................. 188 Bng 7.24 TIORL_0 .............................................................................................................. 189 Bng 7.25 TIOR_1 ................................................................................................................ 190 Bng 7.26 TIOR_2 ................................................................................................................ 191 Bng 7.27 TIORH_3.............................................................................................................. 192 Bng 7.28 TIORL_3 .............................................................................................................. 193 Bng 7.29 TIOR_4 ................................................................................................................ 194 Bng 7.30 TIOR_5 ................................................................................................................ 195 Bng 7.31 Cc nhm thanh ghi c s dng trong hot ng buffer ................................. 211 Bng 7.32 Cc cp xp tng .................................................................................................. 214 Bng 7.33 Cc thanh ghi xut PWM v cc chn xut.......................................................... 217 Bng 7.35 Cc iu kin m ln/xung ca TCNT trong ch m phase 1. .................. 222 Bng 7.36 Cc iu kin m ln/xung ca TCNT trong ch m phase 2. .................. 223 Bng 7.37 Cc iu kin m ln/xung ca TCNT trong ch m phase 3. .................. 224 Bng 7.38 Cc iu kin m ln/xung ca TCNT trong ch m phase 4. .................. 225 Bng 7.39 Ngt TPU ............................................................................................................. 226 Bng 8.1 Cu hnh chn ......................................................................................................... 245 Bng 8.2 Knh nhp tun t v thanh ghi ADDR tng ng ............................................ 247 Bng 8.3 Cc c im chuyn i A/D (Ch n) ...................................................... 255 Bng 8.5 Ngun ngt qung b chuyn A/D ...................................................................... 256 Bng 8.6 Cc c im chn tun t .................................................................................. 260 Bng 9.1 Kch thc d liu, cc bit hp l v kch thc c th c thit lp.................. 268 Bng 9.2 Thit lp v cc vng ca vng lp m rng ......................................................... 280 Bng 9.3 Cc ch chuyn d liu ..................................................................................... 281 Bng 9.4 Danh sch cc ngt qung ca module trn chip cho DMAC ................................ 290 Bng 9.5 u tin ca cc knh DMAC ............................................................................ 302 Bng 9.6 Cc ngun ngt v u tin. ................................................................................ 317 Bng 10.1 Ngun ngt, a ch vector DTC, v cc DTCE tng ng ................................. 332 Bng 10.2 Cc ch truyn ca DTC ................................................................................. 335 Bng 10.3 Cc iu kin ca truyn ti chui ....................................................................... 336 Bng 10.4 S chia nh s chu k bus v kch thc truy xut .............................................. 338 Bng 10.5 iu kin b qua vic ghi li thng tin truyn v cc thanh ghi b b qua vic ghi li thng tin truyn. ................................................................................................................ 340 Bng 10.6 Danh sch chc nng thanh ghi trong ch truyn bnh thng. ...................... 340 Bng 10.7 Lit k chc nng thanh ghi trong ch truyn lp. .......................................... 341 Bng 10.8 Lit k chc nng thanh ghi trong ch truyn khi. ........................................ 342
Bng 10.9 Cc trng thi thc thi ca DTC .......................................................................... 345 Bng 10.10 S chu k cn thit cho mi trng thi thc thi. ................................................. 346 Bng 11.1 Cu hnh chn ....................................................................................................... 354 Bng 12.1 Cu hnh chn ....................................................................................................... 371 Bng 12.2 Mi quan h gia thit lp N v tc bit B ....................................................... 386 Bng 12.3 V d v vic thit lp BRR cho cc tc bit khc nhau ................................... 387 Bng 12.3 V d v vic thit lp BRR cho cc tc bit khc nhau ................................... 388 Bng 12.4 Tc bit ti a cho tng tn s hot ng ......................................................... 389 Bng 12.5 Tc bit ti a vi ng nhp clock ngoi .......................................................... 389 Bng 12.6 Thit lp BRR cho cc tc bit khc nhau ........................................................ 389 Bng 12.7 Tc bit ti a vi ng nhp clock ngoi .......................................................... 391 Bng 12.8 Thit lp BRR cho cc tc bit khc nhau ........................................................ 391 Bng 12.9 Tc bit ti a vi ng nhp clock ngoi .......................................................... 391 Bng 12.10 Cc nh dng truyn tun t ............................................................................. 392 Bng 12.11 Cc c trng thi SSR v Qu trnh x l d liu nhn ..................................... 399 Bng 12.12 Ngun ngt qung SCI ....................................................................................... 421 Bng 12.13 Ngun ngt qung SCI ....................................................................................... 421 Bng 13.1 cho thy cu hnh chn ca SSU .......................................................................... 428 Bng 13.2 Cc ch giao tip v Trng thi chn ca cc chn SSI v SSO ..................... 442 Bng 13.3 Cc ch giao tip v Trng thi chn ca chn SSCK .................................... 443 Bng 13.4 Cc ch giao tip v Trng thi chn ca chn SCS ....................................... 443 Bng 13.5 Ngun ngt qung ................................................................................................ 456 Bng 14.1 Clock ng b v cc chc nng tng ng ........................................................ 461 Bng 14.2 S lng chu k cn truy cp tng khng gian b nh ni ............................. 462 Bng 14.3 S lng chu k cn truy cp thanh ghi ca cc thit b ngoi vi ................... 462 Bng 16.1 S khc bit gia cc ch boot, ch user program, user boot, v ch programmer. .......................................................................................................................... 469 Bng 16.2 Cu hnh chn ....................................................................................................... 474 Bng 16.3 Cc thanh ghi/cc tham s v cc ch ch ..................................................... 475 Bng 16.4 Cc tham s v cc ch ch ........................................................................... 482 Bng 16.5 Vic thit lp ch lp trnh on-board ............................................................... 493 Bng 16.6 Tn s clock h thng cho hot ng iu chnh tc bit t ng .................... 494 Bng 16.7 B nh MAT c th thc thi c ....................................................................... 508 Bng 16.8 Vng c th s dng cho vic lp trnh trong ch User Program ................... 508 Bng 16.9 Vng c th s dng cho vic xa trong ch User Program ........................... 509 Bng 16.10 vng c th s dng cho vic lp trnh trong ch User Boot ........................ 510 Bng 16.11 Cc vng c th s dng xa trong ch User Boot .................................. 511 Bng 16.12 Bo v phn cng ............................................................................................... 513 Bng 16.13 Bo v phn mm ............................................................................................... 513 Bng 16.14 Cc loi thit b c h tr trong ch programmer. .................................... 518 Bng 16.15 Cc cu lnh yu cu v la chn ...................................................................... 522 Bng 16.16 Cc cu lnh lp trnh/xa .................................................................................. 532 Bng 16.17 M trng thi ...................................................................................................... 541 Bng 16.18 M li ................................................................................................................. 541 Bng 17.1 Ngun ngt qung WDT ...................................................................................... 549
Chng 1 Tng quan

1.1 Cc tnh cht
CPU H8SX 32-bit hiu nng cao l s pht trin tng thch ca CPU H8/300, CPU H8/300H, v CPU H8S 16 thanh ghi a dng 16 bit 87 cu lnh cn bn Cc chc nng ngoi vi m rng DMA B iu khin chuyn d liu (DMAC) B iu khin n v xung b m 16 bit (DTC) B lp trnh to xung (TPU) (PPG)B m gim st (WDT) Giao tip tun t (SCI) c th c s dng trong ch ng b xung clock v bt ng b n v giao tip tun t ng b Trnh chuyn i A/D 10-bit B to xung clock On-chip memory: Phn loi sn phm Flash memory version H8SX/1582 Port I/O: o 65 port xut /nhp o 17 port nhp H tr cc ch ngt in (power-down modes) Kch thc nh: Gi LQFP1414-120 M FP-120B Kch thc thn 14.0 14.0 mm rng chn 0.40 mm Dng sn phm R5F61582 ROM 256 kbytes RAM 12 kbytes
1.2 S khi
Hnh 1.1 S khi ca H8SX/1582
1.3 Chn ca H8SX/1582

1.3.1 chn
Hnh 1.2 Cc Chn ca H8SX/1582 1.3.2 Cu hnh chn trong mi ch hot ng Bng 1.1 Cu hnh chn trong mi ch
STT chn 1 2 3 4 5 6 7 Tn vit tt trong Mode 1, Mode 2, v Mode 3 PD5/SSI1 PD6/SSCK1 PD7/SCS1 Vcc P60/TxD4/IRQ8-B Vss P61 /RxD4/I RQ9-B
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
P62/SCK4/IRQ10-B P63/IRQ11-B/TDO* P64/IRQ12-B P65/IRQ13-B PI3 P66/IRQ14-B PJ0/TIOCA6 PJ1/TIOCA6/TIOCB6 PJ2/TIOCC6/TCLKE PJ3/TIOCC6/TIOCD6/TCLKF P67/IRQ15-B PJ4/TIOCA7 PJ5/TIOCA7/TIOCB7/TCLKG PJ6/TIOCA8 PJ7/TIOCA8/TIOCB8/TCLKH PI4 Vss PK0/TIOCA9 Vcc PK1/TIOCA9/TIOCB9 PI5 PK2/TIOCC9 PK3/TIOCC9/TIOCD9 PK4/TIOCA10 PK5/TIOCA10/TIOCB10 PI6
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
PK6/TIOCA11 PK7/TIOCA11/TIOCB11 PH0 PI7 PH1 PH2 PH3 PH4 PH5 PB0 PH6 PH7 Vcc P10/IRQ0 Vss P11/IRQ1 VCL PB1 P12/IRQ2 P13/ADTRG0/IRQ3 P14/TxD3/IRQ4 P15/RxD3/IRQ5 P16/SCK3/IRQ6 P17/ADTRG1/IRQ7 P20/TIOCA3/TIOCB3/I RQ8-A P21/TIOCA3/I RQ9-A/SCS2
60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
P22/TIOCC3/IRQ10-A P23/TIOCC3/TIOCD3/I RQ11-A Vss PA7/B Vcc PB2 PA6 PA5 PA4 P30/PO8/TIOCA0 P31/PO9/TIOCA0/TIOCB0 P32/PO10/TIOCC0/TCLKA P33/PO11/TIOCC0/TIOCD0/TCLKB P24/TIOCA4/TIOCB4/I RQ12-A P34/PO12/TIOCA1/TRST* P35/PO13/TIOCA1/TIOCB1/TCLKC/TMS* P36/PO14/TIOCA2/TDI* P37/PO15/TIOCA2/TIOCB2/TCLKD/TCK* P25/TIOCA4/I RQ13-A RES NMI P26/TIOCA5/I RQ14-A Vcc XTAL EXTAL Vss
86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111
EMLE* PA3/SSO2 P27/TIOCA5/TIOCB5/I RQ15-A PA2/SSI2 PA1/SSCK2 PA0 MD1 P40/AN12 P41/AN13 P42/AN14 P43/AN15 P44/AN8 P45/AN9 P46/AN10 AVcc1 P47/AN11 AVss P50/AN0 AVcc0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7
112 113 114 115 116 117 118 119 120
MD0 PI0 PD0/SSO0 PI1 PD1/SSI0 PD2/SSCK0 PI2 PD3/SCS0 PD4/SSO1
Ch : * chn EMLE cho php/cm cc chc nng g ri trn chip. Khi Chn EMLE mc cao, th cc chn TDO, TDI, TCK, TMS v TRST l c s dng cho E10A. Trong trng hp ny, cc chc nng khc l b cm. 1.3.3 Cc chc nng ca chn Bng 1.2 Cc chc nng ca chn
Phn loi K hiu S th t chn H8SX/1582 Ngun VCC VCL VSS Clock XTAL EXTAL 4, 26, 46, 6, 82 50 6, 24, 48, 62, 85 83 84 Nhp Nhp Nhp Nhp Nhp Cc chn ngun. Ni vi ngun ca h thng. Ni vi Vss thng qua mt t 0.1 uF (gn gn vi chn ny) Chn t. Ni vi t (0V) Cc chn clock. Xung clock ngoi c th ni vo chn EXTAL. Chi tit tham kho phn 18 Clock Pulse Generator (b to xung clock) Cung cp xung ng h h thng cho cc thit b bn ngoi I/O c t
63
Xut
iu khin ch hot ng iu khin h thng
MD1 MD0
92 112
Nhp Nhp
Cc chn thit lp ch hot ng. Cc mc tn hiu ca cc chn ny phi khng c thay i trong sut qu trnh hot ng. Chn nhp tn hiu khi ng li. Vi iu khin ny vo trng thi khi ng li khi tn hiu ny mc thp. Chn nhp tn hiu cho php gi lp ni.Bnh thng tn hiu ny nn mc thp. Tn hiu yu cu ngt NMI. Khi chn ny khng c s dng, n phi c nh mc cao. Tn hiu yu cu ngt
RES
79
Nhp
EMLE
86
Nhp
Ngt qung
NMI
80
Nhp
IRQ15 A / IRQ15 B
IRQ14 A / IRQ14 B IRQ13 A / IRQ13 B IRQ12 A / IRQ12 B IRQ11 A / IRQ11 B IRQ10 A / IRQ10 B IRQ9 A / IRQ9 B IRQ8 A / IRQ8 B IRQ 7 IRQ 6 IRQ5 IRQ 4 IRQ3
88/18 81/13 78/11 73/10 61/9 60/8 59/7 58/5 57 56 55 54 53
Nhp
IRQ 2 IRQ1 IRQ 0
52 49 47 74 75 9 76 77 71 72 75 77 69, 70 70 72, 71 72 74, 75 75 I/O I/O Cc tn hiu t TGRA_0 n TGRD_0 c s dng cho vic lm tn hiu input capture v xut tn hiu output compare hay xut tn hiu PWM Cc tn hiu t TGRA_1 n TGRB_1 c s dng cho vic lm tn hiu input capture v xut tn hiu output compare hay xut tn hiu PWM Cc tn hiu t TGRA_2 n TGRB_2 c s dng cho vic lm tn hiu input capture v xut tn hiu output compare hay xut tn hiu PWM Cc tn hiu t TGRA_3 n TGRD_3 c s dng cho vic lm tn hiu input capture Input Nhp Xut Nhp Nhp Nhp Cc chn nhp cho xung clock ngoi Cc chn s dng cho vic g ri gi lp trn chip.
Giao din g ri
TRST
TMS TDO TDI TCK
n v TCLKA xung TCLKB b m 16-bit TCLKC (TPU) (unit 0) TCLKD TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1
TIOCA2 TIOCB2
76, 77 77
I/O
TIOCA3 TIOCB3
58, 59 58
I/O
10
TIOCC3 TIOCD3 TIOCA4 TIOCB4
60, 61 61 73, 78 73 I/O
v xut tn hiu output compare hay xut tn hiu PWM Cc tn hiu t TGRA_4 n TGRB_4 c s dng cho vic lm tn hiu input capture v xut tn hiu output compare hay xut tn hiu PWM Cc tn hiu t TGRA_5 n TGRB_5 c s dng cho vic lm tn hiu input capture v xut tn hiu output compare hay xut tn hiu PWM Cc chn nhp cho xung clock ngoi
TIOCA5 TIOCB5
81, 88 88
I/O
n v TCLKE xung TCLKF b m 16-bit TCLKG (TPU) (unit 1) TCLKH TIOCA6 TIOCB6 TIOCC6 TIOCD6 TIOCA7 TIOCB7
16 17 20 22 14, 15 15 16, 17 17 19, 20 20
Nhp
I/O
Cc tn hiu t TGRA_6 n TGRD_6 c s dng cho vic lm tn hiu input capture v xut tn hiu output compare hay xut tn hiu PWM Cc tn hiu t TGRA_7 n TGRB_7 c s dng cho vic lm tn hiu input capture v xut tn hiu output compare hay xut tn hiu PWM Cc tn hiu t TGRA_8 n TGRB_8 c s dng cho vic lm tn hiu input capture v xut tn hiu output compare hay xut tn hiu PWM Cc tn hiu t TGRA_9 n
I/O
TIOCA8 TIOCB8
21, 22 22
I/O
TIOCA9
25, 27
I/O
11
TIOCB9 TIOCC9 TIOCD9 TIOCA10 TIOCB10
27 29, 30 30 31, 32 32 I/O
TGRD_9 c s dng cho vic lm tn hiu input capture v xut tn hiu output compare hay xut tn hiu PWM Cc tn hiu t TGRA_10 n TGRB_10 c s dng cho vic lm tn hiu input capture v xut tn hiu output compare hay xut tn hiu PWM Cc tn hiu t TGRA_11 n TGRB_11 c s dng cho vic lm tn hiu input capture v xut tn hiu output compare hay xut tn hiu PWM Cc chn xut tn hiu xung
TIOCA11 TIOCB11
34, 35 35
I/O
B lp trnh to xung (PPG)
PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8
77 76 75 74 72 71 70 69 54 5 55 7 56 8 87
Xut
Giao TxD3 tip tun t TxD4 (SCI) RxD3 RxD4 SCK3 SCK4 n v
Xut
Chn xut cho vic trao i d liu Cc chn nhp nhn d liu
Nhp
I/O
Cc chn xut nhp cho cc tn hiu xung clock Cc chn xut nhp d liu
SSO2
I/O
12
giao SSO1 tip tun t SSO0 ng b (SSU) SSI2 SSI1 SSI0 SSCK2 SSCK1 SSCK0
120 114 89 1 116 90 2 117 59 3 119 96 95 94 93 101 99 98 97 111 110 109 108 107 106 Nhp Cc chn nhp tn hiu tng t cho trnh chuyn i A/D I/O Cc chn xut nhp d liu I/O Cc chn xut nhp d liu I/O Cc chn xut nhp d liu
SCS2
SCS1 SCS0
Trnh chuy n i A/D AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2
13
AN1 AN0
105 103 53 57 104 100 Nhp Nhp Cc chn nhp cc tn hiu trigger khi ng trnh chuyn i A/D Cung cp ngun ca tn hiu tng t v cc chn tham kho ngun (reference power supply) cho trnh chuyn i A/D Khi m trnh chuyn i A/D khng s dng th n c ni vi ngun.
ADTRG0
ADTRG1
AVCC0 AVCC1
AVSS
102
Nhp
Chn t cho trnh chuyn i A/D v D/A. c ni vi t ca h thng Cc chn xut nhp d liu 8 bit
Port xut nhp
P17 P16 P15 P14 P13 P12 P11 P10 P27 P26 P25 P24 P23 P22
57 56 55 54 53 52 49 47 88 81 78 73 61 60
I/O
I/O
Cc chn xut nhp d liu
14
P21 P20 P37 P36 P35 P34 P33 P32 P31 P30 P47 P46 P45 P44 P43 P42 P41 P40 P57 P56 P55 P54 P53 P52 P51 P50
59 58 77 76 75 74 72 71 70 69 101 99 98 97 96 95 94 93 111 110 109 108 107 106 105 103 Nhp Cc chn xut nhp d liu 8 bit Nhp Cc chn xut nhp d liu 8 bit I/O Cc chn xut nhp d liu 8 bit
15
Port xut nhp
P67 P66 P65 P64 P63 P62 P61 P60 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB2 PB1 PB0 PD7 PD6 PD5 PD4 PD3 PD2 PD1
18 13 11 10 9 8 7 5 63 66 67 68 87 89 90 91 65 51 43 3 2 1 120 119 117 116
I/O
Cc chn xut nhp d liu
Nhp I/O
Chn nhp 1 bit Cc chn xut nhp d liu 6 bit
I/O
Cc chn xut nhp d liu 3 bit
I/O
Cc chn xut nhp d liu 8 bit
16
PD0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 I/O port Port xut nhp PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PK7
114 45 44 42 41 40 39 38 36 37 33 28 23 12 118 115 113 22 21 20 19 17 16 15 14 35 I/O Cc chn xut nhp d liu 8 I/O Cc chn xut nhp d liu 8 bit I/O Cc chn xut nhp d liu 8 bit I/O Cc chn xut nhp d liu 8 bit
17
PK6 PK5 PK4 PK3 PK2 PK1 PK0
34 32 31 30 29 27 25
bit
18
Chng 2 CPU
H8SX l mt CPU tc cao vi kin trc bn trong 32-bit. N l s pht trin tng thch ca cc CPU ca dng H8/300, H8/300H v H8S CPU H8SX c 16 thanh ghi a dng 16 bit, c th qun l n 4-Gbyte khng gian b nh tuyn tnh v l mt h thng iu khin thi gian thc.
2.1 Cc tnh nng

S pht trin tng thch ca CPU H8/300, H8/300H v H8S o C th thc thi cc chng trnh i tng ca H8/300, H8/300H v H8S/2000 16 thanh ghi a dng 16 bit o Cng thch hp cho vic s dng nh l 16 thanh ghi a dng 8-bit hay 8 thanh ghi a dng 32-bit 87 cu lnh cn bn o Cc cu lnh lun l v s hc 8-bit, 16-bit hay 32-bit o Cc cu lnh nhn v chia o Cc cu lnh truyn d liu o Cc cu lnh mnh x l bit o Cc cu lnh r nhnh bit o Cu lnh nhn v tch ly 11 ch nh a ch o Trc tip thanh ghi [Rn] o Gin tip thanh ghi [@ERn] o Gin tip thanh ghi vi dch chuyn [@(d:2,ERn),@(d:16,ERn), hay @(d:32,ERn)] o Gin tip thanh ghi ch s vi dch chuyn [@(d:16, RnL.B),@(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), hay @(d:32,ERn.L)] o Gin tip thanh ghi tng sau/trc hay gim sau/trc [@+ERn, @ERn+, @-ERn, hay @ERn-,] o a ch tuyt i [@aa:8, @aa:16, @aa:24, hay @aa:32] o Trc tip [#xx:3, #xx:4, #xx:8, #xx:16, hay #xx:32] o PC tng i [@(d:8,PC) hay @(d:16,PC)] o PC tng i vi thanh ghi ch s [@(RnL.B,PC), @(Rn.W,PC), hay @
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(ERn.L,PC)] o B nh gin tip [@ @ aa:8] o M rng b nh gin tip [@ @vec:7] Hai thanh ghi nn (cn bn) o Thanh ghi nn vector o Thanh ghi nn a ch ngn Khng gian a ch 4Gbyte o Chng trnh: 4Gbyte o D liu: 4Gbyte Thao tc nhanh o Tt c cc cu lnh thng xuyn s dng u c thc thi ch trong 1 hay 2 trng thi o Cc php cng tr gia thanh ghi vi thanh ghi 8-bit, 16-bit hay 32-bit u c thc thi ch trong 1 trng thi o Php nhn gia hai thanh ghi 8-bit: 1 trng thi o Php chia gia hai thanh ghi 16 8-bit: 10 trng thi o Php nhn hai thanh ghi 16 bit: 1 trng thi o Php chia hai thanh ghi 32 16-bit: 18 trng thi o Php nhn 2 thanh ghi 32 bit: 5 trng thi o Php chia 2 thanh ghi 32 bit: 18 trng thi CPU c 4 ch hot ng o Ch hot ng bnh thng (Normal mode) o Ch hot ng trung gian (Middle mode) o Ch hot ng nng cao (Advanced mode) o Cc ch hot ng ti a (Maximum modes) Cc ch ngt in (Power-down modes) o S chuyn tip c thc hin khi thc thi mt cu lnh SLEEP o S la chn cc ch ng hot ng ca xung clock Ch : 1. Ch ch hot ng nng cao (advanced mode) l c s dng trong CPU ca vi x l H8SX/1582. Cn li cc ch bnh thng, trung gian v ti a khng c h tr. 2. Cc b nhn v b chia c h tr bi H8SX/1582. 3. Trong H8SX/1582, mt cu lnh c c lnh ch 32-bit
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2.2 Cc ch hot ng ca CPU

CPU H8SX c 4 ch hot ng: ch bnh thng (Normal), trung bnh (Middle), nng cao (Advanced) v ti a (Maximum). Vic thit lp chi tit trn cc ch , tham kho 3.1, La chn cc ch hot ng (Operating Mode Selection).
Hnh 2.1 Cc ch hot ng ca CPU 2.2.1 Ch bnh thng Bng vector ngoi l v stack ca CPU H8SX c cng cu trc vi CPU H8/300. Ch : Ch bnh thng khng c h tr trong vi iu khin ny (H8SX/1582) Khng gian a ch: khng gian a ch ln nht 64Kbyte c th truy xut. Cc thanh ghi m rng (En): Cc thanh ghi m rng (E0 n E7) c th c s dng nh l cc thanh ghi 16-bit, hay phn 16-bit ln ca thanh ghi 32-bit. Khi thanh ghi m rng En c s dng nh l mt thanh ghi 16-bit, n c th cha bt k gi tr no, thm ch khi cc thanh ghi m rng tng ng Rn c s dng nh l mt thanh ghi a ch. (Nu thanh ghi a dng Rn c s dng trong ch nh a ch gin tip thanh ghi vi s tng trc/sau hay gim trc/sau v mt n v nh hay mn c pht sinh, th lc gi tr trong thanh ghi m rng tng ng En s b nh hng, c th l n s tng/hay gim mt dch sau khi thc hin xong cu lnh truy xut b nh) Tp hp lnh: Tt c cc cu lnh v cc ch nh a ch c th c s dng. Ch c 16 bit thp ca cc a ch hu dng (effective address-EA) l hp l. Bng vector ngoi l v cc a ch r nhnh gin tip b nh: Trong ch bnh thng, vng trn cng bt u ti a ch H0000 c dng cha bng vector ngoi l. Mt a ch nhy c lu trn 16 bit. Cu trc ca bng vector ngoi l c trnh by trong hnh 2.2.
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Hnh 2.2 Bng vector ngoi l (Ch bnh thng) Ch nh a ch gin tip b nh (@ @ aa:8) v gin tip b nh m rng c s dng trong cc cu lnh JMP v JSP. Mt a ch tuyt i 8-bit c cha trong m lnh ch nh mt v tr b nh. S thc thi s r nhnh n ni dung ca v tr b nh. Cu trc ca stack Cu trc stack ca PC ti mt lnh nhy ca mt chng trnh con v cu trc stack ca PC ti mt x l ngoi l c trnh by trong hnh 2.3. Cc ni dung ca PC c lu tr v lu li theo tng n v 16-bit.
Hnh 2.3 Cu trc Stack (Ch bnh thng) 2.2.2 Ch trung bnh Vng chng trnh trong ch trung bnh c m rng n 16Mbyte Khng gian a ch: Khng gian a ch ln nht c th truy xut c l 16Mbyte (tng ca vng chng trnh v d liu). i vi tng phn ring l th n 16 Mbyte cho vng chng trnh hoc n 64Kbyte cho vng d liu. Cc thanh ghi m rng: Cc thanh ghi m rng (t E0 n E7) c th c s dng nh l cc thanh ghi 16-bit, hay phn 16-bit ln ca thanh ghi 32-bit. Khi thanh ghi a dng En c s dng nh l cc thanh ghi 16-bit (tr cc cu lnh JMP v JSR), n c th cha bt k mt gi tr no thm ch khi m cc thanh ghi a dng Rn c s dng nh l mt thanh ghi a ch (Nu thanh ghi a dng Rn c tham kho trong ch nh a ch gin tip thanh ghi vi s tng trc/sau hay gim trc/sau v mt n v nh hay mn xy ra, th gi tr trong
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thanh ghi m rng En s b thay i) Tp lnh: Tt c cc lnh v cc ch nh a ch c th c s dng. Ch c 16 bit thp ca a ch hu dng (effective address- EA) l hp l v 8 bit cao l c m rng du (sign-extended) Bng vector ngoi l v cc a ch r nhnh gin tip b nh: trong ch trung bnh, phn trn ca b nh bt u a ch H000000 dng cha bng vector ngoi l. Mt a ch r nhnh c lu trong 32 bit. 8 bit cao s b b qua v ch c 24 bit thp mi c lu tr. Cu trc ca bng vector ngoi l c trnh by trong hnh 2.4. Ch nh a ch gin tip b nh (@ @aa:8) v gin tip b nh m rng c s dng trong cc cu lnh JMP v JSR. Mt a ch tuyt i 8-bit c cha trong m lnh nh r mt v tr b nh. S thc thi s ch n cc ni dung ca v tr b nh. Trong ch trung bnh, mt ton hng l 32-bit, cung cp mt a ch r nhnh 32-bit. 8 bit cao l c d tr v gi thit l H00 Cu trc Stack: Cu trc stack ca PC ti mt r nhnh chng trnh con v cu trc ca stack ca PC v CCR t mt x l ngoi l c trnh by trong hnh 2.5. Ni dung ca PC c lu tr theo n v 24-bit. 2.2.3 Ch nng cao Vng d liu c m rng n 4 Gbyte so vi ch trung bnh (middle mode) Khng gian a ch: Khng gian a ch ln nht 4 Gbyte c th c truy xut mt cch tuyn tnh. i vi cc vng ring l, vng chng trnh ln n 16Mbyte v vng d liu ln n 4Gbyte c th c cp pht. Cc thanh ghi m rng: Cc thanh ghi m rng (E0 n E7) c th c s dng nh l cc thanh ghi 16-bit, hay 16 bit cao ca cc thanh ghi 32-bit hay cc thanh ghi a ch Tp lnh: Tt c cc tp lnh v ch nh a ch u c th c s dng. Bng vector ngoi l v bng a ch r nhnh gin tip b nh: Trong ch nng cao, phn trn cng c bt u a ch H00000000 c cp pht cho bng vector ngoi l. Mt a ch r nhnh c lu tr trn 32 bit. 8 bit cao c b qua v 24 bit thp l c lu tr. Cu trc ca bng vector ngoi l c trnh by trong hnh 2.4
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Hnh 2.4 Bng vector ngoi l ( ch nng cao v trung bnh) Ch nh a ch gin tip b nh m rng (@ @vec:7) v gin tip b nh (@ @aa:8) l c s dng trong cc cu lnh JMP v JSR. Mt a ch tuyt i 8-bit c cha trong m lnh ch nh mt v tr b nh. S thc thi s nhy n ni dung ca v tr b nh. Trong ch m rng, mt ton hng l 32-bit (longword), cung cp mt a ch r nhnh 32-bit. 8 bit cao c d tr v gi thit n l H00
Hnh 2.5 Cu trc ca Stack (Ch trung bnh v nng cao) Cu trc Stack: Cu trc stack ca PC ti mt r nhnh ca chng trnh con v cu trc stack ca PC v CCR ti mt x l ngoi l c trnh by trong hnh 2.5. Ni dung ca PC c lu tr trong n v 24 bit. 2.2.4 Ch ti a Vng chng trnh c m rng n 4Gbyte. Khng gian a ch: Vng khng gian a ch ln nht c th truy xut mt cch tuyn tnh l 4Gbyte. Cc thanh ghi m rng (En): Cc thanh ghi m rng (E0 n E7) c th c s dng nh thanh ghi 16 bit, phn 16 bit cao ca thanh ghi 32-bit hay thanh
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ghi a ch. Tp lnh: Tt c cc lnh v ch nh a ch u c th c s dng. Bng vector ngoi l v a ch r nhnh gin tip b nh. Trong ch ti a, phn trn ca b nh c bt u a ch H0000 0000 dng cp pht cho bng vector ngoi l. Mt a ch r nhnh c lu tr trn 32 bit. Cu trc ca bng vector ngoi l c trnh by trong hnh 2.6.
Hnh 2.6 Bng vector ngoi l (ch ti a) Cc ch nh a ch gin tip b nh m rng (@ @vec:7) v gin tip b nh (@ @aa:8) u c s dng trong cc cu lnh JMP v JSR. Mt a ch tuyt i 8-bit c cha trong m lnh ch nh mt v tr b nh. S thc thi s r nhnh n ni dung ca v tr b nh. Trong ch ti a, mt ton hng c di 32-bit, cung cp mt a ch r nhnh 32-bit. Cu trc stack: Cu trc stack ca PC ti mt a ch r nhnh v cu trc ca PC v CCR ti mt x l ngoi l u c trnh by trong hnh 2.7. Ni dung ca PC c lu tr theo n v 32 bit. Cc ni dung ca thanh ghi EXR u c lu tr m khng cn quan tm n vic liu n c ang c s dng hay khng.
Hnh 2.7 Cu trc Stack (Ch ti a)
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2.3 c lnh (Fetch)

CPU H8SX c 2 ch c lnh: 16-bit v 32-bit. V vy m n ph hp vi rng ca bus b nh. Vic thit lp ch c lnh (instruction-fetch mode) khng nh hng n php ton (operation) ngoi tr cu lnh c lnh nh l truy xut d liu Ch : trong CPU H8SX/1582, mt lnh c c trong ch 32-bit.
2.4 Khng gian a ch

Hnh 2.8 cho thy mt Bn b nh (memory map) ca CPU H8SX. Cc khng gian a ch khng ging nhau ty thuc vo ch hot ng ca CPU.
Hnh 2.8 Bn b nh
2.5 Cc thanh ghi

CPU H8SX c cc thanh ghi bn trong nh hnh 2.9. C hai loi thanh ghi: cc thanh ghi a dng v cc thanh ghi iu khin. Cc thanh ghi iu khin l thanh ghi b m chng trnh 32-bit (PC), thanh ghi iu khin m rng 8-bit (EXR), thanh ghi m iu kin 8-bit (CCR), thanh ghi nn vector 32-bit (vector base register-VBR), thanh ghi nn a ch ngn 32-bit (SBR), v thanh ghi tch ly nhn 64-bit (multiplyaccumulate register MAC).
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Hnh 2.9 Cc thanh ghi ca CPU 2.5.1 Cc thanh ghi a nng CPU H8SX c 8 thanh ghi a dng 32-bit. Cc thanh ghi a dng c chc nng nh nhau v c th c s dng lm cc thanh ghi a ch ln thanh ghi d liu. Khi mt thanh ghi a dng c s dng lm cc thanh ghi d liu, n c th c truy xut nh cc thanh ghi 32-bit, 16-bit, hay 8-bit. Hnh 2.10 minh ha cc chc nng ca cc thanh ghi a dng. Khi cc thanh ghi a dng c s dng lm thanh ghi 32-bit hay cc thanh ghi d liu, chng c ch nh bi ER (ER0 n ER7). Khi cc thanh ghi a dng c s dng lm cc thanh ghi 16-bit, th cc thanh ghi ER c chia nh ra thnh cc thanh ghi 16-bit c ch nh bi E (E0 n E7) v R (R0 n R7). Chng l nhng thanh ghi tng ng nhau v mt chc nng, cung cp 16 thanh ghi 16-bit. Cc thanh ghi E (E0 n E7) cng c xem nh l cc thanh ghi m rng.
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Khi cc thanh ghi a dng c s dng nh cc thanh ghi 8-bit, th cc thanh ghi R c chia thnh cc thanh ghi 8-bit c t tn l RH (R0H n R7H) v RL (R0L n R7L). Cc thanh ghi ny u tng ng vi nhau v mt chc nng, cung cp ti a 16 thanh ghi 8-bit. Cc thanh ghi a dng ER (ER0 n ER7), R (R0 n R7), v RL (R0L n R7L) cng c s dng nh l cc thanh ghi nh ch s. Ty vo kch thc ton hng m c th la chn cc thanh ghi thch hp. Cc thanh ghi c th c chn mt cch c lp.
Hnh 2.10 Cch s dng cc thanh ghi Thanh ghi a dng ER7 ngoi chc nng l mt thanh ghi a dng n cn c chc nng ca mt con tr stack (SP), v c s dng hon ton trong vic x l ngoi l v r nhnh chng trnh con. Hnh 2.11 s cho thy stack.
Hnh 2.11 Stack 2.3.2 Thanh ghi b m (PC) PC l mt thanh ghi b m chng trnh 32-bit dng ch a ch ca cu lnh s c thc thi k tip. Chiu di ca tt c cc cu lnh ca CPU l 16 bit (mt word) hay l mt b s ca 16 bit. V vy, bit c trng s nh nht s c b qua (Khi m lnh c c, bit ny c gn l 0). 2.5.3 Thanh ghi m iu kin
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Thanh ghi CCR l mt thanh ghi 8-bit m cha thng thi v trng thi ca CPU, bao gm c cho php ngt (interrupt mask) (I), cc bit ngi dng (user-UI,U), c nh na (H), c du (N), c zero (Z), c trn (V) v c nh (C). Cc thao tc c th thc hin trn cc bit ca thanh ghi CCR l cc lnh LDC, STC, ANDC, ORC v XORC. C N, Z, V, v C l c s dng vi vai tr l iu kin nhy cho cc cu lnh nhy (Bcc).
Bit Tn Gi tr R/W bit khi to 7 I 1 R/W Bit mt n ngt qung
c t
Che ngt qung khi n c thit lp l 1. Bit ny s c thit lp l 1 khi bt u mt x l ngoi l. 6 UI Khng xc nh R/W Bit ngi dng hay bit mt n ngt qung C th c ghi v c bng phn mm bng cch s dng cc lnh LDC, STC, ANDC, ORC, v XORC. Bit ny cng c th c s dng nh l cc bit mt n ngt qung R/W C nh na Khi cc lnh ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, hay NEG.B c thc thi, c ny c thit lp l 1 nu c mt hot ng mn hay nh bit th 3, v s c xa xung 0 nu ngc li. Khi cc cu lnh ADD.W, SUB.W, CMP.W, hay NEG.W c thc thi th c ny c thit lp l 1 nu c mt hot ng nh hay mn c xy ra bit th 11, v n s b xa xung 0 nu ngc li. Khi cu lnh ADD.L, SUB.L, CMP.L hay NEG.L c thc thi, c ny s c thit lp l 1 nu c mt hot ng mn hay nh xy ra bit th 27, v b xa xung 0 nu ngc li. R/W Bit ngi dng C th c vit v c t phn mm bng cch s dng cc cu lnh LDC, STC, ANDC, ORC v XORC R/W C du Lu tr gi tr ca bit cao nht (c xem nh l bit du) ca d liu R/W C Zero c thit lp l 1 ch d liu bng 0, v xa xung 0 ch d liu khc 0
Khng xc nh
Khng xc nh
Khng xc nh
Khng xc nh
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Khng xc nh
R/W
C trn c thit lp l 1 khi mt c mt s trn s hc xy ra, v c xa xung 0 nu ngc li
Khng xc nh
R/W
C nh c thit lp l 1 khi m 1 hot ng mn xy ra, v c xa xung 0 nu ngc li. Mt c nh cc kh nng sau: Nh t mt kt qu ca php cng Mn t mt kt qu ca php tr Nh t mt kt qu ca php dch hay php quay C nh cng c s dng nh l bit tch ly (accumulator) bi cc cu lnh x l bit
2.5.4 Thanh ghi iu khin m rng (EXR) EXR l mt thanh ghi 8-bit m cha bit theo di T (trace bit) v 3 bt cho php ngt qung (I2 n I0). Ta c th thao tc ln cc bit ca thanh ghi EXR bng cc lnh LDC, STC, ANDC, ORC, v XORC.
Bit 7 Tn Bit T Gi tr khi to 0 R/ W R/W Bit theo di Khi bit ny c thit lp l 1, th mt ngoi l theo di (trace exception) s c pht sinh mi khi mt cu lnh c thc thi. Khi bit ny c xa xung 0, th cc cu lnh c thc thi theo tun t. c t
6 ti 3 2 1 0
---
Tt c l 1
R/W
Khng dng Cc bt ny lun c c vi gi tr 1
I2 I1 I0
1 1 1
R/W R/W R/W
Cc bit cho php ngt qung Nhng bit ny ch r cp che giu ngt qung
2.5.5 Thanh ghi nn vector (VBR) VBR l mt thanh ghi 32-bit trong 20 bit cao l hp l, 12 bit thp ca thanh ghi ny c gi tr l 0. Thanh ghi ny l mt a ch nn ca bng vector ngoi l ngoi tr reset v ngoi l to bi CPU (gin tip b nh m rng cng nm ngoi
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mc tiu). Gi tr khi u l H0000 0000. Cc ni dung ca VBR b thay i vi cu lnh LDC v STC. 2.5.6 Thanh ghi nn a ch ngn (SBR) SBR l mt thanh ghi 32-bit m trong 24 bit cao l hp l. 8 bit thp c c l cc bit 0. Trong ch nh a ch tuyt i 8-bit, thanh ghi ny c s dng vi vai tr l a ch cao. Gi tr khi to l HFFFF FF00. Ni dung ca SBR s b thay i vi cu lnh LDC v STC. 2.5.7 Thanh ghi tch ly nhn (MAC) MAC l mt thanh ghi 64-bit n lu tr cc kt qu ca cc php ton nhn v tch ly (multiply-and-accumulate). N bao gm 2 thanh ghi 32-bit l MACH v MACL. 10 bit thp ca MACH l hp l, cc bit cao cn li c m rng du (sign extended). Ni dung ca MAC s b thay i vi cc cu lnh MAC, CLRMAC, LDMAC, STMAC. 2.5.8 Cc gi tr khi u ca cc thanh ghi X l ngoi l reset (reset exception handling) s ti a ch bt u t bng vector vo thanh ghi PC, xa bit T trong thanh ghi EXR xung 0, v thit lp bit I trong thanh ghi CCR v EXR ln 1. Cc thanh ghi a dng, MAC, v cc bit khc trong thanh ghi CCR khng c khi to. C th l, gi tr khi u ca con tr chng (stack pointer) (ER7) l khng xc nh. Chnh v vy m thanh ghi SP s c khi u bng mt lnh MOV.L sau khi khi ng li.
2.6 nh dng d liu

CPU H8SX c th x l d liu 1-bit, 4 bit BCD, 8-bit (byte), 16-bit (word), v 32-bit (longword). Cc cu lnh thao tc trn bit tc dng ln mt bit d liu bng cch truy xut bit th n (n=0, 1, 2, , 7) ca d liu ton hng. Cc cu lnh iu ch s thp phn DAA v DAS x l cc byte d liu nh l hai s d liu BCD 4-bit. 2.6.1 nh dng d liu thanh ghi a nng Hnh 2.12 trnh by nh dng d liu trong thanh ghi m rng.
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Hnh 2.12 nh dng d liu thanh ghi a dng 2.6.2 nh dng d liu b nh: Hnh 2.13 trnh by nh dng d liu trong b nh. CPU H8SX c th truy xut mt word d liu v mt longword d liu m c lu tr trong bt k mt a ch no trong b nh. Khi m mt word d liu bt u mt a ch l hay mt longword d liu bt u mt a ch m khng phi l bi s ca 4, th mt chu k bus c chia thnh 2 hay 3 ln truy xut. V d, khi mt longword d liu bt u mt a ch l, th chu k bus c chi thnh 3 ln truy xut: 1 ln truy xut byte, 1 ln truy xut word v 1 ln truy xut byte. Trong trng hp ny, cc ln truy xut c gi thit l thuc cc chu k ring r. Tuy nhin, cc cu lnh c c, word v longword d liu c truy xut trong sut qu trnh thc thi ca cc cu lnh thao tc stack (stack manipulation), thao tc bng r nhnh, cc cu lnh truyn khi v cc cu lnh MAC s c cp pht a ch chn. Khi SP (ER7) c s dng nh l mt thanh ghi a ch truy xut stack, th kch thc ton hng phi l word hoc l longword.
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Hnh 2.13 nh dng d liu b nh
2.7 Tp lnh
CPU H8SX c 87 loi cu lnh. Tp lnh c chia theo chc nng nh trnh by bng 2.1. Php ton s hc, php ton lun l, dch, v cc cu lnh thao tc trn bit, trong ti liu ny c gi l cu lnh php ton (operation instruction). Bng 2.1 Phn loi cu lnh
Chc nng truyn d liu MOV MOVFPE*6, MOVTPE*6 POP, PUSH*1 LDM, STM MOVA Truyn khi EEPMOV MOVM D MOVSD Cc php ADD, ADDX, SUB, SUBX, CMP, NEG, Cu lnh Kch thc B/W/L B W/L L B/W*2 B B/W/L B B/W/L 27 3 6 Loi
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ton s hc
INC, DEC DAA, DAS ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS MULU, DIVU, MULS, DIVS MULU/U, MULS/U EXTU, EXTS TAS MAC LDMAC, STMAC CLRMAC B L B/W W/L L W/L B ------B/W/L B/W/L B 4 8 20
Cc php AND, OR, XOR, NOT ton lun l Dch Thao tc trn bit SHLL, SHLR, SHAL, SHAR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST BSET/EQ, BSET/NE, BCLR/EQ, BCLR/NE, BSTZ, BISTZ BFLD, BFST R nhnh BRA/BS, BRA/BC, BSR/BS, BSR/BC Bcc*5, JMP, BSR, JSR, RTS RTS/L BRA/S iu khin h thng TRAPA, RTE, SLEEP, NOP RTE/L LDC, STC, ANDC, ORC, XORC
B B B*3 --L*5 ----L*5 B/W/L 10 9
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Tng
87
Ghi ch: B: kch thc l byte (8 bit) H: Kch thc l word (16 bit) L: kch thc l longword (32 bit) Ch : 1. POP.W Rn v PUSH.W Rn tng ng vi MOV.W @SP+, Rn v MOV.W Rn, @-SP. POP.L ERn v PUSH.L ERn tng ng vi MOV.L @SP+, ERn v MOV.L ERn, @ -SP. 2. 3. 4. 5. 6. Kch thc d liu s c cng vi dch Kch thc ca d liu ch mt iu kin r nhnh Bcc l tn chung ca cu lnh r nhnh khng iu kin kch thc ca thanh ghi a dng c lu li Khng cho php trong vi iu khin ny.
2.7.1 Cc lnh v cc ch nh a ch Bng 2.2 S kt hp ca cc cu lnh v cc ch nh a ch (1)

Phn loi Cu lnh Kch thc #xx Rn @ @( ER d,E n Rn ) @(d, RnL. B/ @ERn/ @ER n+/ @a a:8 @aa: 16/ @aa: 32 ---
Rn.W / @ER n-/ ERn. @+E L) Rn chuyn MOV d liu MOVFPE, MOVTPE*1
2
B/W/L S B B
SD S/D S/D
SD
SD
SD
SD S/D
SD
S/D*1
POP, PUSH W/L LDM, STM L
S/D S/D
S/D*2 S/D*2
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MOVA*4 chuyn EEPMOV khi MOVMD MOVSD
B/W B B/W/L B S
S SD *3 SD *3 SD *3
Php ADD, CMP B tnh s B hc B B W/L SUB B B B B W/L ADDX, SUBX
D S D
D D S SD
D D S SD SD D D S SD SD
D D S
D D S SD SD
S S
SD
SD D
D D S
D D S SD SD
S D
D S SD
SD SD
SD
B/W/L S B/W/L S B/W/L S
SD SD*5 D D D
INC, DEC ADDS, SUBS
B/W/L L
DAA, DAS B MULXU, DIVXU MULU, DIVU W/L S:4 B/W S:4
SD
SD
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MULXS, DIVXS MULS, DIVS NEG
B/W W/L B W/L
S:4 S:4
SD SD D D D D D D D D D D D D D D D D D D D D
EXTU, EXTS TAS MAC CLRMAC LDMAC STMAC Php ton logic AND, OR, XOR
W/L B # # # # B B B W/L S
O S D S D D S SD SD D D D D D D D D D D D D D D D D D D SD D D D D D S SD SD D D D D D S SD SD D D D D D S SD SD D D D D D D D S D S SD SD D D D D
NOT
B W/L
Dch
SHLL, SHLR
B W/L*6 B/W/L *7
SHAL, SHAR ROTL, ROTR ROTXL, ROTXR
B W/L
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Thao tc trn bit
BSET, BCLR, BNOT, BTST, BSET/cc, BCLR/cc BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST, BSTZ, BISTZ
Thao tc bit R nhnh
BFLD BFST BRA/BS, 8 BRA/BC*
B B B
D S
S D S
S D S
S D S
BSR/BS, 8 BSR/BC* iu khin h thng LDC (CCR, EXR) LDC (VBR, SBR)
B/W*9
S*10
38
STC (CCR, EXR) STC (VBR, SBR) ANDC, ORC, XORC SLEEP NOP
B/W*9
D*11
-----
Ghi ch: d: S: D: SD: S/D S:4 Ch : 1. Ch @aa:16 l hp l. 2. @ERn+ vi vai tr l mt ton hng ngun v @-ERn- vi vai tr l mt ton hng ch. 3. c ch nh bi ER5 vi vai tr l a ch ngun v ER6 vi vai tr l a ch ch cho vic truyn d liu. 4. Kch thc d liu s c cng vi dch chuyn. 5. Ch c @ERn- l hp l. 6. Khi s lng bit c dch chuyn l 1, 2, 4, 8, hay 16. 7. Khi s lng bit c dch chuyn c ch nh bi 5-bit d liu trung gian hay mt thanh ghi a dng. 8. Kch thc d liu ch nh mt iu kin r nhnh 9. Byte trong trng hp trc tip hay gin tip thanh ghi, cn ngc li l word 10. Ch c @ERn+ l hp l. 11. Ch c @-ERn l hp l. d: 16 hay d:32 C th s dng vi vai tr l ton hng ngun C th s dng vi vai tr l ton hng ch C th s dng vi vai tr l ton hng ngun hay ch hoc c hai C th s dng vi vai tr hoc l ton hng ngun hoc l ton hng ch 4-bit d liu trung gian c th s dng vi vai tr l mt ton hng ngun.
39
12. Khng cho php trong Vi iu khin ny. Bng 2.2 S kt hp cc cu lnh v cc ch nh a ch (2)
Ch nh a ch @ER n @(d, PC) @(RnL. B/Rn.W/ ERn.L, PC) @ aa :2 4 @ aa: 32 @ @ aa: 8 @@v ec:7 --
Phn loi
Cu lnh BRA/B S, BRA/B C BSR/BS , BSR/BC Bcc BRA BRA/S JMP BSR JSR RTS, RTS/L TRAPA RTE, RTE/L
Kch th c ---
---
------------------O O
O O O* O O O O O O O O O O O O O
Ghi ch: D: d:8 hay d: 16 Ch : * ch c @(d:8,PC) l hp l 2.7.2 Bng cc lnh c chia theo chc nng Cc bng t 2.4 n 2.11 m t cc cu lnh theo tng nhm chc nng. Cc k hiu c s dng trong cc bng ny c miu t trong bng 2.3
40
Bng 2.3 K hiu cc php ton c t k hiu cc php ton

Rd Rs Rn ERn (EAd) (EAs) EXR CCR VBR SBR N Z V C PC SP #IMM disp + ^ Thanh ghi a dng (ch)* Thanh ghi a dng (ngun)* Thanh ghi a dng Thanh ghi a dng (thanh ghi 32-bit) Ton hng ch Ton hng ngun Thanh ghi iu khin m rng Thanh ghi m iu kin Thanh ghi nn vector Thanh ghi nn a ch ngn C du trong thanh ghi CCR C zero trong thanh ghi CCR C trn trong thanh ghi CCR C nh trong thanh ghi CCR Thanh ghi b m Thanh ghi Stack D liu trc tip dch Php cng Php tr Php nhn Php chia Php AND lun l Php hay lun l
41
Php exclusive hay lun l ~ :8/:16/:24/:32 Dch chuyn Php not lun l (b lun l) Chiu di 8, 16, 24, hay 32 bit
Ch : * Cc thanh ghi a dng bao gm cc thanh ghi 8-bit (t R0H n R7H, R0L n R7L), cc thanh ghi 16-bit (R0 n R7, E0 n E7), v cc thanh ghi 32-bit (t ER0 n ER7). Bng 2.4 Cc lnh chuyn d liu
Cu lnh MOV Kch thc B/W/L Chc nng #IMM (EAd), (EAs) (EAd) Chuyn d liu gia d liu trc tip, thanh ghi a dng v b nh. MOVFPE* MOVTPE* POP B B W/L (EAs) Rd Rs (EAs) @SP+ Rn Chuyn d liu trn stack vo li thanh ghi PUSH W/L Rn @-SP Lu tr ni dung trn thanh ghi a dng vo stack LDM L @SP+ Rn (register list) Chuyn d liu trn stack vo nhiu thanh ghi a dng. 2, 3, hay 4 thanh ghi a dng m c ch s thanh ghi lin tip nhau. STM L Rn (register list) @-SP Lu ni dung ca nhiu thanh ghi a dng ln stack. 2, 3 hay 4 thanh ghi a dng m c ch s thanh ghi lin tip c c s dng. MOVA B/W EA Rd M rng zero v dch ni dung ca mt thanh ghi a dng xc nh hay d liu b nh v cng chng vi mt dch. Kt qu c lu tr li thanh ghi a dng.
Ch : * khng cho php trong vi iu khin

42
Bng 2.5 Cc lnh chuyn khi d liu

Cu lnh EEPMOV.B EEPMOV.W Kch thc B Chc nng Chuyn mt khi d liu Chuyn cc byte d liu m bt u ti mt v tr b nh c ch nh bi ER5 vo mt v tr b nh c ch nh bi ER6. S lng byte d liu c chuyn c ch ra bi thanh ghi R4 hay R4L. B Chuyn mt khi d liu Chuyn cc byte d liu m bt u ti mt v tr c ch ra bi thanh ghi ER5 n v tr b nh c ch ra bi thanh ghi ER6. S lng byte d liu cn chuyn c trong thanh ghi R4. MOVMD.W W Chuyn mt khi d liu Chuyn cc word d liu m bt u ti mt v tr c ch ra bi thanh ghi ER5 n v tr b nh c ch ra bi thanh ghi ER6. S lng word d liu cn chuyn c trong thanh ghi R4. MOVMD.L L Chuyn mt khi d liu Chuyn cc longword d liu m bt u ti mt v tr c ch ra bi thanh ghi ER5 n v tr b nh c ch ra bi thanh ghi ER6. S lng longword d liu cn chuyn c trong thanh ghi R4. MOVSD.B B Chuyn mt khi d liu vi vic kim tra d liu zero Chuyn cc byte d liu m bt u v tr b nh c ch ra bi thanh ghi ER5 n v tr b nh c ch ra bi ER6. S lng byte d liu c chuyn c t trong thanh ghi R4. Khi d liu zero c pht hin trong qu trnh chuyn d liu, th qu trnh chuyn d liu s dng v thc thi cu lnh r nhnh n mt a ch xc nh trc.
MOVMD.B
Bng 2.6 Cc lnh v php ton s hc

Cu lnh ADD SUB kch thc chc nng B/W/L (EAd) #IMM + (EAd), (EAd) (EAs) + (EAd) Thc hin php cng hay php tr gia d liu trc tip, thanh ghi a dng, v b nh. Byte d liu trc tip khng th tr i byte d liu trong thanh ghi a dng c.
43
ADDX SUBX
B/W/L
(EAd) #IMM C + (EAd), (EAd) (EAs) C + (EAd)Thc hin php cng hay tr c nh trn cc d liu trc tip, cc thanh ghi a dng hay b nh. C th s dng ch nh a ch gin tip thanh ghi vi s gim sau hay gin tip thanh ghi ch nh v tr b nh. Rd 1 + Rd, Rd 2 + Rd Tng hay gim mt thanh ghi a dng 1 hay 2 n v. (i vi trng hp ton hng l 1 byte th ch c th tng hay gim ch mt n v).
INC DEC
B/W/L
ADDS SUBS DAA DAS
Rd 1 + Rd, Rd 2 + Rd, Rd 4 + Rd Cng hay tr 1, 2, hay 4 vo 1 thanh ghi a dng
Rd (decimal adjust) + Rd iu chnh kt qu php cng hay php tr trong mt thanh ghi m rng bi hot ng tham kho n thanh ghi CCR to ra d liu 2 s 4 bit BCD
MULXU
B/W
Rd Rs + Rd Thc thi php nhn khng du trn d liu trong hai thanh ghi a dng: 8 bit x 8 bit + 16 bit, hoc 16 bit x 16 bit +32 bit.
MULU
W/L
Rd Rs + Rd Thc thi php nhn khng du trn d liu trong hai thanh ghi a dng: 8 bit x 8 bit + 16 bit, hoc 16 bit x 16 bit +32 bit.
MULU/U
Rd Rs + Rd Thc thi php nhn khng du trn hai thanh ghi a dng ( 32 bit x 32 bit + upper 32 bit)
MULXS
B/W
Rd Rs + Rd Thc thi php nhn c du trn d liu trong hai thanh ghi a dng: 8 bit x 8 bit + 16 bit, hoc 16 bit x 16 bit +32 bit.
MULS
W/L
Rd Rs + Rd Thc thi php nhn c du trn d liu trong hai thanh ghi a dng:8 bit x 8 bit + 16 bit, hoc 16 bit x 16 bit +32 bit.
MULS/U
Rd Rs + Rd Thc thi php nhn c du trn hai thanh ghi a dng ( 32 bit x 32 bit + upper 32 bit)
44
Cu lnh DIVXU
Kch thc B/W
Chc nng Rd Rs + Rd Thc thi php chia khng du trn hai thanh ghi a dng: hoc l 16 bit 8 bit + 8 bit cha thng v 8 bit cha phn d, hoc 32 bit 16 bit + 16 bit cha thng v 16 bit cha phn d.
DIVU
W/L
Rd Rs + Rd Thc thi php chia khng du trn hai thanh ghi a dng: hoc l 16 bit 16 bit + 16 bit cha thng, hoc 32 bit 32 bit + 32 bit cha thng.
DIVXS
B/W
Rd Rs + Rd Thc thi php chia c du trn hai thanh ghi a dng: hoc l 16 bit 8 bit + 8 bit cha thng v 8 bit cha phn d, hoc 32 bit 16 bit + 16 bit cha thng v 16 bit cha phn d.
DIVS
W/L
Rd Rs + Rd Thc thi php chia khng du trn hai thanh ghi a dng: hoc l 16 bit 16 bit + 16 bit cha thng, hoc 32 bit 32 bit + 32 bit cha thng.
CMP
B/W/L (EAd) - #IMM, (EAd) - (EAs) So snh d liu gia d liu trc tip, cc thanh ghi a dng hay b nh v lu kt qu vo thanh ghi CCR
NEG
B/W/L 0 - (EAd) + (EAd) Ly s b 2 ca d liu (b 2 s hc) trong mt thanh ghi a chc nng hoc ni dung ca mt v tr b nh
EXTU
W/L
(EAd) (zero extension) + (EAd) Thc hin m rng zero trn 8 hay 16 bit thp ca d liu trong mt thanh ghi a dng hay ca b nh thnh 1 word hay 1 longword.
EXTS
W/L
(EAd) (sign extension) + (EAd) Thc hin m rng du trn 8 hay 16 bit thp ca d liu trong mt thanh ghi a dng thnh kch thc word hay longword.
TAS
@ERd 0, 1 + (<bit 7> of @EAd) Kim tra ni dung ca b nh, v thit lp bit c trng s cao nht (bit 7) ln 1.
45
MAC
---
(EAs) (EAd) + MAC + MAC Thc hin vic nhn c du trn ni dung b nh v cng kt qu vo MAC
CLRMAC
---
0 + MAC Xa MAC xung 0
LDMAC
---
Rs + MAC Ti gi tr t mt thanh ghi a dng vo MAC
STMAC
---
MAC + Rd Lu gi tr t MAC vo mt thanh ghi a dng
Bng 2.7 Cc cu lnh php ton lun l

Cu lnh AND Kch thc Chc nng
B/W/L (EAd) ( #IMM + (EAd), (EAd) ( (EAs) + (EAd) Thc hin php AND lun l gia d liu trc tip, cc thanh ghi v b nh.
OR
B/W/L (EAd) ) #IMM + (EAd), (EAd) ) (EAs) + (EAd) Thc hin php hay lun l gia d liu trc tip, cc thanh ghi hay b nh vi nhau.
XOR
B/W/L (EAd) * #IMM + (EAd), (EAd) * (EAs) + (EAd) Thc hin php exclusive hay lun l gia d liu trc tip, cc thanh ghi v b nh.
NOT
B/W/L
(EAd) + (EAd) Ly b 1 ca ni dung ca mt thanh ghi a dng hay mt v tr b nh
Bng 2.8 Cc cu lnh ca php ton dch

Cu lnh SHLL SHLR Kch thc Chc nng
B/W/L (EAd) (shift) + (EAd) Thc hin php shift lun l trn ni dung ca mt thanh ghi a dng hay ca mt v tr b nh. Ni dung ny c th c shift 1, 2, 4, 8, hay 16 bit. Ni dung ca mt thanh ghi a dng c th shift mt s lng bit ty . Trong trng hp ny, th s bit c ch nh bi 5 bit d liu trc tip hoc 5 bit thp ca ni
46
dung ca mt thanh ghi a dng. SHAL SHAR B/W/L (EAd) (shift) + (EAd) Thc hin php shift s hc trn ni dng ca mt thanh ghi hay ca mt v tr b nh. Php shift ch c th p dng shift 1 hay 2 bit. B/W/L (EAd) (rotate) + (EAd) Quay ni dung ca mt thanh ghi a dng hay mt ca mt v tr b nh. Php quay 1 hay 2 bit l hp l. B/W/L (EAd) (rotate) + (EAd) Quay ni dung ca mt thanh ghi a dng hay ca mt v tr b nh c s dng c nh. Php quay ch s dng quay 1 hay 2 bit
ROTL ROTR ROTXL ROTXR
Bng 2.9 Cc cu lnh thao tc bit

Cu lnh BSET Kch thc B Chc nng 1 (<bit-No.> of <EAd>) Thit lp ni dung ca mt bit ca mt thanh ghi a dng hay ca mt v tr b nh ln 1. S th t ca bit c chia ra bi 3 bit d liu trc tip hay l 3 bit thp ca mt thanh ghi a dng. BSET/cc B cc, 1 (<bit-No.> of <EAd>) Nu iu kin theo l thuyt c tha mn, cu lnh ny s thit lp s mt bit xc nh trong mt v tr b nh ln 1. S th t ca bit c th c xc nh bi 3-bit d liu trc tip, hay bi 3 bit thp ca mt thanh ghi a dng. Trng thi c Z c th c xem nh l mt iu kin. BCLR B 0 (<bit-No.> of <EAd>) Xa ni dung ca mt bit ca mt thanh ghi a dng hay ca mt v tr b nh xung 0. S th t ca bit c chi ra bi 3 bit d liu trc tip hay l 3 bit thp ca mt thanh ghi a dng. BCLR/cc B if cc, 0 (<bit-No.> of <EAd>) Nu iu kin theo l thuyt c tha mn, cu lnh ny s thit lp s xa mt bit xc nh trong mt v tr b nh xung 0. S th t ca bit c th c xc nh bi 3-bit d liu trc tip, hay bi 3 bit thp ca mt thanh ghi a dng. Trng thi c Z c th c xem nh l mt iu kin BNOT B (<bit-No.> of <EAd>) (<bit-No.> of <EAd>) o ni dung ca mt bit trong mt thanh ghi a dng hay trong
47
mt v tr b nh. S th t ca bit ny c th c ch ra bi 3 bit ca d liu trc tip hay 3 bit thp ca mt thanh ghi a dng. BTST B (<bit-No.> of <EAd>) Z Kim tra ni dung ca mt bit ca mt thanh ghi a dng hay mt v tr b nh v thit lp hay xa c Z tng ng. Ch s ca bit cn kim tra c t trong 3-bit d liu trc tip hay trong 3-bit thp ca mt thanh ghi a dng. BAND B C (<bit-No.> of <EAd>) C
Thc hin php AND c nh vi mt bit trong mt thanh ghi a dng hay mt v tr b nh v lu kt qu vo c nh. S th t ca bit c ch ra bi 3-bit d liu trc tip. BIAND B C [, (<bit-No.> of <EAd>)] C
Thc hin php AND c nh vi gi tr o ca mt bit trong mt thanh ghi a dng hay mt v tr b nh v lu kt qu vo c nh. S th t ca bit c ch ra bi 3-bit d liu trc tip. BOR B C (<bit-No.> of <EAd>)C
Thc hin php hay c nh vi mt bit trong mt thanh ghi a dng hay mt v tr b nh v lu kt qu vo c nh. S th t ca bit c ch ra bi 3-bit d liu trc tip. BIOR B C [~ (<bit-No.> of <EAd>)] C
Thc hin php hay c nh vi gi tr o ca mt bit trong mt thanh ghi a dng hay mt v tr b nh v lu kt qu vo c nh. S th t ca bit c ch ra bi 3-bit d liu trc tip. BXOR B C (<bit-No.> of <EAd>) + C
Thc hin php Exclusive-OR c nh vi mt bit trong mt thanh ghi a dng hay mt v tr b nh v lu kt qu vo c nh. S th t ca bit c ch ra bi 3-bit d liu trc tip. BIXOR B C [~ (<bit-No.> of <EAd>)] C
Thc hin php exclusive-OR c nh vi gi tr o ca mt bit trong mt thanh ghi a dng hay mt v tr b nh v lu kt qu vo c nh. S th t ca bit c ch ra bi 3-bit d liu trc tip. BLD B (<bit-No.> of <EAd>) C Chuyn ni dung ca mt bit ca mt thanh ghi a dng hay mt v tr b nh vo c nh. S th t ca bit c ch ra bi 3-bit d liu trc tip.
48
BILD
~ (<bit-No.> of <EAd>) C Chuyn gi tr o ca ni dung ca mt bit trong mt thanh ghi a dng hay mt v tr b nh vo c nh. S th t ca bit c ch ra bi 3-bit d liu trc tip.
BST
C (<bit-No.> of <EAd>) Chuyn gi tr ca c nh vo mt bit trong thanh ghi a dng hay mt v tr b nh. S th t ca bit c ch ra bi 3-bit d liu trc tip.
BSTZ
Z (<bit-No.> of <EAd>) Chuyn gi tr ca c zero vo mt bit trong thanh ghi a dng hay mt v tr b nh. S th t ca bit c ch ra bi 3-bit d liu trc tip.
BIST
C (<bit-No.> of <EAd>) Chuyn gi tr o ca c nh vo mt bit trong thanh ghi a dng hay mt v tr b nh. S th t ca bit c ch ra bi 3bit d liu trc tip.
BISTZ
Z (<bit-No.> of <EAd>) Chuyn gi tr o ca c zero vo mt bit trong thanh ghi a dng hay mt v tr b nh. S th t ca bit c ch ra bi 3bit d liu trc tip.
BFLD
(EAs) (bit field) + Rd Chuyn ni dung mt khi cc bit (bit field) trong v tr b nh vo cc bit thp ca mt thanh ghi a dng.
BFST
Rs (EAd) (bit field) Chuyn ni dung ca cc bit thp trong mt thanh ghi a dng vo mt khi cc bit trong ni dung v tr b nh (memory location contents)
Bng 2.10 Cc cu lnh r nhnh

Cu lnh BRA/BS BRA/BC BSR/BS BSR/BC B Kch thc B Chc nng Kim tra mt bit trong ni dung ca mt v tr b nh. Nu iu kin c tha mn, th thc hin vic r nhnh n mt a ch xc nh Kim tra mt bit trong ni dung ca mt v tr b nh. Nu iu kin c tha mn th thc thi vic r nhnh n chng trnh con ti mt a ch xc nh.
49
Bcc BRA/S
-----
R nhnh n mt a ch xc nh nu iu kin c tha mn. R nhnh khng iu kin n mt a ch sau khi thc thi cu lnh k tip. Cu lnh k tip nn l mt cu lnh di 1-word ngoi tr cc cu lnh chuyn khi v r nhnh R nhnh khng iu kin n mt a ch xc nh R nhnh n mt chng trnh con ti mt a ch xc nh R nhnh n mt chng trnh con ti mt a ch xc nh Lnh tr v ca mt chng trnh con Tr v t mt chng trnh con, phc hi d liu t stack vo li cc thanh ghi a dng.
JMP BSR JSR RTS RTS/L
-----------
Bng 2.11 Cc lnh iu khin h thng

Cu lnh TRAPA RTE RTE/L SLEEP LDC Kch thc --------B/W Chc nng Khi ng x l ngoi l cu lnh by. Lnh tr v ca chng trnh x l ngoi l Lnh tr v ca mt chng trnh x l ngoi l, phc hi d liu t stack vo cc thanh ghi a dng. Gy ra mt s chuyn i sang trng thi ngt in(power-down state) #IMM CCR, (EAs) CCR, #IMMEXR, (EAs) EXR Np d liu trc tip hay ni dung ca mt thanh ghi hay mt v tr b nh vo thanh ghi CCR hay EXR. Mc d thanh ghi CCR v EXR l cc thanh ghi 8-bit, vic dch chuyn vi kch thc mt word cng c th thc hin gia chng vi b nh. Trong trng hp th 8 bit cao l hp l L Rs VBR, Rs SBR Chuyn ni dung ca thanh ghi a dng vo thanh ghi VBR hay SBR STC B/W CCR (EAd), EXR (EAd) Chuyn ni dung ca thanh ghi CCR hay EXR vo thanh ghi m rng hay b nh.
50
Mc d thanh ghi CCR v EXR l cc thanh ghi 8-bit, nhng mt s dch chuyn vi kch thc 1 word cng c th c thc hin gia chng vi b nh. Trong trng hp ny th 8-bit cao s hp l. L VBR Rd, SBR Rd Chuyn ni dung ca VBR hay SBR vo mt thanh ghi a dng ANDC B CCR #IMM CCR, EXR #IMM EXR
Thc hin php AND lun l gia ni dung ca thanh ghi CCR hay EXR vi d liu trc tip ORC B CCR #IMM CCR, EXR #IMM EXR
Thc hin php hay lun l gia ni dung ca thanh ghi CCR hay EXR vi d liu trc tip XORC B CCR #IMM CCR, EXR #IMM EXR
Thc hin php exclusive-OR lun l gia ni dung ca thanh ghi CCR hay EXR vi d liu trc tip NOP PC + 2 PC Khng lm g c ch vic tng thanh ghi b m
2.7.3 nh dng cu lnh cn bn (khun mu cc cu lnh cn bn) Cu lnh ca CPU H8SX bao gm cc khi theo n v 2 byte (1 word). Mt cu lnh bao gm mt trng tc v (operation-op field), mt trng thanh ghi (r field), mt trng m rng a ch hiu dng (EA field), v mt trng iu khin (cc). Hnh 2.4 trnh by cc v d v khun mu cu lnh (instruction format)
51
Hnh 2.14 nh dng cu lnh Trng tc v (thao tc) ch chc nng ca cu lnh, v ch ch nh a ch v thao tc c thc hin ln ton hng. Trng tc v lun bao gm 4 bit u tin ca lnh. Mt vi cu lnh c hai trng tc v. Trng thanh ghi ch mt thanh ghi a dng. Cc thanh ghi a ch c ch ra bi 3 bit, cc thanh ghi d liu c ch ra bi 3 hay 4 bit. Mt vi lnh c hai trng thanh ghi. Mt vi lnh khng c trng ny. M rng a ch hiu dng 8, 16, hay 32 bit xc nh d liu trc tip, mt a ch tuyt i hay mt dch Trng iu khin Xc nh iu kin r nhnh ca cu lnh Bcc. CPU H8SX h tr 11 ch nh a ch c lit k trong bng 2.12. Mi cu lnh s dng mt tp hp con ca cc ch nh a ch ny. Cc cu lnh thao tc trn bit s dng ch nh a ch trc tip thanh ghi, gin tip thanh ghi hay a ch tuyt i l ch mt ton hng, v ch nh a ch trc tip thanh ghi (cc cu lnh BSET, BCLR, BNOT, v BTST) hay trc tip ch s th t ca bit trong ton hng.
SST Ch nh a ch 1 2 3 4 Trc tip thanh ghi Gin tip thanh ghi Gin tip thanh ghi vi dch Gin tip thanh ghi ch s vi dch Gin tip thanh ghi vi s tng sau Gin tip thanh ghi vi s gim trc Gin tip thanh ghi vi s tng trc Gin tip thanh ghi vi s gim sau K hiu ERn @ERn @(d:2,ERn)/@(d:16,ERn)/@(d:32,ERn) @(d:16, RnL.B)/ @(d:16,Rn.W)/ @(d:16,ERn.L) @(d:32, RnL.B)/ @(d:32,Rn.W)/ @(d:32,ERn.L) @ERn+ @-ERn @+ERn @ERn-
52
6 7 8 9 10 11
a ch tuyt i Trc tip Thanh ghi PC tng i Thanh ghi PC tng i vi thanh ghi ch s Gin tip b nh Gin tip b nh m rng
@aa:8/@aa:16/@aa:24/@aa:32 #xx:3/#xx:4/#xx:8/#xx:16/#xx:32 @(d:8, PC)/@(d:16, PC) @(RnL.B,PC)/ @(Rn.W,PC)/ @(ERn.L,PC) @@aa:8 @@vec:7
2.8.1 Trc tip thanh ghi --- Rn Gi tr ca ton hng l ni dung ca mt thanh ghi m rng 8, 16, 32 bit m c ch ra trong bi trng vector trong t m lnh. T R0 n R7 v E0 n E7 c th s dng vi vai tr l thanh ghi 16-bit. ER0 n ER7 c th s dng vi vai tr l cc thanh ghi 32-bit. 2.8.2 Gin tip thanh ghi ---@ERn Gi tr ton hng l ni dung ca v tr b nh m c ch n bi ni dung ca mt thanh ghi a ch (ERn). ERn c xc nh bi trng thanh ghi ca m lnh. Trong ch nng cao (advanced mode), nu ch nh a ch ny c s dng trong cu lnh r nhnh, th 24 bit thp l hp l v 8 bit cao c gi thit l 0 (H00). 2.8.3 Gin tip thanh ghi vi dch --- @(d:2, ERn), @(d:16, ERn), hay @(d:32, ERn) Gi tr ca ton hng l ni dung ca mt v tr b nh m c tr n bi tng ca ni dung ca mt thanh ghi a ch (ERn) v mt dch 16 hay 32 bit. ERn c xc nh bi trng thanh ghi trong m lnh. dch c bao gm trong m lnh v dch 16-bit l c m rng du khi cng vo ERn. Ch nh a ch ny c mt nh dng ngn (@(d:2, ERn)). nh dng ngn c th c s dng khi dch l 1, 2 hay 3 v ton hng l d liu byte, khi m dch l 2, 4, hay 6 v d liu word, hay khi dch l 4, 8, 12 v ton hng l d liu longword 2.8.4 Gin tip thanh ghi ch s vi dch @(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), hay @(d:32,ERn.L) Gi tr ton hng l ni dung ca mt v tr b nh m c ch n bi tng ca kt qu thao tc sau v mt dch 16 hay 32 bit: Cc bit c ch ra trong ni dung ca mt thanh ghi a ch (RnL, Rn, ERn) c ch ra bi trng thanh ghi trong m lnh, n s c m rng zero n 32-bit d liu v nhn vi 1, 2, 4. dch c
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cha trong m lnh v dch 16-bit c m rng du khi cng vo ERn. Nu ton hng l d liu byte, ERn c nhn 1. Nu ton hng l d liu word hay longword, ERn c nhn vi 2, hay 4. 2.8.5 Gin tip thanh ghi vi mt s tng sau, gim trc, tng trc v gim sau---@ERn+, @-ERn, @+ERn, hay @ERnGin tip thanh ghi vi mt s tng sau ---@ERn+ Gi tr ca ton hng l ni dung ca mt v tr b nh m c ch n bi ni dung ca mt thanh ghi a ch (ERn). Thanh ghi ERn c xc nh bi trng thanh ghi trong m lnh. Sau khi v tr b nh c truy xut th 1, 2 hay 4 c cng vo ni dung ca thanh ghi a ch v tng ny c lu vo thanh ghi a ch ny. Gi tr c cng vo l 1 nu truy xut byte, 2 nu truy xut word, v 4 nu truy xut longword. Gin tip thanh ghi vi mt s gim trc ---@-ERn Gi tr ca ton hng l ni dung ca mt v tr b nh m c ch n bi Kt qu ca thao tc: gi tr 1, 2 hay 4 c tr vo ni dung ca thanh ghi a ch (ERn). Thanh ghi ERn c xc nh bi trng thanh ghi trong m lnh. Sau , gi tr ton hng c lu vo thanh ghi a ch ny. Gi tr c tr vo l 1 nu truy xut byte, 2 nu truy xut word, v 4 nu truy xut longword. Gin tip thanh ghi vi mt s tng trc---@+ERn Gi tr ca ton hng l ni dung ca mt v tr b nh m c ch n bi Kt qu ca thao tc: gi tr 1, 2 hay 4 c cng vo ni dung ca thanh ghi a ch (ERn). Thanh ghi ERn c xc nh bi trng thanh ghi trong m lnh. Sau , gi tr ton hng c lu vo thanh ghi a ch ny. Gi tr c cng vo l 1 nu truy xut byte, 2 nu truy xut word, v 4 nu truy xut longword. Gin tip thanh ghi vi mt s gim sau ---@ERnGi tr ca ton hng l ni dung ca mt v tr b nh m c ch n bi ni dung ca mt thanh ghi a ch (ERn). Thanh ghi ERn c xc nh bi trng thanh ghi trong m lnh. Sau khi v tr b nh c truy xut th 1,2 hay 4 c tr vo ni dung ca thanh ghi a ch v tng ny c lu vo thanh ghi a ch ny. Gi tr c tr vo l 1 nu truy xut byte, 2 nu truy xut word, v 4 nu truy xut longword. Nu ni dung ca mt thanh ghi a dng m cng c s dng nh l mt thanh ghi a ch c ghi vo b nh s dng ch nh a ch ny, th d liu c ghi l ni dung ca thanh ghi sau khi tnh ton mt a ch hiu dng. Nu thanh ghi a dng nh nhau c ch nh trong mt cu lnh v hai a ch hiu ng c tnh, th ni dung ca thanh ghi a dng sau php tnh u tin ca mt a ch hiu dng l c s dng trong php tnh th hai ca mt a ch hiu dng khc. V d 1: MOV.W R0, @ER0+
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Gi tr thanh ghi ER0 trc khi thc thi l H12345678 Th sau khi thc hin cu lnh gi tr H567A s c ghi vo a ch H12345678 V cu lnh .W truy xut 1 word nn cng 2 vo thanh ghi ER0 chnh v vy m gi tr ca R0 l H567A v gi tr ny c ghi vo b nh H12345678 V d 2: MOV.B @ER0+, @ER0+ Ni dung ca thanh ghi ER0 trc khi thc thi l H0000 1000. Th ni dung nh H0000 1000 c c v sau gi tr thanh ghi ER0 s c tng ln 1 (do truy xut 1 byte - .B) l H0000 10001. V ni dung nh va c ny s c ghi vo ni dung ca nh H0000 10001 (c ch ti bi ER0). Sau khi thc hin cu lnh ny th ER0 tip tc tng ln 1. Do gi tr ca n s l H0000 1002. 2.8.6 a ch tuyt i ---@aa:8, @aa:16, @aa:24, hay @aa:32 Gi tr ton hng l ni dung ca mt v tr b nh m c ch n bi mt a ch tuyt i c bao gm trong m lnh. C 8-bit (@aa:8), 16-bit (@aa:16), 24-bit (@aa:24), and 32-bit (@aa:32) a ch tuyt i truy xut vng d liu, a ch tuyt i ca 8 bits (@aa:8), 16 bits (@aa:16), hay 32 bits (@aa:32) c s dng. Vi mt a ch tuyt i 8-bit, 24 bit cao c xc nh bi thanh ghi SBR. Vi a ch tuyt i 16-bit, th 16 bit ln l c m rng du (sign-extended). Mt a ch tuyt i 32-bit c th truy xut ton b khng gian a ch. truy xut vng chng trnh, a ch tuyt i 24 bits (@aa:24) hay 32 bits (@aa:32) c s dng. Vi mt a ch tuyt i 24-bit, tt c 8 bit cao c gi thit l 0 (H00) Bng 2.13 Vng truy xut ca a ch tuyt i
2.8.7 Trc tip --- #xx
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Gi tr ca ton hng l d liu 8-bit (#xx:8), 16-bit (#xx:16), hay 32-bit (#xx:32) c bao gm trong m lnh. Ch nh a ch ny c nh dng ngn m trong 3 hay 4-bit d liu trc tip c th c s dng. Khi kch thc ca d liu trc tip l nh hn gi tr ton hng ch (byte, word, hay longword) th d liu trc tip s c m rng zero (zero-extended). Cc cu lnh ADDS, SUBS, INC v DEC cha hon ton d liu trc tip. Mt vi cu lnh thao tc bit cha 3-bit d liu trc tip trong m lnh, ch s th t bit. Cu lnh BFLD v BFST cha d liu trc tip 8-bit trong m lnh, ch khi bit. Cu lnh TRAPA cha d liu trc tip 2-bit trong m lnh xc nh mt a ch vector 2.8.8 Thanh ghi PC tng i---@(d:8,PC) hay @(d:16,PC) Ch ny c s dng trong cu lnh Bcc v BSR. Gi tr ton hng l mt a ch r nhnh 32-bit, m l tng ca mt dch 8 hay 16-bit trong m lnh v a ch 32-bit ca ni dung thanh ghi PC. dch 8-bit hay 16-bit c m rng zero n 32-bit khi cng vi ni dung thanh ghi PC. Ni dung ca thanh ghi PC m trn dch c cng vo l a ch ca byte u tin ca cu lnh k tip, chnh v vy m gii hn ca r nhnh l t -126 n +128 byte (-63 n +64 word) hay -32766 n 32768 byte (-16383 n 16384 word) tnh t cu lnh r nhnh. Gi tr kt qu phi l mt s chn. Trong ch nng cao (advanced mode), ch c 24 bit thp ca a ch r nhnh ny l hp l; cn 8 bit cao c gi thit l 0 (H00) 2.8.9 PC tng i vi thanh ghi nh ch s---@(RnL, B, PC), @(Rn, W, PC), hay @(ERn, L, PC). Ch ny c s dng trong cc cu lnh Bcc v BSR. Gi tr ca ton hng l mt a ch r nhnh 32-bit, a ch m l tng ca kt qu sau v a ch 32-bit ca ni dung thanh ghi PC: ni dung ca mt thanh ghi a ch c xc nh bi trng thanh ghi cha trong m lnh (RnL, Rn, hay ERn) s c m rng zero v nhn vi 2. Ni dung ca PC m trn dch c cng vo l a ca byte u tin ca cu lnh k tip. Trong ch nng cao (advanced mode) ch c 24 bit thp ca a ch r nhnh l hp l, 8 bit cao cn li c gi thit l 0 (H00). 2.8.10 Gin tip b nh---@@aa:8 Ch ny c th c s dng bi cc lnh JMP v JSR. Gi tr ton hng l mt a ch r nhnh, a ch m l ni dung ca mt v tr b nh c ch ti bi mt a ch 8 bit tuyt i trong m lnh. Cc bit cao ca mt a ch tuyt i 8-bit l c gi thit l 0, v vy m khng gian a ch c gii hn t 0 n 255 (H0000 n HFFFF trong ch bnh thng (Normal mode), v t H00 0000 n H00 00FF trong cc ch khc)
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Trong ch bnh thng, v tr b nh c ch ti bi d liu c kch thc 1 word v a ch r nhnh l di 16 bit. Trong cc ch khc, v tr b nh c ch ti bi d liu c kch thc 1 longword. Trong ch trung bnh hay ch nng cao, byte u tin ca d liu 1 longword c gi thit l 0 (H00). Ch rng phn cao nht ca gii hn a ch cng c s dng nh l mt vng x l ngoi l. Mt a ch vector ca mt x l ngoi l ngoi tr reset hay mt sai st v a ch ca CPU v c th c thay th bi VBR. Hnh 2.15 s trnh by mt v d ca mt a ch r nhnh s dng ch nh a ch ny
Hnh 2.15 c t a ch r nhnh trong b nh 2.8.11 Gin tip b nh m rng---@@vec:7 Ch ny c th s dng bi cc cu lnh JMP v JSR. Gi tr ca ton hng l mt a ch r nhnh, m l ni dung ca mt v tr b nh c ch n bi kt qu thao tc sau: tng ca 7-bit d liu trong m lnh v gi tr ca H80 c nhn bi 2 hay 4. Vng a ch lu tr mt a ch r nhnh l H0100 n H01FF trong ch bnh thng v H00 0200 n H00 03FF trong cc ch khc. Trong k hiu dch hp ng, mt a ch lu mt a ch r nhnh l c xc nh. Trong ch bnh thng, v tr b nh c tr n bi mt d liu kch thc word v a ch r nhnh c kch thc l 16 bit. Trong cc ch khc, v tr b nh c ch n bi d liu longword. Trong ch trung bnh hay nng cao, byte u tin ca d liu longword c gi thit l 0 (H00). 2.8.12 Tnh ton a ch hiu dng: Bng 2.14 v 2.15 c t cch tnh a ch hiu dng trong mi ch nh a ch. Cc bit thp ca a ch hiu dng l hp l v cc bit cao cn li th b b qua (m rng zero hay m rng du) ty thuc vo ch hot ng ca CPU. Cc bit hp l trong ch trung bnh (middle mode) l nh sau: 16 bit thp ca a ch hiu dng l hp l v 16 bit cao th c m rng du cho cc cu lnh chuyn d liu v cc php tnh. 24 bit thp ca a ch hiu dng l hp l v 8 bit cao cn li th c m rng
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zero cho cc cu lnh r nhnh Bng 2.14 Tnh ton a ch hiu dng cho cc cu lnh chuyn d liu v cc php tnh
Bng 2.15 Tnh ton a ch hiu dng cho cc cu lnh r nhnh
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2.8.13 Cu lnh MOVA Cu lnh MOVA lu tr a ch hiu dng trong mt thanh ghi a dng 1. u tin, d liu thu c bi ch nh a ch c ch ra trong phn th 2 trong bng 2.14 2. K , a ch hiu dng c tnh bng cch s dng d liu thu c nh l mt ch s bng ch nh a ch c trnh by trong mc 5 ca bng 2.14. D liu thu c c s dng thay cho thanh ghi a dng. Kt qu c lu tr tr li vo thanh ghi a dng. Chi tit, tham kho H8SX Family Software Manual. Cc trng thi x l CPU H8SX c 5 trng thi x l chnh l: trng thi khi ng li, trng thi x l ngoi l, trng thi thc thi chng trnh, trng thi ngt bus (bus-released), v trng thi dng chng trnh. Hnh 2.16 s cho bit s chuyn i gia cc trng thi. Trng thi khi ng li
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Trong trng thi ny CPU v cc khi ngoi vi c khi chy v dng. Khi mt tn hiu thp p vo chn RES, th tt c cc qu trnh x l hin ti s dng v CPU vo ch khi ng li. X l ngoi l khi ng li bt u khi chn tn hiu t chn RES chuyn t thp ln cao. Trng thi khi ng li cng c th c tin hnh bi mt s trn b m gim st (watchdog timer). Chi tit, tham kho phn 4 trong Exception Handling. Trng thi x l ngoi l Trng thi x l ngoi l l mt s thay i trng thi xy ra khi m CPU chuyn t vic thc thi chng trnh hin ti sang thc thi chng trnh x l ngoi l, v d mt cu lnh khi ng li, cu lnh d theo, cu lnh ngt qung hay mt cu lnh trap. CPU c mt a ch bt u (vector) t bng vector x l ngoi l v r nhnh n a ch ny. Chi tit tham kho phn 4 Exception Handling Trng thi thc thi chng trnh Trong trng thi ny CPU thc thi chng trnh theo th t. Trng thi gii phng bus (bus-released) Trong trng thi ny, bus s c gii phng p ng yu cu t b iu khin DMA (DMAC) v b iu khin chuyn d liu (DTC). Trong khi bus c gii phng, th CPU ngng hot ng. Trng thi dng hot ng l trng thi ngt in khi m CPU dng hot ng. Trng thi dng hot ng xy ra khi m mt cu lnh SLEEP c thc thi hay CPU vo trng thi d phng (standby mode). Chi tit tham kho phn 19 Power-Down Modes.
Hnh 2.16 S chuyn i trng thi
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Chng 3 Cc ch hot ng ca MCU

3.1 Chn la ch hot ng
Vi iu khin ny c 3 ch hot ng (t ch 1 n ch 3). Ch hot ng c chn la bng cch thit lp cc chn ch (MD1 v MD0). Bng 3.1 lit k s thit lp cc ch hot ng ca MCU. Trong Vi iu khin ny, ch hot ng nng cao (advanced mode) cho ch hot ng ca CPU vi khng gian a ch 16Mbyte. Ch khi u ca vi iu khin c th c la chn t ch khi ng v ch khi ng ngi dng lp trnh hay xa b nh truy xut nhanh (flash memory) v ch khi u n chip. Bng 3.1 Thit lp ch hot ng MCU
Ch MD1 MD0 hot ng MCU 1 2 3 0 1 1 1 0 1 Ch hot ng MCU Nng cao Khng gian a ch 16 Mbytes M t ROM trn chip Cho php Cho php Cho php
Ch khi ng user Ch khi ng Ch bt u chip n
Trong ch 1 v 2, ch khi ng ngi dng (user boot mode) v ch khi ng (boot mode), th b nh truy xut nhanh (flash memory) c th c lp trnh v xa. Chi tit v ch khi ng ngi dng v ch khi ng tham kho phn 17 ca Flash Memory Trong ch 3 ca vi iu khin thc hin ch n chip
3.2 c t Thanh ghi

Cc thanh ghi sau l lin quan n vic thit lp ch hot ng Thanh ghi iu khin ch (MDCR) Thanh ghi iu khin h thng (SYSCR) 3.2.1 Thanh ghi iu khin ch (MDCR) Thanh ghi MDCR xc nh ch hot ng hin ti. Khi MDCR c c, th cc trng thi ca tn hiu nhp trn chn MD1 v MD0 c cht. Cht ny c gii phng bi reset
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Tn bit --------MDS3 MDS2 MDS1 MDS0 ----------------0 1 0 1
Gi tr khi to
R/W R R R R R R R R R R R R R R R R Khng dng Khng dng
c t
Cc bit ny l cc bit ch c v khng th hiu chnh
Khng xc nh * Khng xc nh * Khng xc nh * Khng xc nh * 0 1 0 1 Khng xc nh * Khng xc nh * Khng xc nh * Khng xc nh
La chn ch 3 n 0 Nhng bit ny xc nh ch hot ng c la chn bi cc chn ch (MD1 v MD0) (xem bng 3.2)
Cc bt ny l cc bit ch c v khng th thay i gi tr
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Ch : * c quyt nh bi cc chn MD1 v MD0 Bng 3.2 Thit lp cc bit t MSD3 n MSD0
3.2.2 Thanh ghi iu khin h thng (SYSCR) SYSCR iu khin hot ng bo ha MAC, la chn ch rng bus cho vic c lnh v ch hot ng ca DTC, cho php hay cm RAM ni v cc thanh ghi iu khin b nh flash
Bit
Tn bit
Gi tr R/W ban u Tt c = 1 R Khng dng
c t
15, 14 ---
Chng l nhng bit ch c v khng th hiu chnh gi tr. R/W iu khin ch hot ng bo ha MAC La chn ch hot ng bo ha hoc l ch khng bo ha cho cu lnh MAC 0: cu lnh MAC l hot ng khng bo ha 1:cu lnh MAC l hot ng bo ha
13
MACS
12
---
Khng dng Bit ny l bit ch c v khng th hiu chnh n.
11
---
R/W
Khng dng Bit ny lun c c vi gi tr l 1. Gi tr ghi vo n phi lun lun l 0
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10
---
R/W
Khng dng Bit ny lun c c vi gi tr l 1. Gi tr c ghi vo phi lun l 1
---
R/W
Khng dng Bit ny lun c c vi gi tr l 1. Gi tr ghi vo n phi lun lun l 0
RAME
R/W
Bit cho php RAM Cho php hoc khng cho php RAM ni. Bit ny c khi to khi trng thi reset c c gii phng. Khng c ghi gi tr 0 trong sut qu trnh truy xut RAM ni 0: khng cho php RAM ni 1: cho php RAM ni.
FLSHE
R/W
Cho php thanh ghi iu khin b nh Flash iu khin truy xut n cc thanh ghi iu khin b nh flash. Thit lp bit ny ln 1 cho php c v ghi vo cc thanh ghi iu khin b nh flash. Xa bit ny xung 0 cm vic c ghi vo cc thanh ghi iu khin b nh flash. Lc , ni dung ca cc thanh ghi iu khin b nh s c gi li. Ga tr ghi nn l 0 khi vi iu khin khng phi l phin bn b nh flash. 0: khng cho php cc thanh ghi iu khin b nh flash 1: cho php cc thanh ghi iu khin b nh flash
6 ti 2
---
Tt c l
R/W
Khng dng Cc bit ny lun c c vi gi tr l 0. Gi tr ghi vo phi lun l 0
DTCM D
R/W
La chn ch DTC La chn ch hot ng DTC 0: DTC l ch nh a ch y 1:DTC l ch nh a ch ngn
---
R/W
Khng dng Bit ny lun c c vi gi tr l 1. Gi tr ghi vo phi nn lun l 1.
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3.3 Cc c t ch hot ng 3.3.1 Ch 1 Ch 1 l ch khi ng ngi dng cho b nh flash. Cc thao tc l tng t vi ch 3 ngoi tr vic lp trnh hay xa b nh flash 3.3.2 Ch 2 Ch 2 l ch khi ng cho b nh flash. Cc thao tc l ging vi ch 3 ngoi tr vic lp trnh hay xa b nh flash 3.3.3 Ch 3 Ch 3 l ch nng cao (advanced mode) m trong khng gian a ch l 16 Mbyte, v ch n chip vi on-chip ROM c cho php
3.4 nh x a ch
3.4.1 nh x a ch
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Hnh 3.1 trnh by Bn a ch
66
Chng 4 X l ngoi l
4.1 Cc kiu x l ngoi l v u tin
Nh lit k trong bng 4.1, x l ngt qung c to ra bi vic reset, vic theo di, mt li sai a ch, mt ngt qung, mt cu lnh by, v cc cu lnh khng hp l (Lnh khng hp l general v Lnh khng hp l slot). X l ngt qung c xp u tin theo bng 4.1. Nu 2 hay nhiu hn 2 ngoi l xy ra cng lc, chng s ch c chp nhn v thc thi ty thuc u tin. Ngun ngoi l, cu trc stack, v tc v ca CPU thay i ty thuc vo ch iu khin ngt qung. Chi tit v ch iu khin ngt qung c cp ti trong chng 5, B iu khin ngt qung. Bng 4.1 Cc loi ngoi l v u tin u tin Kiu ngoi l Cao Reset nh thi x l ngoi l X l ngoi l c bt u khi c mt thay i mc t thp ln cao ti chn RES, hoc khi b nh thi b trn. CPU bt u trng thi reset khi chn RES xung mc in p thp.
Lnh khng hp l X l ngoi l bt u khi c mt dng lnh khng xc nh c thc thi. Theo di*1 Li a ch X l ngoi l bt u sau khi thc thi cu lnh hin ti, nu bit theo di (bit T) trong EXR c gi tr 1. Sau khi pht hin c li sai v a ch xut hin, x l ngoi l bt u lc hon thnh thc thi cu lnh hin ti. X l ngoi l bt u sau khi thc thi cu lnh hin ti hoc mt x l ngoi l khc, nu c mt yu cu ngt qung xy ra.*2 X l ngoi l bt u khi thc hin mt cu lnh by (TRAPA).
Ngt qung
Lnh by*3 Thp
Ch : 1. Ngoi l theo di ch c cho php trong ch iu khin ngt qung 2. X l ngoi l theo di khng c thc thi sau khi thc thi lnh RTE. 2. Ngt qung khng c pht hin trong khi hon tt thc thi cc lnh ANDC, ORC, XORC, LDC, hoc hon tt x l reset. 3. Yu cu x l ngoi l lnh by c chp nhn ti mi thi im trong khi thc thi chng trnh.
4.2 Ngun ngoi l v bng vector x l ngoi l

Cc a ch VTAO (vector table address offset a ch offset bng vector) khc nhau c gn cho cc ngun ngoi l khc nhau. a ch bng vector c tnh
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ton da trn ni dung thanh ghi VBR v a ch VTAO. a ch bt u ca chng trnh con phc v ngoi l c np vo t bng vector x l ngoi l (ch nh bi a ch bng vector). Bng 4.2 cho ta bit a ch VTAO ca cc ngun ngoi l. Bng 4.3 ch ra phng thc tnh cc a ch bng vector x l ngoi l. Bi v cc ch c s dng l khc nhau ty thuc vo tng dng sn phm, bit thm chi tit v cc ch sn sng, xin xem li phn 3. Bng 4.2 Bng vector x l ngoi l
a ch offset bng vertor *1 Ch nng cao, Ch bnh trung bnh v ti a thng*2 H'0080 ti H0081 H'0082 ti H0083 H'0084 ti H0085 H'0086 ti H0087 H'0088 ti H0089 H'0100 ti H0103 H'0104 ti H0107 H'0108 ti H010B H'010C ti H010F H'0110 ti H0113
Ngun ngoi l Ngt qung ngoi IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11
S vector 64 65 66 67 68 69 70 71 72 73 74 75
H'008A ti H008B H'0114 ti H0117 H'008C ti H008D H'0118 ti H011 B H'008E ti H008F H'011 C ti H011 F H'0090 ti H0091 H'0092 ti H0093 H'0094 ti H0095 H'0096 ti H0097 H'0120 ti H0123 H'0124 ti H0127 H'0128 ti H012B H'012C ti H012F
IRQ12 76 IRQ13 77 IRQ14 78 IRQ15 79 Phn dnh cho h thng 80 Ngt qung trong*4 81 | 255 Reset Phn dnh cho h thng 0 1 2 Lnh khng hp l Theo di Phn dnh cho h thng Ngt qung (NMI) Lnh by(#0) 3 4 5 6 7 8
H'0098 ti H0099 H'0130 ti H0133 H'009A ti H009B H'0134 ti H0137 H'009C ti H009D H'0138 ti H013B H'009E ti H009F H'013C ti H013F H'00A0 ti H00A1 H'0140 ti H0143 H'00A2 ti H00A3 H'0144 ti H0147 | | H'01 FE ti H01 FF H'03FC ti H03FF H'0000 ti H0001 H'0002 ti H0003 H'0004 ti H0005 H'0006 ti H0007 H'0008 ti H0009 H'0000 ti H0003 H'0004 ti H0007 H'0008 ti H000B H'000C ti H000F H'0010 ti H0013
H'000A ti H000B H'0014 ti H0017 H'000C ti H000D H'0018 ti H001B H'000E ti H000F H'0010 ti H0011 H'001C ti H001F H'0020 ti H0023
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(#1) (#2) (#3) Sai a ch CPU Sai a ch DMA*

3
9 10 11 12 13 14 ! 63
H'0012 ti H0013 H'0014 ti H0015 H'0016 ti H0017 H'0018 ti H0019
H'0024 ti H0027 H'0028 ti H002B H'002C ti H002F H'0030 ti H0033
H'001A ti H001 B H'0034 ti H0037 H'001C ti H001D H'0038 ti H003B ! ! H'007E ti H007F H'00FC ti H00FF
Phn dnh cho h thng
Ch :
1. 2. 3. 4.
16 bit thp ca a ch Khng c trong Vi iu khin ny. Sai a ch DMA c to ra gia DTC v DMAC. Mun bit thm chi tit v bng vector, xem Chng 5.5
Bng 4.3 Phng php tnh ca a ch bng vector x l ngoi l Ngun ngoi l Reset, Sai a ch CPU Nhng ci khc Ghi ch VBR: Vector base register a ch offset bng vector: Xem Bng 4.2. Phng php tnh ton vi a ch bng vector a ch bng vector = (a ch offset bng vector) a ch bng vector = VBR + (a ch offset bng vector)
4.3
Reset
Mt reset c u tin cao hn bt k mt ngoi l no khc. Khi chn RES xung mc thp, tt c cc chng trnh u dng li v Vi iu khin ny chuyn vo trng thi reset. chc chn rng Vi iu khin ny c reset, gi cho chn RES mc thp ti thiu 20ms khi ngun in c bt. Khi tc v reset ang c din ra, gi chn RES mc thp ti thiu 20 chu k sau . Mt chip c th c reset bi vic trn b nh thi gim st. bit thm chi tit, xin xem phn 12, WDT. Mt reset khi ng trng thi bt u ca CPU v thanh ghi ca cc b phn ngoi vi ni. Ch iu khin ngt qung c quay v 0 sau khi reset. 4.3.1 X l ngoi l reset
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Khi chn RES ln mc cao sau khi c gi mc thp trong mt khong thi gian cn thit, Vi iu khin ny bt u x l reset theo cc bc sau: 1. Trng thi bt u ca CPU v thanh ghi ca cc b phn ngoi vi ni c khi ng, VBR c xa, bit T trong thanh ghi EXR c xa, bit I trong EXR v CCR c gn ln 1. 2. a ch vector x l ngoi l reset c c v chuyn vo thanh ghi PC, sau chng trnh s thc thi bt u t a ch c ch nh trong thanh ghi PC. Hnh 4.1 cho ta thy mt v d v reset. 4.3.2 Ngt qung sau khi reset Nu mt ngt qung c cho php sau khi reset nhng trc khi con tr chng (SP) c khi tr, th thanh ghi PC v CCR s khng c lu li ng cch, dn n chng trnh s b hng. ngn nga iu ny, tt c cc yu cu ngt qung, k c NMI, u b cm ngay sau khi reset. Bi v cu lnh u tin ca chng trnh lun thc thi ngay sau khi reset kt thc, hy chc chn rng cu lnh ny s khi tr cho SP (v d: MOV.L #xx: 32, SP). 4.3.3 Chc nng ca cc thit b ngoi vi ni sau khi reset kt thc Sau khi trng thi reset c kt thc, MSTPCRA, MSTPCRB, v MSTPCRC c khi tr l H0FFF, HFFFF, v HFF00 theo th t, v tt c cc module (tr DMAC v DTC) u c a vo ch dng. Kt qu l, cc thanh ghi ca cc module ngoi vi ni khng th c c hay ghi. Vic c/ghi thanh ghi s c cho php li khi ch dng ny c hy
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Hnh 4.1 Chui hnh ng khi reset (On-Chip ROM Cho php Advanced Mode)
4.4
Theo di
Theo di c cho php ch iu khin ngt qung 2, v khng c kch hot ch iu khin ngt qung 0, bt k trng thi ca bit T. Trc khi chuyn ch iu khin ngt qung, bit T phi c xa v 0. bit thm chi tit v cc ch iu khin ngt qung, xem thm chng 5, B iu khin ngt qung. Nu bit T trong thanh ghi EXR c gn ln 1, ch theo di c kch hot. Trong ch theo di, mt ngoi l theo di xy ra ti cui mi lnh. Ch theo di khng b nh hng bi mt n ngt qung trong CCR. Bng 4.4 cho ta thy trng thi ca CCR v EXR sau khi thc thi chng trnh x l ngoi l theo di. Ch theo di c hy b bi vic xa bit T trong EXR trong qu trnh x l ngoi l theo di. Tuy nhin, bit T (c lu li trn stack) vn gi gi tr 1 ca n, v khi chng trnh con phc v ngoi l theo di gi lnh RTE quay v, ch theo di s c phc hi. X l ngoi l theo di s khng c thc hin sau khi thc thi lnh RTE. Ngt qung vn c cho php cho d ang trong chng trnh con x l ngoi l theo di. Bng 4.4 Trng thi ca CCR v EXR sau khi x l ngoi l theo di
I I2 to I0 X l ngoi l theo di khng c cho php. 1 ------CC R UI EX R T 0
Ch iu khin ngt qung 0 2
Ghi ch: 1: 0: Gn ln 1 Xa v 0
----: Gi nguyn gi tr trc.
4.5
Sai a ch
4.5.1 Nguyn nhn sai a ch Vic np lnh, cc tc v stack, vic c/ghi d liu, v vic chuyn a ch n (xem bng 4.5) u c th gy ra li sai a ch. Bng 4.5 Chu k bus v sai a ch
Chu k bus Kiu Np lnh S dng bus CPU M t Np lnh t a ch chn Sai a ch Khng (bnh thng)
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Np lnh t a ch l Np lnh t vng khc khng gian module ngoi vi ni*1 Np lnh t vng khng gian module ngoi vi ni*1 Np lnh t khng gian b nh ngoi trong ch chip n Np lnh t khu vc cm truy cp*2 Tc v stack CPU Truy cp stack khi ni dung con tr chng l a ch chn Truy cp stack khi ni dung con tr chng l a ch l c/ghi d liu CPU Truy cp d liu t a ch chn Truy cp d liu t a ch l Truy cp t khng gian b nh ngoi trong ch chip n Truy cp vo vng cm c/ghi d liu DTC/DMAC Truy cp d liu t a ch chn Truy cp d liu t a ch l Truy cp t khng gian b nh ngoi trong ch chip n Truy cp vo vng cm Chuyn a ch n DMAC Trong ch chuyn a ch n, thit b c truy cp nm vng khng gian b nh ngoi Trong ch chuyn a ch n, thit b c truy cp khng nm trong vng khng
Xy ra Khng (bnh thng) Xy ra Xy ra Xy ra Khng (bnh thng) Xy ra Khng (bnh thng) Khng (bnh thng) Xy ra Xy ra Khng (bnh thng) Khng (bnh thng) Xy ra Xy ra Khng (bnh thng)
Xy ra
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gian b nh ngoi
Ch : 1. V khng gian ngoi vi ni, xem thm phn 6, b iu khin bus. 2. V vng cm truy cp, xem li hnh 3.1 phn 3.4. 4.5.2 X l li sai a ch Khi c mt li sai a ch xy ra, qu trnh x l li sai a ch s bt u sau khi chu k bus gy ra li sai kt thc v cu lnh hin ti c hon tt. Qu trnh x l li sai a ch s c thc hin theo nhng bc sau: 1. Lu li gi tr cc thanh ghi PC, CCR v EXR vo stack. 2. Cp nht bit mt n ngt qung v xa bit T. 3. a ch bng vector x l ngoi l tng ng vi li sai a ch s c pht ra, a ch bt u ca chng trnh con phc v ngoi l s c ti t bng vector vo thanh ghi PC, v chng trnh thc thi bt u t a ch . Mc d c mt li sai a ch xy ra trong qu trnh chuyn ti x l ngoi l, li sai ny s c b qua. Vic ny ngn nga vic chng v tn cc li sai a ch. Nu ni dung con tr SP khng phi l s chn khi c mt qu trnh x l li sai a ch xy ra, gi tr ca stack (cc thanh ghi PC, CCR, v EXR) s khng xc nh. Khi c mt li sai a ch xy ra, nhng tc v sau s c thc hin dng DTC v DMAC. Bit EER trong DICCR ca DTC c gn ln 1. Bit ERRF trong DMDR_0 ca DMAC c gn ln 1. DTE trong tt c cc knh ca DMAC c xa v 0 v DMAC b bt buc phi dng. Bng 4.6 Trng thi ca CCR v EXR sau khi x l li sai a ch
Ch iu khin ngt qung 0 2 CCR I 1 1 UI T 0 EXR I2 ti I0 1
Ghi ch: 1: 0: -: Gn ln 1. Xa xung 0. Gi nguyn gi tr c
4.6
Ngt qung
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4.6.1 Ngun ngt qung Cc ngun ngt qung l NMI, IRQ0 ti IRQ15, v cc module ngoi vi ni, xem Bng 4.7. Bng 4.7 Cc ngun ngt qung
Ngun Chn NMI (ng nhp bn ngoi) Chn IRQ0 ti IRQ15 (ng nhp bn ngoi) ng h gim st (WDT) B chuyn analog/digital n v xung nh thi 16-bit (TPU) B iu khin DMA (DMAC) Giao tip ni tip (SCI) Giao tip ni tip ng b (SSU) S ca ngun 1 15 1 2 52 8 8 9 Kiu NMI IRQ0 ti IRQ14 ngoi Module vi ni
Cc s vector v a ch offset bng vector khc nhau s c gn cho cc ngun ngt qung khc nhau (Xem bng 5.2 Chng 5). 4.6.2 X l ngt qung Ngt qung c iu khin bi b iu khin ngt qung. B iu khin ngt qung c hai ch iu khin ngt qung v c th gn cc ngt qung (khc NMI) cho 8 u tin (cp mt n) cho php iu khin a ngt qung. Ngun bt u qu trnh x l ngt qung v a ch vector khc nhau ty theo tng sn phm. Chi tit hn c th xem chng 5. Qu trnh x l ngt qung gm cc bc: 1. Ni dung cc thanh ghi PC, CCR v EXR c lu trong stack. 2. mt n ngt qung c cp nht v bit T c xa. a ch bng vector x l ngt qung tng ng vi ngun ngt qung c to ra, a ch bt u ca chng trnh con phc v ngt qung c ti v t bng vector v lu vo thanh ghi PC, v chng trnh bt u thc thi ti a ch .
4.7
X l ngoi l cu lnh
C 2 loi cu lnh gy ra x l ngoi l: lnh by v lnh khng hp l. 4.7.1 Lnh by Qu trnh x l lnh by bt u khi cu lnh TRAPA c thc thi. X l lnh by c th c thc thi tt c mi lc trong trng thi thc thi chng trnh. Qu trnh x l lnh by c thc hin theo cc bc sau: 1. Lu li ni dung ca PC, CCR v EXR vo stack. 2. Bit mt n ngt qung c cp nht v bit T c xa.
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3. a ch bng vector x l ngoi l tng ng vi s vector ca lnh TRAPA c pht ra, a ch bt u ca chng trnh con phc v ngoi l c ti v t bng vector v lu vo PC, chng trnh thc thi s bt u t a ch . a ch bt u c c trong bng vector tng ng vi s vector t 0 n 3, nh ch nh trong m cu lnh. Bng 4.8 Trng thi ca CCR v EXR sau khi thc thi chng trnh x l lnh by
Ch iu khin ngt qung 0 2 CCR I 1 1 UI T 0 EXR I2 ti I0 -
Ghi ch: 1: 0: -: Gn ln 1. Xa xung 0. Gi nguyn gi tr c.
4.7.2 Lnh khng hp l C hai loi lnh khng hp l: Lnh khng hp l general v lnh khng hp l slot. X l ngoi l ca trng hp Lnh khng hp l general bt u khi c mt cu lnh khng xc nh c gii m. X l ngoi l ca trng hp Lnh khng hp l slot bt u khi nhng cu lnh sau c t trong 1 slot (ngay sau mt cu lnh nhy): mt lnh gm 2 hoc nhiu hn 2 t hoc lnh thay i ni dung ca PC. Cc cu lnh khng hp l general v slot lun lun c th c thc thi trong khi chy chng trnh. Qu trnh x l ngoi l cho cc cu lnh khng hp l general v slot gm cc bc sau: 1. Lu ni dung cc thanh ghi PC, CCR v EXR vo stack. 2. Bit mt n ngt qung s c cp nht v bit T c xa xung 0. 3. Mt a ch bng vector x l ngoi l tng ng s c pht sinh, a ch bt u ca chng trnh phc v ngoi l s c ti t bng vector vo thanh ghi PC, v chng trnh thc thi s bt u t a ch . Bng 4.9 Trng thi ca CCR v EXR sau khi x l lnh khng hp l
Ch iu CCR EXR
75
khin ngt qung 0 2 1 1
UI -----
T --0
I2 to I0 -----
4.8
Trng thi stack sau khi x l ngoi l
Hnh 4.2 cho thy stack sau khi hon thnh vic x l ngoi l.
Hnh 4.2 Trng thi stack sau khi x l ngoi l
4.9
Ch khi s dng
Khi truy cp stack, Vi iu khin ny mc nh rng bit a ch thp nht l 0. Stack lun c truy cp ti bi cu lnh vi i s d liu l word hoc longword, v gi tr ca con tr chng (SP:ER7) lun lun l s chn. S dng cc cu lnh sau lu cc thanh ghi: PUSH.W Rn (hoc MOV.W Rn, @-SP) PUSH.L ERn (hoc MOV.L ERn, @-SP) S dng cc cu lnh sau phc hi cc thanh ghi: POP.W Rn (hoc MOV.W @SP+, Rn) POP.L ERn (hoc MOV.L @SP+, ERn) Cc tc ng ti stack khi con tr chng SP ang c gi tr l lun dn ti mt li sai a ch. Hnh 4.3 cho thy v d khi thc thi mt tc v trong lc SP ang c gi tr l.
76
Hnh 4.3 Tc v xy ra khi gi tr SP l s l
77
Chng 5 B iu khin ngt qung

5.1 Cc c tnh
Hai ch iu khin ngt qung Bt k ch no trong hai ch iu khin ngt qung ny u c th c chn bi cc bit INTM1 v INTM0 trong thanh ghi iu khin ngt qung (INTCR). u tin c th c n nh bi thanh ghi u tin ngt qung (IPR) IPR c cung cp thit lp cc u tin ngt qung. Mi ngt qung u c 8 cp u tin thit lp, tr nhng ngt qung c lit k bn di. 6 ngt qung di y c gn u tin = 8, tc n c chp nhn tt c mi lc. NMI Lnh khng hp l general Theo di Lnh by Sai a ch CPU Sai a ch DMA* a ch vector c lp Tt c cc ngun ngt qung u c n nh bi mt a ch vector c lp, iu ny gip chng ta khng cn tm chng trnh con phc v ngt qung tng ng vi ngun. 17 ngt qung ngoi NMI l ngt qung c u tin cao nht, v n c chp nhn trong mi lc. C th xc nh NMI bng cnh ln hoc cnh xung . IRQ0 ti IRQ15 c th c xc nh bi mt cnh ln, mt cnh xung, mc cao, mc thp, hoc c s thay i mc. iu khin DTC v DMAC DTC v DMAC c th c kch hot bi ngt qung. Chc nng iu khin u tin CPU Cc cp u tin c th c n nh cho CPU, DTC v DMAC. u tin ca CPU c th c n nh t ng bng cch pht sinh mt ngoi l. Hot ng x l ngoi l CPU c th c u tin cao hn vic truyn d liu ca DTC v DMAC. Ghi ch: * Mt li sai a ch DMA ch ny sinh trong qu trnh s dng DTC v DMAC. S khi ca b x l ngt qung c m t Hnh 5.1
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Hnh 5.1 S khi ca b x l ngt qung
5.2 Cc chn xut/nhp

Bng 5.1
Tn NMI
Cu hnh chn
Xut/nhp Chc nng Nhp Nonmaskable External Interrupt (Ngt qung khng th che) C th xc nh bi cnh ln, cnh xung. Maskable External Interrupts (Ngt qung c th che) C th dng cnh ln, cnh xung, thay i mc, hoc mc cao,mc thp xc nh.
IRQ15 Nhp ti IRQ0
5.3
Cc m t thanh ghi
B iu khin ngt qung c cc thanh ghi sau. Thanh ghi iu khin ngt qung (INTCR) Thanh ghi iu khin u tin CPU (CPUPCR) Thanh ghi u tin ngt qung A ti G, I, K ti O, Q, v R (IPRA ti IPRG, IPRI, IPRK ti IPRO, IPRQ, v IPRR)
79
Thanh ghi cho php IRQ (IER) Cc thanh ghi iu khin cm bin IRQ H v L (ISCRH, ISCRL) Thanh ghi trng thi IRQ (ISR) Software standby release IRQ enable register (SSIER) 5.3.1 Thanh ghi iu khin ngt qung (INTCR) INTCR chn ch iu khin ngt qung, v cnh tch cc cho NMI.
Bit 7,6
Tn bit -
Gi tr khi u 0
R/W R Khng dng.
M t
y l nhng bit ch c v khng th chnh sa 5 4 INTM1 INTM0 0 0 R/W R/W Ch chn iu khin ngt qung 1 v 0 Nhng bit ny s chn ch iu khin ngt qung cho b iu khin ngt qung. 00: Ch iu khin ngt qung 0 Ngt qung c iu khin bi bit I trong CCR. 01: Cm thit lp. 10: Ch iu khin ngt qung 2. Ngt qung c iu khin bi cc bit I2 ti I0 trong EXR v IPR. 11: Cm thit lp. 3 NMIEG 0 R/W Ch chn cnh cho NMI Chn ch cnh nhp vo cho chn NMI. 0: Yu cu ngt qung s c pht ra khi c cnh xung chn NMI. 1: Yu cu ngt qung s c pht ra khi c cnh ln chn NMI. 2 ti 0 0 R/W Khng dng. y l nhng bit ch c v khng th chnh sa
5.3.2 Thanh ghi iu khin u tin CPU (CPUPCR)

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CPUPCR s quyt nh u tin ca CPU c cao hn ca DTC v DMAC hay khng. u tin ca DTC c thit lp bi cc bit DTCP2 ti DTCP0 trong thanh ghi ny. u tin ca tng knh DMAC c thit lp bi thanh ghi iu khin DMAC.
Ch : * Khi bit IPSETE c gn ln 1, u tin ca CPU s t ng cp nht, v nhng bit ny s khng th chnh sa.
Bit Tn bit Gi tr khi u 0 R/W M t
CPUPC E
R/W
Cho php iu khin u tin CPU Gn bit ny ln 1 s lm cho CPU c quyn u tin cao hn DMAC. 0: CPU lun c u tin thp nht 1: cho php iu chnh u tin CPU
6 5 4
DTPC2 DTPC1 DTPC0
0 0 0
R/W R/W R/W
u tin DTC t cp 2 ti cp 0 000: Cp u tin 0 (Thp nht) 001: Cp u tin 1 010: Cp u tin 2 011: Cp u tin 3 100: Cp u tin 4 101: Cp u tin 5 110: Cp u tin 6 111: Cp u tin 7 (Cao nht)
IPSETE
R/W
Cho php thit lp u tin ngt qung iu khin chc nng t ng n nh u tin cho CPU. Gn bit ny bng 1 s t ng thit lp cc bit CPUP2 ti CPUP0 thnh bit mt n ngt qung (bit I trong CCR hoc bit I2 ti I0 trong EXR). 0: cc bit CPUP2 ti CPUP0 s khng c cp nht t ng 1: Gi tr cc bit mt n ngt qung s c lu vo cc bit CPUP2 ti CPUP0.
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2 1 0
CPUP2 CPUP1 CPUP0
0 0 0
R/(W) * R/(W) * R/(W) *
u tin CPU t cp 2 ti cp 0 Nhng bit ny s thit lp u tin CPU. Khi bit CPUPCE c gn ln 1, u tin ca CPU s c thit lp ty vo gi tr cc bit ny. 000: Cp u tin 0 (Thp nht) 001: Cp u tin 1 010: Cp u tin 2 011: Cp u tin 3 100: Cp u tin 4 101: Cp u tin 5 110: Cp u tin 6 111: Cp u tin 7 (Cao nht)
Ch : * Khi bit IPSETE c gn ln 1, u tin ca CPU s t ng cp nht, v nhng bit ny s khng th chnh sa.
5.3.3 Thanh ghi u tin ngt qung A ti G, I, K ti O, Q, v R (IPRA ti IPRG, IPRI, IPRK ti IPRO, IPRQ, v IPRR) IPR thit lp u tin (cc cp 7 ti 0) cho cc ngt qung khc NMI. Thit lp cc gi tr t 000 n 111 trong tng nhm 3 bit ca cc bit 1412, 108, 64, v 20 s n nh u tin cho cc ngt qung tng ng. bit c cc loi ngt qung tng ng vi cc bit no trong IPR, xem bng 5.2.
Bit 15 14 13 12
Tn bit # IPR14 IPR13 IPR12
Gi tr R/W M t khi u 0 R Khng dng y l bit ch c v khng th chnh sa. 1 R/W Thit lp u tin cho ngt qung tng ng. 1 R/W 1 R/W 000: Cp u tin 0 (thp nht) 001: Cp u tin 1 010: Cp u tin 2 011: Cp u tin 3 100: Cp u tin 4
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11 10 9 8
# IPR10 IPR9 IPR8
0 1 1 1
R R/W R/W R/W
101: Cp u tin 5 110: Cp u tin 6 111: Cp u tin 7 (cao nht) Khng dng y l bit ch c v khng th chnh sa. Thit lp u tin cho ngt qung tng ng. 000: Cp u tin 0 (thp nht) 001: Cp u tin 1 010: Cp u tin 2 011: Cp u tin 3 100: Cp u tin 4 101: Cp u tin 5 110: Cp u tin 6 111: Cp u tin 7 (cao nht) Khng dng Thit lp u tin cho ngt qung tng ng. 000: Cp u tin 0 (thp nht) 001: Cp u tin 1 010: Cp u tin 2 011: Cp u tin 3 100: Cp u tin 4 101: Cp u tin 5 110: Cp u tin 6 111: Cp u tin 7 (cao nht) Khng dng y l bit ch c v khng th chnh sa. Thit lp u tin cho ngt qung tng ng. 000: Cp u tin 0 (thp nht) 001: Cp u tin 1 010: Cp u tin 2 011: Cp u tin 3 100: Cp u tin 4 101: Cp u tin 5 110: Cp u tin 6 111: Cp u tin 7 (cao nht) y l bit ch c v khng th chnh sa.
7 6 5 4
# IPR6 IPR5 IPR4
0 1 1 1
R R/W R/W R/W
3 2 1 0
# IPR2 IPR1 IPR0
0 1 1 1
R R/W R/W R/W
5.3.4 Thanh ghi cho php IRQ (IER) IER cho php hoc cm cc yu cu ngt qung IRQ15 ti IRQ0.
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Tn Gi tr R/W M t bit khi u IRQ15E 0 R/W Cho php IRQ15 Yu cu ngt qung IRQ15 c cho php khi bit ny bng 1. IRQ14E 0 IRQ13E 0 IRQ12E 0 IRQ11E 0 IRQ10E 0 IRQ9E 0 IRQ8E 0 IRQ7E 0 IRQ6E 0 IRQ5E 0 IRQ4E 0 IRQ3E 0 IRQ2E 0 IRQ1E 0 IRQ0E 0 R/W Cho php IRQ14 Yu cu ngt qung IRQ14 c cho php khi bit ny bng 1. R/W Cho php IRQ13 Yu cu ngt qung IRQ13 c cho php khi bit ny bng 1. R/W Cho php IRQ12 Yu cu ngt qung IRQ12 c cho php khi bit ny bng 1. R/W Cho php IRQ11 Yu cu ngt qung IRQ11 c cho php khi bit ny bng 1. R/W Cho php IRQ10 Yu cu ngt qung IRQ10 c cho php khi bit ny bng 1. R/W Cho php IRQ9 Yu cu ngt qung IRQ9 c cho php khi bit ny bng 1. R/W Cho php IRQ8 Yu cu ngt qung IRQ8 c cho php khi bit ny bng 1. R/W Cho php IRQ7 Yu cu ngt qung IRQ7 c cho php khi bit ny bng 1. R/W Cho php IRQ6 Yu cu ngt qung IRQ6 c cho php khi bit ny bng 1. R/W Cho php IRQ5 Yu cu ngt qung IRQ5 c cho php khi bit ny bng 1. R/W Cho php IRQ4 Yu cu ngt qung IRQ4 c cho php khi bit ny bng 1. R/W Cho php IRQ3 Yu cu ngt qung IRQ3 c cho php khi bit ny bng 1. R/W Cho php IRQ2 Yu cu ngt qung IRQ2 c cho php khi bit ny bng 1. R/W Cho php IRQ1 Yu cu ngt qung IRQ1 c cho php khi bit ny bng 1. R/W Cho php IRQ0 Yu cu ngt qung IRQ0 c cho php khi bit ny bng 1.
5.3.5 Cc thanh ghi iu khin cm bin IRQ H v L (ISCRH v ISCRL) ISCRH v ISCRL chn kiu to ra yu cu ngt qung trn cc chn IRQ15 ti IRQ0.
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Bng vic thay i thanh ghi ISCR, IRQnF (n = 15 ti 0) trong thanh ghi ISR thng tnh c c gn bng 1 thng qua mt tc v ni. Trong trng hp ny, mt qu trnh x l ngt qung s c thc thi nu c mt yu cu ngt qung IRQn c cho php. ngn chn mt ngt qung khng theo mun xy ra, thanh ghi ISCR cn phi c thay i khi ngt qung IRQn b cm, v IRQnF trong ISR u b xa thnh 0. ISCRH
ISCRL
ISCRH
Bit Tn bit Gi tr khi u 0 0 R/W M t
15 14
IRQ15S R IRQ15S F
R/W R/W
00: YCNQ to ra bi mc thp ca chn IRQ15 01: YCNQ to ra bi cnh xung ca chn IRQ15 10: YCNQ to ra bi cnh ln ca chn IRQ15 11: YCNQ to ra bi c hai cnh ln v xung ca IRQ15
13 12
IRQ14S R IRQ14S F
0 0
R/W R/W
85
11 10
IRQ13S R IRQ13S F
0 0
R/W R/W
9 8
IRQ12S R IRQ12S F
0 0
R/W R/W
7 6
IRQ11S R IRQ11S F
0 0
R/W R/W
5 4
IRQ10S R IRQ10S F
0 0
R/W R/W
3 2
IRQ9SR IRQ9SF
0 0
R/W R/W
1 0
IRQ8SR IRQ8SF
0 0
R/W R/W
ISCRL
86
Bit
Tn bit
Gi tr khi u 0 0
R/W
M t
15 14
IRQ7S R IRQ7S F
R/W R/W
13 12
IRQ6S R IRQ6S F
0 0
R/W R/W
11 10
IRQ5S R IRQ5S F
0 0
R/W R/W
9 8
IRQ4S R IRQ4S F
0 0
R/W R/W
7 6
IRQ3S R IRQ3S F
0 0
R/W R/W
5 4
IRQ2S R IRQ2S F
0 0
R/W R/W
IRQ1S
R/W
00: YCNQ to ra bi mc thp ca chn IRQ1
87
R IRQ1S F
R/W
01: YCNQ to ra bi cnh xung ca chn IRQ1 10: YCNQ to ra bi cnh ln ca chn IRQ1 11: YCNQ to ra bi c hai cnh ln v xung ca IRQ1
1 0
IRQ0S R IRQ0S F
0 0
R/W R/W
00: YCNQ to ra bi mc thp ca chn IRQ0 01: YCNQ to ra bi cnh xung ca chn IRQ0 10: YCNQ to ra bi cnh ln ca chn IRQ0 11: YCNQ to ra bi c hai cnh ln v xung ca IR0
Ghi ch: YCNQ = Yu cu ngt qung. 5.3.6 Thanh ghi trng thi IRQ (ISR) ISR l mt thanh ghi trng thi cho cc ngt qung t IRQ15 n IRQ0.
Ch : * Ch c th ghi 0 xa c. Cc cu lnh x l bit hoc tc v b nh nn c dng xa c.

Bit Tn bit Gi tr khi u 0 0 0 0 0 0 0 0 0 0 R/W M t
15 14 13 12 11 10 9 8 7 6
IRQ15 F IRQ14 F IRQ13 F IRQ12 F IRQ11 F IRQ10 F
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
[iu kin lp] Khi c mt ngt qung c chn bi ISCR [iu kin xa] Ghi 0 sau khi c IRQnF = 1. Khi chn ch pht sinh yu cu ngt qung mc thp v chn IRQn mc cao. Khi chn ch pht sinh yu cu ngt qung cnh ln, cnh xung hoc c hai. Khi DTC c kch hot bi mt ngt qung IRQn, v bit DISEL trong MRB 88
5 4 3 2 1 0
IRQ9F IRQ8F IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W
ca DTC c xa xung 0.
5.3.7 Thanh ghi cho php IRQ tt ch stanby ca CPU(SSIER) SSIER s chn cc chn ch standby phn mm s dng trong cc chn IRQ15 ti IRQ0. Ngt qung IRQ c dng trong ch standby phn mm khng nn c thit lp lm ngun kch hot DTC.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Tn bit SSI15 SSI14 SSI13 SSI12 SSI11 SSI10 SSI9 SSI8 SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1
Gi tr R/W khi u 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W
M t Thit lp IRQ m ch standby phn mm s pht sinh Cc bit ny s chn chn IRQn ch standby phn mm s dng (n=15 ti 0). 0: Yu cu IRQn khng phi l ca ch standby phn mm 1: Khi mt yu cu IRQn xy ra trong ch standby phn mm, vi iu khin s thot ra khi ch standby sau khi thi gian thit lp dao ng kt thc.
89
SSI0
R/W
5.4
Ngun ngt qung
5.4.1 Cc ngt qung ngoi C 17 loi ngt qung ngoi:: NMI v IRQ15 ti IRQ0. Nhng ngt qung ny c th s dng cho ch ch phn mm. Ngt qung NMI: Yu cu ngt qung khng th che (NMI) l ngt qung c u tin cao nht, v lun c chp nhn bi CPU bt chp ch iu khin ngt qung hay nhng thit lp ca cc bit mt n ngt qung trong CPU. Bit NMIEG trong thanh ghi INTCR s la chn ch pht sinh yu cu ngt qung l theo cnh ln hay cnh xung chn NMI. Khi c mt yu cu ngt qung NMI c pht sinh, b iu khin ngt qung s xem rng c mt li sai xy ra, v thc hin cc bc sau: # Lp bit ERR trong DTCCR ca DTC ln 1. # Lp bit ERRF trong DMDR_0 ln 1. # Xa bit DTE ca tt c cc knh trong DMAC v lp tc dng vic truyn d liu. Ngt qung IRQn: Mt ngt qung IRQn c yu cu bi tn hiu nhp t cc chn IRQ15 ti IRQ0. IRQn (n=15 ti 0) c cc c im sau y: S dng thanh ghi ISCR, chng ta c th chn mt trong cc ch pht sinh yu cu ngt qung sau: mc thp, cnh xung, cnh ln, hoc c hai; trn cc chn IRQn. Dng thanh ghi IER cm/cho php cc ngt qung IRQn. Dng thanh ghi IPR thit lp u tin ngt qung cho cc ngt qung IRQn. Trng thi ca cc yu cu ngt qung IRQn c ghi li trong thanh ghi ISR. Cc c ISR c th c xa xung 0 bi phn mm. Cc cu lnh x l bit hoc tc v b nh nn c dng xa c trong thanh ghi ISR. Pht hin cc ngt qung IRQn c cho php thng qua vic thit lp cc thanh ghi P1ICR, P2ICR, P5ICR, v P6ICR, v khng thay i bt k thit lp ca ng xut. Tuy nhin, khi mt chn c s dng nh ng nhp cho ngt qung ngoi, chn khng c s dng nh chn xut nhp cho bt c chc nng no khc bng cch xa bit DDR tng ng xung 0. S khi ca cc ngt qung IRQn c m t trong Hnh 5.2.
90
Hnh 5.2 S khi ca cc ngt qung IRQn Khi ch pht sinh ngt qung IRQ c thit lp l mc thp, mc in p chn IRQn nn c gi mc thp cho ti khi mt qu trnh x l ngt qung c khi ng. Sau cho tn hiu ng nhp IRQn tng ng ln mc cao trong thi gian chy chng trnh x l ngt qung v xa IRQnF v 0. Ngt qung c th s khng c thc thi khi tn hiu t ng nhp IRQn tng ng c gi mc cao trc khi qu trnh x l ngt qung bt u. 5.4.2 Cc ngt qung ni Cc ngun ngt qung ni l t cc module ngoi vi ni, v chng c nhng c im chung sau y: Vi mi module ngoi vi ni, ta c cc c ghi trng thi yu cu ngt qung, v cc bit cho php hoc cm ngt qung. Chng c th iu khin ngt qung mt cch c lp. Khi bit cho php c gn ln 1, mt yu cu ngt qung s c pht ti b x l ngt qung. u tin ngt qung c th c thit lp bi thanh ghi IPR. DTC v DMAC c th c kch hot bi TPU, SCI, SSU, hoc cc yu cu ngt qung khc. Vic kch hot DTC v DMAC c th c iu khin bi chc nng iu khin u tin ca CPU i vi DTC v DMAC.
5.5
Bng vector x l ngt qung
Bng 5.2 lit k cc ngun ngt qung, a ch offset cc vector, v u tin ngt qung. Trong th t u tin mc nh, ch s vector nh hn tng ng vi u tin ln hn. Khi ch iu khin ngt qung 2 c chn, cc cp u tin c th thay i bi vic thit lp ni dung thanh ghi IPR. i vi cc ngun ngt qung c phn cng v tr trong IPR, u tin ca chng s tun theo mc nh, tc khng th thay i. Bng 5.2 Ngun ngt qung, a ch offset cc vector v u tin ngt qung
91
Phn loi Chn ngoi
Ngun ngt qung
Ch s vector 7 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87
a ch offset vector* H'001C H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011 C H'0120 H'0124 H'0128 H'012C H'0130 H'0134 H'0138 H'013C H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C
IPR
u Kch Kch tin hot hot DTC DMAC O O O O O O O O O O O O O O O O O O O O
NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 Khng dng cho h thng WDT WOVI D tr cho h thng
Cao IPRA14 ti IPRA12 IPRA10 ti IPRA8 IPRA6 ti IPRA4 IPRA2 ti IPRA0 IPRB14 ti IPRB12 IPRB10 ti IPRB8 IPRB6 ti IPRB4 IPRB2 ti IPRB0 IPRC14 ti IPRC12 IPRC10 ti IPRC8 IPRC6 ti IPRC4 IPRC2 ti IPRC0 IPRD14 ti IPRD12 IPRD10 ti IPRD8 IPRD6 ti IPRD4 IPRD2 ti IPRD0 IPRE10 ti IPRE8
A/D_0 ADI0 A/D_1 ADI1
IPRF10 ti IPRF8 Thp
Phn loi
Ngun ngt Ch s qung vector TGI0A TGI0B TGI0C TGI0D TCI0V TGI1A TGI1 B TCI1V TCI1 U TGI2A TGI2B TCI2V TCI2U TGI3A 88 89 90 91 92 93 94 95 96 97 98 99 100 101
TPU_0
TPU_1
TPU_2
TPU_3
a ch offset vector* H'0160 H'0164 H'0168 H'016C H'0170 H'0174 H'0178 H'017C H'0180 H'0184 H'0188 H'018C H'0190 H'0194
u Kch tin hot DTC IPRF6 ti IPRF4 Cao O O O O IPRF2 ti IPRF0 O O IPRG14 ti IPRG12 O O IPRG10 ti IPRG8 O IPR
Kch hot DMAC O O O O
92
TPU_4
TPU_5
TGI3B TGI3C TGI3D TCI3V TGI4A TGI4B TCI4V TCI4U TGI5A TGI5B TCI5V TCI5U D tr cho h thng
Phn loiNgun ngt qung D tr cho h thng
102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 Ch s vector 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145
DMAC
DMTEND0 DMTEND1 DMTEND2 DMTEND3 D tr cho h thng
DMAC
DMEEND0 DMEEND1 DMEEND2 DMEEND3 D tr cho h thng
H'0198 H'019C H'01A0 H'01A4 H'01A8 IPRG6 ti IPRG4 H'01AC H'01 B0 H'01 B4 H'01 B8 IPRG2 ti IPRG0 H'01 BC H'01C0 H'01C4 H'01 C8 H'01 CC H'01D0 H'01D4 H'01D8 H'01DC H'01 E0 H'01E4 Thp a ch IPR u offset tin vector* H'01 E8 Cao H'01 EC H'01 F0 H'01 F4 H'01 F8 H'01 FC H'0200 IPRI14 ti IPRI12 H'0204 IPRI10 ti IPRI8 H'0208 IPRI6 ti IPRI4 H'020C IPRI2 ti IPRI0 H'0210 H'0214 H'0218 H'021 C H'0220 IPRK14 ti IPRK12 H'0224 H'0228 H'022C H'0230 H'0234 H'0238 H'023C H'0240 H'0244
O O O O O O O Kch hot DTC O O O O O O O O
Kch hot DMAC
93
146 147 148 149 150 151 152 153 154 155
H'0248 H'024C H'0250 H'0254 H'0258 H'025C H'0260 H'0264 H'0268 H'026C
Thp
Phn loi
Ngun ngt Ch s qung vector ERI3 RXI3 TXI3 TEI3 ERI4 RXI4 TXI4 TEI4 TGI6A TGI6B TGI6C TGI6D TCI6V TGI7A TGI7B TCI7V TCI7U TGI8A TGI8B TCI8V TCI8U TGI9A TGI9B TGI9C TGI9D TCI9V TGI10A TGI10B D tr cho h thng D tr cho h thng TCI10V 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186
SCI_3
SCI_4
TPU_6
TPU_7
TPU_8
TPU_9
TPU_10
a ch offset vector* H'0270 H'0274 H'0278 H'027C H'0280 H'0284 H'0288 H'028C H'0290 H'0294 H'0298 H'029C H'02A0 H'02A4 H'02A8 H'02AC H'02B0 H'02B4 H'02B8 H'02BC H'02C0 H'02C4 H'02C8 H'02CC H'02D0 H'02D4 H'02D8 H'02DC H'02E0 H'02E4
IPR
u tin
IPRL10 ti IPRL8 Cao
IPRL6 ti IPRL4
IPRL2 ti IPRL0
IPRM14 ti IPRM12 ti IPRM8 IPRM10 IPRM6 ti IPRM4 IPRM2 ti IPRM0 IPRN14 ti IPRN12 IPRN10 ti IPRN8
IPRN6 ti IPRN4 IPRN2 ti IPRN0
Kch hot DTC O O O O O O O O O O O O O O O O O O O
Kch hot DMAC O O O O O O O O O
H'02E8 IPRO14 ti IPRO12
94
TCI10U
187
H'02EC
Thp
Phn loi
Ngun Ch s ngt qung vector TGI11A TGI11 B TCI11 V TCI11 U D tr cho h thng 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219
TPU_11
a ch IPR u Kch offset tin hot vector* DTC H02F0 IPRO10 ti IPRO8 Cao H'02F4 H'02F8 IPRO6 ti IPRO4 H'02FC H'0300 H'0304 H'0308 H'030C H'0310 H'0314 H'0318 H'031 C H'0320 H'0324 H'0328 H'032C H'0330 H'0334 H'0338 H'033C H'0340 H'0344 H'0348 H'034C H'0350 H'0354 H'0358 H'035C H'0360 H'0364 H'0368 H'036C O Thp
Kch hot DMAC
Phn loi Ngun ngt Ch s qung vector SSU_0 D tr cho 224 h thng 225 226 SSERI0 227
a ch IPR u Kch Kch offset tin hot hot vector* DTC DMAC H'0380 IPRR14 ti IPRR1 Cao H'0384 H'0388 H'038C
95
SSU_1
SSU_2
H'03AC H'03B0 IPRR2 ti IPRR0 H'03B4 H'03B8 H'03BC H'03C0 H'03C4 H'03C8 H'03CC H'03D0 H'03D4 H'03D8 H'03DC H'03E0 H'03E4 H'03E8 H'03EC H'03F0 H'03F4 H'03F8 H'03FC Thp Ch : *16 bit thp ca a ch bt u trong ch nng cao.
SSRXI0 SSTXI0 D tr cho h thng SSERI1 SSRXI1 SSTXI1 D tr cho h thng SSERI2 SSRXI2 SSTXI2 D tr cho h thng
228 229 230 231 232 233 234
H'0390 IPRR10 ti IPRR8 H'0394 H'0398 H'039C H'03A0 IPRR6 ti IPRR4 H'03A4 H'03A8
O O O O O O
O O O O O O
235 236 237 238 239 D tr cho 240 h thng 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255
5.6
Cc ch iu khin ngt qung v tc v ngt qung
B iu khin ngt qung c hai ch iu khin ngt qung: Ch iu khin ngt qung 0 v ch iu khin ngt qung 2. Cc tc v ngt qung s khc nhau ty thuc vo ch iu khin. Ch iu khin ny c chn bi thanh ghi INTCR. Bng 5.3 cho thy s khc nhau gia hai ch . Bng 5.3 Cc ch iu khin ngt qung
Ch iu Thanh ghi Bit mt n khin ngt thit lp ngt qung qung u tin M t
96
Mc nh
Cc cp u tin ca cc ngun ngt qung c thit lp c nh. Cc ngt qung khc NMI c th c che bi bit I.
IPR
I2 ti I0
C th thit lp 8 cp u tin bng cc bit I2 ti I0 trong thanh ghi IPR cho cc ngt qung khc NMI.
5.6.1 Ch iu khin ngt qung 0 Trong ch iu khin ngt qung 0, cc yu cu ngt qung khc NMI c che bi bit I trong thanh ghi CCR ca CPU. Hnh 5.3 cho thy s lu ca tc v chp nhn ngt qung trong trng hp ny. Nu c mt yu cu ngt qung xy ra v bit cho php ngt qung tng ng c lp ln 1, yu cu ngt qung s c gi ti b iu khin ngt qung. Nu bit I trong CCR c lp ln 1, ch c ngt qung NMI c cho php, tt c cc ngt qung khc u phi ch. Nu bit I c xa v 0, yu cu ngt qung s c chp nhn. i vi vic c nhiu yu cu ngt qung ng thi, b iu khin ngt qung s chn yu cu ngt qung c u tin cao nht, v gi n ti CPU, sau cho cc yu cu ngt qung khc ch. Khi CPU chp nhn yu cu ngt qung, n bt u qu trnh x l ngt qung sau khi kt thc cu lnh hin ti. Gi tr cc thanh ghi PC v CCR c lu vo stack trong qu trnh x l ngt qung. Gi tr thanh ghi PC trong stack chnh l a ch dng lnh tip theo sau khi tr v t chng trnh con x l ngt qung. K tip, bit I trong CCR c lp ln 1. Vic ny s che tt c ngt qung khc NMI. CPU s tm a ch vector ca ngt qung c chp nhn v bt u thc thi chng trnh con x l ngt qung ti a ch c ch nh bi a ch vector trong bng vector
97
Hnh 5.3 lu ca th tc chp nhn ngt qung trong ch iu khin ngt qung 0 5.6.2 Ch iu khin ngt qung 2 Trong ch iu khin ngt qung 2, cc yu cu ngt qung khc NMI s c xem xt bng cch so snh cp mt n ngt qung (t bit I2 ti I0) trong thanh ghi EXR ca CPU v thit lp trong IPR. C 8 cp trong vic iu khin mt n. Hnh 5.4 cho thy lu ca tc v chp nhn ngt qung trong trng hp ny. Nu c mt yu cu ngt qung xy ra v bit cho php ngt qung tng ng c lp ln 1, yu cu ngt qung s c gi ti b iu khin ngt qung. i vi vic c nhiu yu cu ngt qung xy ra ng thi, b iu khin ngt qung s chn yu cu ngt qung vi u tin cao nht da theo IPR, v cho cc yu cu ngt qung khc ch. Nu cc yu cu ngt qung c cng u tin, yu cu ngt qung s c chn bng u tin mc nh trong bng 5.2. Tip theo, u tin ca yu cu ngt qung c chn s c so snh vi cp mt n ngt qung trong EXR. Khi yu cu ngt qung ny c u tin thp hn
98
so vi cp mt n, n s c gi ch, v ch c cc yu cu ngt qung c u tin cao hn cp mt n mi c chp nhn. Khi CPU chp nhn mt yu cu ngt qung, n s bt u qu trnh x l ngt qung sau khi thc thi xong cu lnh hin ti. Ni dung cc thanh ghi PC, CCR v EXR c lu vo stack trong qu trnh x l ngt qung. Ni dung thanh ghi PC chnh l a ch lnh k tip c thc thi sau khi quay v t chng trnh con phc v ngt qung. Bit T trong thanh ghi EXR c xa xung 0. Cp mt n ngt qung s c ghi li vi u tin ca ngt qung c cho php. Nu ngt qung ny l NMI, cp mt n ngt qung s c lp ln H7. CPU s tm a ch vector ca ngt qung c chp nhn v bt u thc thi chng trnh con x l ngt qung ti a ch c ch nh bi a ch vector trong bng vector
99
Hnh 5.4 S dng chy ca th tc chp nhn ngt qung trong ch iu khin ngt qung 0 5.6.3 Qu trnh x l ngt qung Hnh 5.5 cho thy qu trnh x l ngt qung. V d ny l trng hp ch iu khin ngt qung 0 c thit lp ln ch ti a, cc vng stack v chng trnh u nm trn b nh ni
Hnh 5.5 Qu trnh x l ngt qung 5.6.4 Thi gian p ng ngt qung Bng 5.4 cho thy thi gian p ng ngt qung khong thi gian t lc pht yu cu ngt qung n khi cu lnh u tin trong chng trnh con phc v ngt qung
100
c thc thi. The symbols for execution states used in Bng 5.4 are explained in Bng 5.5. Vi iu khin ny c th chuyn d liu trong b nh ni rt nhanh, v vy t chng trnh trn ROM ni v stack trn RAM ni cho php tc x l cao. Bng 5.4 Thi gian p ng ngt qung
Trng thi thc thi Ch bnh thng5 Ch iu khin ngt qung 0 Ch iu khin ngt qung 2 Ch nng cao Ch iu khin ngt qung 0 3 Ch iu khin ngt qung 2 Ch ti a5 Ch iu khin ngt qung 0 Ch iu khin ngt qung 2
Quyt nh u tin ngt qung1 S chu k cho ti lc thc thi xong lnh2 Lu PC, CCR, EXR Np vector Np lnh3 X l ni4 Tng cng 10 ti 31 11 ti 31 10 ti 31 SK ti 2SK*6 2SK
1 to 19 + 2SI
SK ti 2SK*6 Sh
2SK
2SK
2SK
2.SI 2 11 ti 31 11 ti 31 11 ti 31
Ch : 1. Hai trng thi cho ngt qung ni. Trong trng hp s dng lnh MULXS hay DIVXS Np sau khi chp nhn ngt qung hoc cho mt cu lnh ca chng trnh x l ngt qung. Tc v bn trong sau khi chp nhn ngt qung hay sau khi np vector Khng c trong Vi iu khin ny. Khi thit lp thanh ghi SP ln 4n, thi gian p ng ngt qung l S k; khi thit lp ln 4n + 2, thi gian p ng ngt qung l 2Sk. Bng 5.5 S lng trng thi thc thi trong chng trnh con phc v ngt qung
101
i tng truy cp Thit b ngoi Bus 8-bit B nh ni 1 1 2 Truy cp 2 chu k 8 4 8 Truy cp 3 chu k 12+4m 6+2m 12+4m Bus 16-bit Truy cp 2 chu k 4 2 4 Truy cp 3 chu k 6+2m 3+m 6+2m Bus 32-bit Truy cp 2 chu k 2 2 2 Truy cp 3 chu k 3+m 3+m 3+m
K hiu Np vector Sh Np lnh SI iu khin vector Sk Ghi ch: m:
S chu k i khi truy cp thit b ngoi.
5.6.5 Kch hot DTC v DMAC bi ngt qung DTC v DMAC c th c kch hot bi mt ngt qung. Trong trng hp ny, nhng la chn sau c chp nhn: Yu cu ngt qung ti CPU Yu cu ngt qung ti DTC Yu cu kch hot ti DMAC Kt hp gia nhng cch trn xem chi tit cc yu cu ngt qung c th c s dng kch hot DMAC, xem Bng 5.2 v phn 7, B iu khin DMA (DMAC), v phn 8, B iu khin truyn d liu (DTC). Hnh 5.6 cho s khi ca DTC, DMAC, v b iu khin ngt qung.
102
Hnh 5.6 S khi ca DMAC v b iu khin ngt qung La chn ngun ngt qung: Cc ngun kch hot ca tng knh DMAC c chn bi thanh ghi DMRSR. Ngun kch hot c chn l ng nhp ca DMAC thng qua mt mch chn. Khi vic truyn d liu bi mt ngt qung ni c cho php (DTF1 = 1, DTF0 = 0, DTA = 1) v bit DTE trong DMDR c lp ln 1, ngt qung c chn lm ngun kch hot DMAC s c iu khin bi DMAC v khng th dng lm ngun kch hot DTC hoc ngun ngt qung ca CPU c na. Ngun ngt qung khng b iu khin bi DMAC s c gn lm ngun kch hot DTC hay ngun ngt qung CPU bi bit DTCE trong DTCERA ti DTCERH ca DTC. Xc nh bit DISEL trong MRB ca DTC pht ra cc yu cu ngt qung ti CPU bng cch xa bit DTCE sau khi truyn d liu ca DTC kt thc. Ch rng khi DTC xc nh trc s lng d liu c truyn v bin m c gn gi tr 0, mt yu cu ngt qung c to ra bi CPU bng cch xa bit DTCE v 0 sau khi DTC truyn d liu. Khi c cng mt ngun ngt qung c chn lm ngun kch hot DTC v ngun ngt qung CPU, DTC phi c gn u tin cao hn CPU. Nu bit IPSETE trong CPUPCR c lp ln 1, u tin c xc nh da vo thanh ghi IPR. V th, CPUP hoc IPR tng ng vi ngun ngt qung phi c gn tr nh hn hoc bng gi tr ca DTCP. Nu CPU c gn u tin cao hn DTC, DTC c th khng c kch hot , v vic truyn d liu c th khng c thc hin. Xc nh u tin: Ngun kch hot DTC c chn da trn u tin mc nh, v s la chn ny khng b nh hng bi cp mt n hoc cp u tin ca n. Th t tc v: Nu cng mt ngt qung c chn lm ngun kch hot DTC v ngun ngt qung CPU, chng trnh x l ngt qung ca CPU s c thc thi sau tc v truyn d liu ca DTC. Nu c cng ngt qung c chn lm ngun kch hot DTC, DMAC v CPU, cc tc v tng ng s c thc thi c lp.
103
Bng 5.6 lit k nhng la chn ngun kch hot DMAC, la chn ngun ngt qung v iu khin xa ngun ngt qung bng cch thit lp cc bit DTCE trong DTCERA ti DTCERH ca DTC v bit DISEL trong MRB ca DTC. Bng 5.6 iu khin chn/xa ngun ngt qung
Thit lp DMAC DTE 0 0 1 Thit lp DTC DTCE * 0 1 1 * * DISEL X X X V iu khin chn/xa ngun ngt qung DMAC X V O X DTC V X V X CPU
Ghi ch: V: Ngt qung tng ng c dng. Ngun ngt qung b xa. (C ca ngun ngt qung phi c xa bi chng trnh con phc v ngt qung ca CPU) O: X: *: Ngt qung tng ng c dng. Ngun ngt qung khng b xa. Ngt qung tng ng cha sn sng. Khng quan tm.
Ch khi s dng: Ngun ngt qung ca SCI v b chuyn AD c xa bng vic thit lp nh Bng 5.6, khi DTC v DMAC c/ghi cc thanh ghi nu trn. bt u a knh vi DTC v DMAC bng cng mt ngt qung, u tin bng nhau cn c gn 5.7 Chc nng iu khin u tin CPU trn DTC v DMAC
B iu khin ngt qung c mt chc nng dng iu khin u tin gia DTC, DMAC v CPU bng cch gn cc u tin khc nhau cho chng. Bi v u tin c th c gn t ng vo CPU bng mt ngt qung xy ra, nn mt chng trnh x l ngt qung trong CPU c th c thc thi trc khi truyn d liu ca DTC v DMAC. u tin ca CPU c th c gn bi cc bit CPUP2 ti CPUP0 trong CPUPCR. u tin ca DMAC c gn cho tng knh bi cc bit DMAP2 ti DMAP0 trong cc thanh ghi iu khin ch DMA 0 ti 3 (DMDR_0 ti DMDR_3). Chc nng iu khin u tin trn DTC v DMAC c cho php bi vic lp bit CPUPCE trong thanh ghi CPUPCR ln 1. Khi CPUPCE l 1, ngun kch hot DTC v DMAC c iu khin da trn u tin tng ng.
104
Ngun kch hot DTC c iu khin da trn u tin ca CPU, c ch nh bi cc bit CPUP2 ti CPUP0 v u tin ca DTC, c ch nh bi cc bit DTCP2 ti DTCP0. Nu CPU c u tin cao hn, ngun kch hot DTC s b gi li. DTC ch c kch hot khi vic gi ngun kch hot ny b hy b (CPUCPCE = 1 v gi tr ca cc bit CPUP2 ti CPUP0 ln hn gi tr ca DTCP2 ti DTCP0). u tin ca DTC c ch nh bi cc bit DTCP2 ti DTCP0 bt k ngun kch hot. u tin ca DMAC c th c ch nh cho tng knh. Ngun kch hot DMAC c iu khin da trn u tin ca CPU v u tin ca DMAC, c ch nh bi cc bit DMAP2 ti DMAP0. Nu CPU c u tin cao hn, ngun kch hot DMAC s b gi li. DMAC ch c kch hot khi vic gi ngun kch hot ny b hy b (CPUCPCE = 1 v gi tr ca cc bit CPUP2 ti CPUP0 ln hn gi tr cc bit DMAP2 ti DMAP0). Khi cc u tin khc nhau ca DMAC c gn cho cc knh, knh c u tin cao hn s tip tc truyn d liu trong khi knh c u tin thp hn CPU s b gi li. C hai phng thc gn u tin cho CPU bng bit IPSETE trong thanh ghi CPUPCR. Lp bit UPSETE ln 1 cho php chc nng t gn gi tr ca bin mt n ngt qung CPU vo u tin ca CPU. Xa bit IPSETE xung 0 s cm chc nng ny. Khi , u tin s c gn trc tip bng phn mm ghi li gi tr cc thanh ghi CPUP2 ti CPUP0. Ngay c khi IPSETE bng 1, u tin ca CPU vn c th c gn bi phn mm bng cch ghi li gi tr ca bit mt n ngt qung CPU (Bit I trong CCR hay I2 ti I0 trong EXR). u tin c t ng gn khi bit IPSETE bng 1 s khc nhau ty thuc vo ch iu khin ngt qung. Trong ch iu khin ngt qung 0, bit I trong thanh ghi CCR ca CPU c gn vo bit CPUP2. Cc bit CPUP1 v CPUP0 c c nh gi tr 0. Trong ch iu khin ngt qung 2, gi tr ca cc bit I2 ti I0 trong EXR ca CPU c gn vo cc bit CPUP2 ti CPUP0. Bng 5.7 iu khin u tin CPU
Trng thi iu khin Ch iu khin ngt qung 0 u Bit mt n Bit IPSETE CPUP2 ti tin ngt ngt trong CPUP0 qung qung CPUPCR Mc nh I bt k I=0 I=1 2 Thit lp I2 ti I0 ca IPR 0 1 0 1 Cp nht ca CPUP2 ti CPUP0
B'111 ti B'000 Cho php B'000 B'100 B'111 ti B'000 Cho php I2 ti I0 Cm Cm
105
Bng 5.8 cho thy mt v d vic thit lp chc nng iu khin u tin cho DTC v DMAC v trng thi iu khin yu cu truyn d liu. Mc d u tin ca DMAC c th c gn cho tt c cc knh, Bng 5.8 cho thy bng m t ca mt knh n. V vy, tng knh c th truyn d liu mt cch c lp bi gn cc u tin khc nhau. Bng 5.8 V d ca vic thit lp chc nng iu khin u tin v trng thi iu khin
CPUPCE trong Ch iu CPUPCR khin ngt qung CPUP2 ti CPUP0 DTCP2 DMAP2 ti ti DTCP0 DMAP0 Trng thi iu khin yu cu truyn d liu DTC 0 0 1 Bt k B'000 B'100 B'100 B'100 B'000 2 0 1 Bt k B'000 B'000 B'011 B'100 B'101 B'110 B'111 B'101 Bt k B'000 B'000 B'000 B'111 B'111 Bt k B'000 B'011 B'011 B'011 B'011 B'011 B'011 B'011 Bt k B'000 B'000 B'011 B'101 B'101 Bt k B'000 B'101 B'101 B'101 B'101 B'101 B'101 B'101 DMAC
Cho php Cho php Cho php Cho php Che Che Che Che
Cho php Cho php Cho php Cho php Cho php Cho php Cho php Cho php Cho php Cho php Cho php Cho php Che Che Che Che Che Cho php Cho php Che Che Cho php
106
B'101
B'110
B'101
Cho php Cho php
5.8
Ch khi s dng
5.8.1 Xung t gia to v cm ngt qung Khi mt bit cho php ngt qung c xa v 0 che ngt qung, vic che ny s c hiu qu ngay sau khi thc hin cu lnh. Khi mt bit ngt qung c xa v 0 bi cu lnh nh BCLR hay MOV, nu mt ngt qung c to ra trong khong thi gian thc thi cu lnh, ngt qung ny vn c cho php sau khi hon thnh cu lnh, v qu trnh x l ngt qung cho ngt qung y vn c thc thi sau khi hon tt cu lnh. Tuy nhin, nu c mt yu cu ngt qung vi u tin cao hn ngt qung , qu trnh x l ngt qung s chp nhn ngt qung mi, v ngt qung trc b b qua. Vic xy ra tng t khi ta xa c ngun ngt qung xung 0. Nhng xung t trn s khng xy ra nu ta xa c ngt qung hay bit cho php v 0 trong khi ngt qung kia b che.
Hnh 5.7 Xung t gia to v cm ngt qung Ging vy, khi c mt ngt qung c yu cu ngay sau khi bit cho php DTC c thay i kch hot DTC, vic kch hot DTC v qu trnh x l ngt qung s c CPU thc thi c hai. Khi thay i bit cho php DTC, cn phi chc rng khng c mt ngt qung no c yu cu. 5.8.2 Lnh cm ngt qung Cc cu lnh cm ngt qung ngay lp tc sau khi thc thi l LDC, ANDC, ORC v XORC. Sau khi bt k lnh no trn y c thc hin, tt c cc ngt qung bao gm c NMI s b cm, v dng lnh tip theo lun c thc hin. Khi bit
107
I c lp bi mt trong cc cu lnh trn, gi tr mi s c hiu lc sau khi cu lnh kt thc c 2 chu k. 5.8.3 Nhng lc ngt qung b cm C nhng lc vic chp nhn ngt qung s b cm bi b iu khin ngt qung. iu khin ngt qung s cm ngt qung trong khong thi gian 3 chu k sau khi CPU cp nht cp mt n vi cc cu lnh LDC, ANDC, ORC, hoc XORC; v trong khong thi gian ghi cc thanh ghi trong b iu khin ngt qung. 5.8.4 Ngt qung khi ang thc thi cu lnh EEPMOV Tc v ngt qung khc nhau gia 2 lnh EEPMOV.B v EEPMOV.W. Vi cu lnh EEPMOV.B, mt yu cu ngt qung (k c NMI) c to ra trong qu trnh truyn s khng c chp nhn cho n khi truyn xong. Vi cu lnh EEPMOV.W, nu mt yu cu ngt qung c to ra trong qu trnh truyn, chng trnh phc v ngt qung s bt u khi kt thc chu k truyn n. Gi tr thanh ghi PC c lu vo stack trong trng hp ny chnh l a ch lnh tip theo. V th, nu mt ngt qung c to ra trong qu trnh thc thi lnh EEPMOV.W, nhng dng lnh sau nn c s dng. L1 : EEPMOV.W MOV.W R4,R4 BNE L1 5.8.5 Ngt qung khi ang thc thi cu lnh MOVMD v MOVSD. Vi cc cu lnh MOVMD v MOVSD , nu c mt yu cu ngt qung c to ra trong qu trnh truyn, vic x l ngt qung s bt u khi kt thc chu k truyn n. Thanh ghi PC c lu vo stack trong trng hp ny l a ch ca lnh MOVMD v MOVSD. Vic truyn d liu cn li c phc hi sau khi quay v t chng trnh phc v ngt qung. 5.8.6 C ngt qung ca cc thit b ngoi vi xa mt c yu cu ngt qung bng CPU, c nn c c trc khi xa nu xung module ngoi vi c to ra bi chia tn s xung h thng. iu ny lm cho tn hiu yu cu ng b vi xung h thng. bit thm chi tit, xem phn 18.5.1.
108
Chng 6 Cc cng xut nhp

Bng 6.1 tm tt cc chc nng ca cc port xut nhp. Cc chn ca mi port cng c cc chc nng khc nhau v d cc chn xut nhp ca cc khi ngoi vi trn chip hay cc chn nhp tn hiu ngt ngoi. Mi mt port xut nhp bao gm mt thanh ghi trc tip d liu DDR iu khin xut nhp, mt thanh ghi d liu DR lu tr d liu xut, mt thanh ghi PORT s dng cho vic c cc trng thi ca chn, v mt thanh ghi iu khin buffer iu khin tt/m buffer nhp. Cc port 4 v 5 khng c thanh ghi DR hay DDR. Cc port D, H, I, J, v K c cc ko ln nhp bn trong dng MOS v mt thanh ghi PCR iu khin cc ko ln ny. Port 2 c mt thanh ghi ODR dng iu khin tn hiu xut c dng open-drain. S chnh dng tn hiu nhp (schmitt-trigger input) c th c s dng khi m mt port c s dng vi chc nng l tn hiu nhp ca mt ngt qung hay ca b nh thi TPU Bng 6.1 Cc chc nng ca cc cng
Cng
c t
Bit Xut nhp
Chc nng Nhp Xut
SchmittTrigger Input*1
Chc nng nhp c ko ln dng MOS ---
Chc nng xut opendrain
Port 1
Port I/O a nng cng c chc nng nh l cc ng nhp tn hiu ngt qung, tn hiu xut nhp SCI, v c tn hiu nhp ca trnh chuyn i A/D
P17
ADTRG1/
IRQ7
---
IRQ7
---
6 5
P16/SCK3 P15
IRQ6
RxD3/
-----
IRQ6 IRQ5
IRQ5
4 3 P14 P13
IRQ4
ADTRG0/
TxD3 ---
IRQ4 IRQ3
IRQ3
2 P12
IRQ2
---
IRQ2
109
1 0 Port 2 Port xut 7 nhp a nng cng c chc nng nh l cc port nhp 6 tn hiu ngt qung, xut nhp TPU, v xut nhp SSU, 5
P11 P10 P27/ TIOCB5
IRQ1 IRQ0 IRQ15 -A/

TIOCA5
-------
IRQ1 IRQ0
P27, TIOCA5, TIOCB5, --O
IRQ15 A/ P26/ TIOCA5 --P26, TIOCA5,
IRQ14 -A/
IRQ14 A/ P25/ TIOCA4 --P25, IRQ13-A, TIOCA4
IRQ13 -A/
P24/ TIOCB4
TIOCA4/
---
P24, TIOCA4, TIOCB4, IRQ12-A
IRQ12 -A/
P23/ TIOCD3
TIOCC3/
---
P23, TIOCC3, TIOCD3,
IRQ11 -A/
IRQ11 A/ 2 P22/ TIOCC3 --P22, TIOCC3,
IRQ10 -A/
IRQ10 A/ 1 P21/ TIOCA3/ --P21, TIOCA3,
IRQ9 -A/
SCS2
0 P20/ TIOCA3/ ---
IRQ9 -A/
P20,
110
TIOCB3
IRQ8 -A/
TIOCA3, TIOCB3,
IRQ8 -A/
Port 3 Port xut 3 nhp a nng cng bao gm chc nng xut 2 PPG v xut nhp TPU 7 P33/ TIOCD0 TIOCC0/ TCLKB PO11 P33, TIOCC0, TIOCD0, TCLKB P32/ TIOCC0 TCLKA PO10 P32, TIOCC0, TCLKA P37/ TIOCB2 TIOCA2/ TCLKD PO15 P37, TIOCA2, TIOCB2, TCLKD 6 P36/ TIOCA2 5 P35/ TIOCB1 TIOCA1/ TCLKC PO13 --PO14 P36, TIOCA2 P35, TIOCA1, TIOCB1, TCLKC 4 P34/ TIOCA1 1 P31/ TIOCB0 TIOCA0 PO9 --PO12 P34, TIOCA1 P31, TIOCA0, TIOCB0 0 P30/ TIOCA0 Port 4 Port xut nhp a nng cng c chc nng nhp tn 7 6 5 4 --------P47/AN11 P46/AN10 P45/AN9 P44/AN8 ----------PO8 P30, TIOCA0 -----------
111
hiu A/D
3 2 1 0
------------------------P67
P43/AN15 P42/AN14 P41/AN13 P40/AN12 P57/AN7 P56/AN6 P55/AN5 P54/AN4 P53/AN3 P52/AN2 P51/AN1 P50/AN0
-------------------------------
Port 5
Port xut nhp a nng cng c chc nng nhp tn hiu A/D
7 6 5 4 3 2 1 0
Port 6
Port xut 7 nhp a nng c c chc 6 nng xut nhp SCI, v nhp tn hiu ngt 5
IRQ15 -B/ ---
IRQ15 -B/
P66
IRQ14 -B/ ---
IRQ14 -B/
P65
IRQ13 -B/ ---
IRQ13 -B/
P64
IRQ12 -B/ ---
IRQ12 -B/
P63
IRQ11 -B/
---
IRQ11 -B/
P62/SCK4
IRQ10 -B/ ---
IRQ10 -B/
P61
RxD4/
---
IRQ9 -B/
IRQ9 -B/
112
P60
IRQ8 -B/
TxD4
IRQ8 -B/
Port A
Port xut nhp a nng cng bao gm chc nng xut nhp SSU v xut B
7 6 5 4 3
--PA6 PA5 PA4 PA3/SSO 2 PA2/SSI2
PA7 ---------
B ---------
---
---
O Ch cho SSU
2 1 0 Port B Port a nng 2 1 0
---
-------------------
PA1/SSCK2 --PA0 PB2 PB1 PB0 ---------
Cng
c t
Bi t
Chc nng Xut nhp Nhp Xut
SchmittTrigger Input*1
Chc nng nhp c ko ln dng MOS
Chc nng xut opendrai n
Port D
Port xut 7 nhp a nng cng c chc 6 nng xut nhp SSU 5 4 3
PD7/
---
---
---
O Ch cho SSU
SCS1
PD6/SSCK 1 PD5/SSI1 PD4/SSO1 PD3/ -----
-------
-------
SCS0
2 PD2/SSCK 0 -----
113
1 0 Port H Port xut nhp a nng 7 6 5 4 3 2 1 0 Port I Port xut nhp a nng 7 6 5 4 3 2 1 0 Port J Port xut nhp a nng cng c chc nng xut nhp TPU 7
PD1/SSI0 PD0/SSO0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 PJ7/ TIOCB8
------------------------------------TIOCA 8/ TCLKH
------------------------------------------------------PJ7, TIOCA8, TIOCB8, TCLKH O --O ----O ---
PJ6/ TIOCA8
---
---
PJ6, TIOCA8
PJ5/ TIOCB7
TIOCA 7/ TCLKG
---
PJ5, TIOCA7, TIOCB7, TCLKG
PJ4/
---
---
PJ4,
114
TIOCA7 3 PJ3/ TIOCD6 TIOCC6 / TCLKF ---
TIOCA7 PJ3, TIOCC6, TIOCD6, TCLKF
PJ2/ TIOCC6
TCLKE
---
PJ2, TIOCC6, TCLKE
PJ1/ TIOCB6
TIOCA 6
---
PJ1, TIOCA6, TIOCB6
PJ0/ TIOCA6
---
---
PJ0, TIOCA6
Port K
Port xut nhp a nng cng c chc nng xut nhp TPU
PK7/ TIOCB11
TIOCA 11
---
PK7, TIOCA1 1, TIOCB1 1
---
PK6/ TIOCA11
---
---
PK6, TIOCA1 1
PK5/ TIOCB10
TIOCA 10
---
PK5, TIOCA1 0, TIOCB1 0
PK4/ TIOCA10
---
---
PK4, TIOCA1 0
PK3/ TIOCD9
TIOCC9
---
PK3, TIOCC9, TIOCD9
PK2/ TIOCC9
---
---
PK2, TIOCC9
115
PK1/ TIOCB9
TIOCA 9
---
PK1, TIOCA9, TIOCB9
PK0/ TIOCA9
---
---
PK0, TIOCA9
Ch : Cc chn m khng c buffer nhp Schmitt-trigger th c buffer nhp CMOS
6.1 c t cc thanh ghi

Bng 6.2 Cc thanh ghi ca mi port
Cng S lng chn 8 4 8 8 8 7 7 3 8 8 8 8 8 Cc thanh ghi DDR O O O ----O O O O O O O O DR O O O ----O O O O O O O O PORT O O O O O O O O O O O O O ICR O O O O O O O O O O O O O PCR ----------------O O O O O ODR --O ----------------------PHRTIDR ------------------O -------
Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port A Port B* Port D Port H Port I Port J Port K
Ghi ch: O: c thanh ghi ---: khng c thanh ghi Ch : * 3 bit thp l hp l v 5 bit cao l d tr. Gi tr ghi vo lun nn l gi tr khi ng
116
Hnh 6.1 l mt s khi ca port
Hnh 6.1 S khi 6.1.1 Thanh ghi trc tip d liu (PnDDR) (n=1 n 3, 6, A, B, D, H, I, J, v K) DDR l mt thanh ghi 8-bit ch ghi, ch ra port xut nhp ca tng bit. Mt tc v c t thanh ghi DDR l khng hp l.
117
Khi m chc nng ca port xut nhp c chn, th chn tng ng s c chc nng l mt port xut nu bit v tr tng ng vi n trong thanh ghi DDR c thit lp l 1. Ngc li, chn ny thc hin chc nng nh l mt port nhp nu v tr bit tng ng ca n trong thanh ghi DDR c thit lp l 0.
Ch : 3 bit thp l hp l v 5 bit cao l d tr i vi thanh ghi trc tip d liu port B. 6.1.2 Thanh ghi d liu (PnDR) (n=1 n 3, 6, A, B, D, H, I, J, v K) Thanh ghi DR l mt thanh ghi 8-bit c th c/ghi n l ni lu tr d liu xut ca cc chn c s dng nh l cc cng xut a nng (thanh ghi gi tr xut). Gi tr c khi u ca thanh ghi ny l H00.
Ch : i vi thanh ghi d liu port B (PBDR) th 3 bit thp l hp l cn 5 bit cao l c d tr. 6.1.3 Thanh ghi cng (PORTn) (n=1 n 6, A, B, D, H, I, J, v K) Thanh ghi PORT l mt thanh ghi 8-bit ch c n phn nh cc trng thi ca cc chn thuc cng. Mt tc v ghi vo thanh ghi ny s l khng hp l. Khi thanh ghi PORT c c, th cc bit trong thanh ghi DR m c cc bit tng ng trong thanh ghi DDR c thit lp l 1 s c c (ngha l c d liu c xut ra) v cc trng thi ca mi chn m c cc bit tng ng trong thanh ghi DDR c xa xung 0 cng c c (ngha l c trng thi ca cc chn thuc cng) m khng quan tm n gi tr ca thanh ghi ICR. Gi tr khi u ca thanh ghi PORT l khng xc nh v n c quyt nh da vo cc trng thi ca cc chn cng.
Ch : i vi thanh ghi port B (PORTB) th 3 bit thp l hp l cn 5 bit cao l c d tr. 6.1.4 Thanh ghi iu khin buffer nhp (PnICR) (n=1 n 6, A, B, D, H, I, J, v K)
118
Thanh ghi ICR l mt thanh ghi c th c/ghi 8-bit n iu khin buffer cng nhp. Khi cc bit trong thanh ghi ICR c thit lp l 1, th cc buffer nhp ca cc chn tng ng l hp l. Cn nu cc bit trong thanh ghi ny c xa xung 0, th cc buffer nhp tng ca cc chn tng ng l khng hp l v lc cc tn hiu nhp s c c nh mc in th cao. Khi cc chn thc hin chc nng nh l mt cng nhp cho cc module ngoi vi, th cc bit tng ng nn c thit lp l 1. Gi tr khi to nn c ghi vo mt bit m c chn tng ng l khng c s dng nh l mt cng nhp hay c s dng nh l mt chn xut nhp tn hiu tng t. Khi thanh ghi PORT c c, th cc trng thi ca chn lun lun c c m khng quan tm n gi tr trong thanh ghi ICR. Cc module trn chip l khng b nh hng bi cc trng thi ca chn khi gi tr ca thanh ghi ICR c xa xung 0. Khi thanh ghi ICR b chnh sa, th mt cnh trong (internal edge) c th s c xy ra ph thuc vo cc trng thi ca chn. Do , thanh ghi ICR nn c chnh sa khi m cc chn nhp tng ng khng c s dng. V d, trong vic nhp tn hiu IRQ, chnh sa thanh ghi ICR trong khi ngt qung b cm, xa c IRQF trong thanh ghi ISR ca iu khin ngt xung 0, v sau cho php tr li vic ngt qung tng ng. Nu mt cnh xung xy ra sau khi thanh ghi ICR c thit lp, th cnh xung ny s b hy b. Gi tr khi to ca thanh ghi ICR l H00.
6.1.5 Thanh ghi iu khin ko ln dng MOS (pull up MOS) (PnPCR) (n= D, H, I, J, v K) Thanh ghi PCR l mt thanh ghi c th c/ghi 8-bit n iu khin trng thi tt/m ko ln MOS ca cng nhp. Nu mt bit trong thanh ghi PCR c thit lp l 1 trong khi chn ang trong trng thi nhp, th pull-up MOS nhp tng ng vi bit trong thanh ghi PCR l c m. Bng 6.3 s ch ra trng thi nhp pull-up MOS (ko ln MOS). Gi tr khi to ca thanh ghi PCR l H00.
Bng 6.3 Trng thi pull-up MOS nhp

Cng Trng thi chn Khi Trng thi standby phn Thao tc
119
ng Port D Xut module ngoi vi trn chip Cng nhp Port H Cng xut Cng nhp Port I Cng xut Cng nhp Port J Xut module ngoi vi trn chip Cng nhp Port K Xut module ngoi vi trn chip Cng nhp Tt Tt Tt Tt Tt Tt Tt Tt Tt Tt
mm Tt Tt Tt Tt Tt M/Tt Tt Tt Tt Tt
khc Tt M/Tt Tt M/Tt Tt M/Tt Tt M/Tt Tt M/Tt
Ghi ch: Tt: ko ln MOS nhp lun lun tt M/Tt: Nu thanh ghi PCR c thit lp l 1, th pull-up MOS nhp l m; Nu thanh ghi PCR c xa xung 0, th pull-up MOS nhp l tt. 6.1.6 Thanh ghi iu khin Open-Drain (PnODR) (n=2)
Thanh ghi ODR l mt thanh ghi c th c/ghi 8-bit n la chn chc nng xut open-drain. Nu mt bit ca thanh ghi ODR c thit lp l 1, th chc nng ca chn tng ng vi bit ny s nh l mt ng xut NMOS open-drain. Nu mt bit trong thanh ghi ODR c xa xung 0, th chn tng ng vi bit trong ODR s thc hin chc nng nh l mt ng xut CMOS. Gi tr khi u ca thanh ghi ODR l H00. 6.1.7 Thanh ghi d liu nhp thi gian thc cng H (PHRTIDR) Thanh ghi PHRTIDR lu tr cc trng thi ca port H s dng chn IRQ14 nh l mt trigger. Bng vic kim tra trn cc bit IRQ14SR v IRQ14SF trong thanh ghi ISCRH v cc tn hiu tch cc c th c la chn, tch cc mc thp, cnh xung, cnh ln hay c hai cnh. Chi tit tham kho phn thanh ghi ISCRH v ISCRL ca phn b iu khin ngt qung.
120
6.2 iu khin buffer xut

Phn ny s c t u tin xut ca mi chn Tn ca mi chn module ngoi vi l c theo sau bi _OE. iu ny (v d MIOCA4_OE) ch ra rng liu tn hiu xut ca chc nng tng ng l hp l (1) hay l mt s thit lp khc c ch nh. Bng 6.4 s lit k mi s thit lp cc tn hiu hp l xut. Chi tit v cc tn hiu xut tng ng, tham kho c t thanh ghi ca mi module ngoi vi. Nu tn ca mi chn module ngoi vi c theo sau bi A hay B, chn chc nng c th c chnh sa bi thanh ghi iu khin chc nng cng (PFCR). Chi tit, tham kho Chng 6.3.3, Thanh ghi iu khin chc nng port B (PFCRB). 6.2.1 Cng 1 P17/ ADTRG1 / IRQ7 : Chc nng ca chn c chuyn i nh trnh by di thng qua vic thit lp bit P17DDR Thit lp Cng IO Tn module Port xut nhp Chc nng chn P17 xut P17 nhp (trng thi khi u) P17DDR 1 0
P16/SCK3/ IRQ6 : Chc nng ca chn c chuyn i nh trnh by di thng qua vic thit lp bit P16DDR v SCI_3 (knh giao tip tun t 3, chi tit tham kho phn giao tip tun t SCI) Thit lp SCI_3 Tn module SCI_3 Port I/O Chc nng chn SCK3 xut P16 xut SCK3_OE 1 0 Cng IO P16DDR --1 0
P16 nhp(trng thi khi u) 0
121
P15/RxD3/ IRQ5 : Chc nng ca chn c chuyn i nh trnh by di thng qua vic thit lp bit P16DDR. Thit lp Cng IO Tn module Port xut nhp Chc nng chn P15 xut P15 nhp (trng thi khi u) 1 0 P15DDR
P14/TxD3/ IRQ4 : Chc nng ca chn c chuyn i nh trnh by di thng qua vic thit lp bit P14DDR v SCI_3 Thit lp SCI_4 Tn module SCI_3 Port I/O Chc nng chn TxD3xut P14 xut P14 nhp(trng thi khi u) TxD3_OE 1 0 0 Cng IO P14DDR --1 0
P13/ ADTRG0 / IRQ3 : Chc nng ca chn c chuyn i nh trnh by di thng qua vic thit lp bit P13DDR. Thit lp Cng IO Tn module Port xut nhp Chc nng chn P13 xut P13 nhp (trng thi khi u) P13DDR 1 0
P12/ IRQ2 : Chc nng ca chn c chuyn i nh trnh by di thng qua vic thit lp bit P12DDR. Tn module Chc nng chn Thit lp
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Cng IO P12DDR Port xut nhp P12 xut P12 nhp (trng thi khi u) 1 0
P11/ IRQ1 : Chc nng ca chn c chuyn i nh trnh by di thng qua vic thit lp bit P11DDR Thit lp Cng IO Tn module Port xut nhp Chc nng chn P11 xut P11 nhp (trng thi khi u) P11DDR 1 0
P10/ IRQ0 : Chc nng ca chn c chuyn i nh trnh by di thng qua vic thit lp bit P10DDR Thit lp Cng IO Tn module Port xut nhp Chc nng chn P10 xut P10 nhp (trng thi khi u) 6.2.2 Cng 2 P27/TIOCA5/TIOCB5/ IRQ15 -A: Chc nng ca chn c chuyn i nh trnh by bng di y thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port 9 (PFCR9), TPU_5 (knh 5 ca b nh thi, chi tit tham kho b nh thi TPU), v bit P27DDR. Thit lp TPU_5 Tn module Chc nng chn TIOCB5_OE Port IO P27DDR P10DDR 1 0
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TPU_5 Port I/O
TIOCB5 xut P27 xut P27 nhp(trng thi khi u)
1 0 0
--1 0
P26/TIOCA5/ IRQ14 -A: Chc nng ca chn c chuyn i nh trnh by bng di y thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port 9 (PFCR9), TPU_5, v bit P26DDR. Thit lp TPU_5 Tn module TPU_5 Port I/O Chc nng chn TIOCA5 xut P26 xut P26 nhp(trng thi khi u) TIOCA5_OE 1 0 0 Cng IO P26DDR --1 0
P25/TIOCA4/ IRQ13 -A: Chc nng ca chn c chuyn i nh trnh by bng di y thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port 9 (PFCR9), TPU_4, v bit P25DDR. Thit lp TPU_4 Tn module TPU_4 Port I/O Chc nng chn TIOCA4 xut P25 xut P25 nhp(trng thi khi u) TIOCA4_OE 1 0 0 Cng IO P25DDR --1 0
P24/TIOCA4/TIOCB4/ IRQ12 -A: Chc nng ca chn c chuyn i nh trnh by bng di y thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port 9 (PFCR9), TPU_4, v bit P24DDR. Thit lp TPU_4 Tn module Chc nng chn TIOCB4_OE Cng IO P24DDR
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TPU_4 Port I/O
TIOCB4 xut P24 xut P24 nhp(trng thi khi u)
1 0 0
--1 0
P23/TIOCC3/TIOCD3/ IRQ11 -A: Chc nng ca chn c chuyn i nh trnh by bng di y thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port 9 (PFCR9), TPU_3, v bit P23DDR. Thit lp TPU_3 Tn module TPU_3 Port I/O Chc nng chn TIOCD3 xut P23 xut P23 nhp(trng thi khi u) TIOCD3_OE 1 0 0 Cng IO P23DDR --1 0
P22/TIOCC3/ IRQ10 -A: Chc nng ca chn c chuyn i nh trnh by bng di y thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port 9 (PFCR9), TPU_3, v bit P22DDR. Thit lp TPU_3 Tn module TPU_3 Port I/O Chc nng chn TIOCC3 xut P22 xut P22 nhp(trng thi khi u) TIOCC3_OE 1 0 0 Cng IO P22DDR --1 0
P21/TIOCA3/ IRQ9 -A/ SCS2 : Chc nng ca chn c chuyn i nh trnh by bng di y thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port 9 (PFCR9), SSU_2, TPU_3, v bit P21DDR. Thit lp SSU_2 Tn module Chc nng chn TPU_3 Cng IO
SCS2 _OE TIOCA3_OE P21DDR
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SSU_2 TPU_3 Port I/O
SCS2 xut
1 0 0 0
--1 0 0
----1 0
TIOCA3 xut P21 xut P21 nhp(trng thi khi u)
P20/TIOCA3/TIOCB3/ IRQ8 -A: Chc nng ca chn c chuyn i nh trnh by bng di y thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port 9 (PFCR9), TPU_3, v bit P20DDR. Thit lp TPU_3 Tn module Chc nng chn TPU_3 Port I/O TIOCB3 xut P20 xut P20 nhp(trng thi khi u) 6.2.3 Cng 3 P37/PO15/TIOCA2/TIOCB2/TCLKD: Chc nng ca chn c chuyn i nh trnh by bng di y thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port 9 (PFCR9), TPU_2, PPG (b to xung, chi tit tham kho b to xung), v bit P37DDR. Thit lp TPU_2 Tn module TPU_2 PPG Port I/O Chc nng chn TIOCB2xut PO15 xut P37 xut P37 nhp(trng thi khi u) PPG Cng IO TIOCB3_OE 1 0 0 Cng IO P20DDR --1 0
TIOCB2_OE PO15_OE P37DDR 1 0 0 0 --1 0 0 ----1 0
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P36/PO14/TIOCA2: Chc nng ca chn c chuyn i nh trnh by bng di y thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port 9 (PFCR9), TPU_2, PPG, v bit P36DDR. Thit lp TPU_2 Tn module TPU_2 PPG Port I/O Chc nng chn TIOCA2xut PO14 xut P36 xut P36 nhp(trng thi khi u) PPG Cng IO
TIOCA2_OE PO14_OE P36DDR 1 0 0 0 --1 0 0 ----1 0
P35/PO13/TIOCA1/TIOCB1/TCLKC: Chc nng ca chn c chuyn i nh trnh by bng di y thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port 9 (PFCR9), TPU_1, PPG, v bit P35DDR. Thit lp TPU_1 Tn module TPU_1 PPG Port I/O Chc nng chn TIOCB1xut PO13 xut P35 xut P35 nhp(trng thi khi u) PPG Cng IO
TIOCB1_OE PO13_OE P35DDR 1 0 0 0 --1 0 0 ----1 0
P34/PO12/TIOCA1: Chc nng ca chn c chuyn i nh trnh by bng di y thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port 9 (PFCR9), TPU_1, PPG, v bit P34DDR. Thit lp TPU_1 Tn module TPU_1 Chc nng chn TIOCA1xut PPG Cng IO
TIOCA1_OE PO12_OE P34DDR 1 -----
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PPG Port I/O
PO12 xut P34 xut P34 nhp(trng thi khi u)
0 0 0
1 0 0
--1 0
P33/PO11/TIOCC0/TIOCD0/TCLKB: Chc nng ca chn c chuyn i nh trnh by bng di y thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port 9 (PFCR9), TPU_0, PPG, v bit P33DDR. Thit lp TPU_0 Tn module TPU_0 PPG Port I/O Chc nng chn TIOCD0xut PO11 xut P33 xut P33 nhp(trng thi khi u) PPG Cng IO
TIOCD0_OE PO11_OE P33DDR 1 0 0 0 --1 0 0 ----1 0
P32/PO10/TIOCC0/TCLKA: Chc nng ca chn c chuyn i nh trnh by bng di y thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port 9 (PFCR9), TPU_0, PPG, v bit P32DDR. Thit lp TPU_0 Tn module TPU_0 PPG Port I/O Chc nng chn TIOCC0xut PO10 xut P32 xut P32 nhp(trng thi khi u) PPG Cng IO
TIOCC0_OE PO10_OE P32DDR 1 0 0 0 --1 0 0 ----1 0
P31/PO9/TIOCA0/TIOCB0: Chc nng ca chn c chuyn i nh trnh by bng di y thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port 9 (PFCR9), TPU_0, PPG, v bit P31DDR. Tn Chc nng chn Thit lp
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module
TPU_0
PPG
Cng IO
TIOCB0_OE PO9_OE P31DDR TPU_0 PPG Port I/O TIOCB0xut PO9 xut P31 xut P31 nhp(trng thi khi u) 1 0 0 0 --1 0 0 ----1 0
P30/PO8/TIOCA0: Chc nng ca chn c chuyn i nh trnh by bng di y thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port 9 (PFCR9), TPU_0, PPG, v bit P30DDR. Thit lp TPU_0 Tn module TPU_0 PPG Port I/O Chc nng chn TIOCA0xut PO8 xut P30 xut P30 nhp(trng thi khi u) 6.2.4 Cng 6 P67/ IRQ15 -B: Cc chc nng ca chn c thay i thng qua vic thit lp bit P67DDR. Thit lp Cng IO Tn module Port xut nhp Chc nng chn P67 xut P67DDR 1 PPG Cng IO
TIOCA0_OE PO8_OE P30DDR 1 0 0 0 --1 0 0 ----1 0
P67 nhp (trng thi khi 0 u)
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P66/ IRQ14 -B: Cc chc nng ca chn c thay i thng qua vic thit lp bit P66DDR.
Thit lp Cng IO Tn module Port xut nhp Chc nng chn P66 xut P66DDR 1
P66 nhp (trng thi khi 0 u) P65/ IRQ13 -B/HRxD: Cc chc nng ca chn c thay i thng qua vic thit lp bit P65DDR. Thit lp Cng IO Tn module Port xut nhp Chc nng chn P65 xut P65DDR 1
P65 nhp (trng thi khi 0 u) P64/ IRQ12 -B: Cc chc nng ca chn c thay i thng qua vic thit lp bit P64DDR. Thit lp Cng IO Tn module Port xut nhp Chc nng chn P64 xut P64DDR 1
P64 nhp (trng thi khi 0 u)
P63/ IRQ11 -B: Cc chc nng ca chn c thay i thng qua vic thit lp bit P63DDR.
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Thit lp Cng IO Tn module Port xut nhp Chc nng chn P63 xut P63DDR 1
P63 nhp (trng thi khi 0 u) P62/SCK4/ IRQ10 -B: Cc chc nng ca chn c thay i thng qua vic thit lp bit P62DDR v bit SCI_4. Thit lp SCI_4 Tn module Chc nng chn SCI_4 Port I/O SCK4 xut P62 xut P62 nhp(trng thi khi u) SCK4_OE 1 0 0 Cng I/O P62DDR --1 0
P61/RxD4/ IRQ9 -B: Cc chc nng ca chn c thay i thng qua vic thit lp bit P61DDR. Thit lp Cng IO Tn module Port xut nhp Chc nng chn P61 xut P61DDR 1
P61 nhp (trng thi khi 0 u) P60/TxD4/ IRQ8 -B: Cc chc nng ca chn c thay i thng qua vic thit lp bit P60DDR v bit SCI_4. Thit lp Tn module Chc nng chn SCI_4 Cng I/O
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TxD4_OE SCI_4 Port I/O TxD4 xut P60 xut P60 nhp(trng thi khi u) 6.2.5 Cng A 1 0 0
P60DDR --1 0
PA7: Chc nng ca chn c thay i thng qua vic thit lp bit PA7DDR. Thit lp Cng IO Tn module Port xut nhp Chc nng chn B xut PA7DDR 1
PA7 nhp (trng thi khi 0 u) PA6: Chc nng ca chn c thay i thng qua vic thit lp bit PA6DDR. Thit lp Cng IO Tn module Port xut nhp Chc nng chn PA6 xut PA6DDR 1
PA6 nhp (trng thi khi 0 u) PA5: Chc nng ca chn c thay i thng qua vic thit lp bit PA5DDR. Thit lp Cng IO Tn module Port xut nhp Chc nng chn PA5 xut PA5DDR 1
PA5 nhp (trng thi khi 0 u)
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PA4: Chc nng ca chn c thay i thng qua vic thit lp bit PA4DDR. Thit lp Cng IO Tn module Port xut nhp Chc nng chn PA4 xut PA4DDR 1
PA4 nhp (trng thi khi 0 u) PA3/SSO2: Chc nng ca chn c thay i thng qua vic thit lp bit PA3DDR v bit SSU_2. Thit lp SSU_2 Tn module SSU_2 Port I/O Chc nng chn SSO2 xut PA3 xut PA3 nhp(trng thi khi u) SSO2_OE 1 0 0 PA3DDR --1 0
PA2/SSI2: Chc nng ca chn c thay i thng qua vic thit lp bit PA2DDR v bit SSU_2. Thit lp SSU_2 Tn module SSU_2 Port I/O Chc nng chn SSI2 xut PA2 xut PA2 nhp(trng thi khi u) SSI2_OE 1 0 0 Cng IO PA2DDR --1 0
PA1/SSCK2: Chc nng ca chn c thay i thng qua vic thit lp bit PA1DDR v bit SSU_2. Thit lp Tn module Chc nng chn SSU_2 Cng IO
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SSCK2_OE SSU_2 Port I/O SSCK2xut PA1 xut PA1 nhp(trng thi khi u) 1 0 0
PA1DDR --1 0
PA0: Chc nng ca chn c thay i thng qua vic thit lp bit PA0DDR. Thit lp Cng IO Tn module Port xut nhp Chc nng chn PA0 xut PA0 nhp (trng thi khi u) 6.2.6 Cng B PB2: Chc nng ca chn c thay i thng qua vic thit lp bit PB2DDR. Thit lp Cng IO Tn module Port xut nhp Chc nng chn PB2 xut PB2 nhp (trng thi khi u) PB2DDR 1 0 PA0DDR 1 0
PB1: Chc nng ca chn c thay i thng qua vic thit lp bit PB1DDR. Thit lp Cng IO Tn module Port xut nhp Chc nng chn PB1 xut PB1 nhp (trng thi khi u) PB1DDR 1 0
PB0: Chc nng ca chn c thay i thng qua vic thit lp bit PB0DDR.
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Thit lp Cng IO Tn module Port xut nhp Chc nng chn PB0 xut PB0 nhp (trng thi khi u) 6.2.7 Cng D PD7/ SCS1 : Chc nng ca chn c thay i thng qua vic thit lp bit PD7DDR v bit SSU_1 (n v giao tip tun t ng b). Thit lp SSU_1 Tn module SSU_1 Port I/O Chc nng chn
SCS1 xut SCS1 _OE
PB0DDR 1 0
Cng IO PD7DDR --1 0
1 0 0
PD7 xut PD7 nhp(trng thi khi u)
PD6/ SSCK1: Chc nng ca chn c thay i thng qua vic thit lp bit PD6DDR v bit SSU_1. Thit lp SSU_1 Tn module SSU_1 Port I/O Chc nng chn SSCK1 xut PD6 xut PD6 nhp(trng thi khi u) SSCK1_OE 1 0 0 Cng IO PD6DDR --1 0
PD5/ SSI1: Chc nng ca chn c thay i thng qua vic thit lp bit PD5DDR v bit SSU_1. Tn module Chc nng chn Thit lp
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SSU_1 SSI1_OE SSU_1 Port I/O SSI1xut PD5 xut PD5 nhp(trng thi khi u) 1 0 0
Cng IO PD5DDR --1 0
PD4/ SSO1: Chc nng ca chn c thay i thng qua vic thit lp bit PD4DDR v bit SSU_1. Thit lp SSU_1 Tn module SSU_1 Port I/O Chc nng chn SSO1 xut PD4 xut PD4 nhp(trng thi khi u) SSO1_OE 1 0 0 Cng IO PD4DDR --1 0
PD3/ SCS0 : Chc nng ca chn c thay i thng qua vic thit lp bit PD3DDR v bit SSU_0. Thit lp SSU_0 Tn module SSU_0 Port I/O Chc nng chn
SCS0 xut SCS0 _OE
Cng IO PD3DDR --1 0
1 0 0
PD3 xut PD3 nhp(trng thi khi u)
PD2/SSCK0: Chc nng ca chn c thay i thng qua vic thit lp bit PD2DDR v bit SSU_0. Thit lp SSU_0 Tn module Chc nng chn SSCK0_OE Cng IO PD2DDR
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SSU_0 Port I/O
SSCK0 xut PD2 xut PD2 nhp(trng thi khi u)
1 0 0
--1 0
PD1/SSI0: Chc nng ca chn c thay i thng qua vic thit lp bit PD1DDR v bit SSU_0. Thit lp SSU_0 Tn module SSU_0 Port I/O Chc nng chn SSI0 xut PD1 xut PD1 nhp(trng thi khi u) SSI0_OE 1 0 0 Cng IO PD1DDR --1 0
PD0/SSO0: Chc nng ca chn c thay i thng qua vic thit lp bit PD0DDR v bit SSU_0. Thit lp SSU_0 Tn module SSU_0 Port I/O Chc nng chn SSO0 xut PD0 xut PD0 nhp(trng thi khi u) 6.2.8 Cng H PH7, PH6, PH5, PH4, PH3, PH2, PH1, v PH0: Port H thc hin chc nng nh mt port xut nhp 8-bit, n cng c vai tr nh mt port nhp thi gian thc (realtime). Vic s dng port H nh mt cng nhp thi gian thc, th cc trng thi chn ca port H c lu trong thanh ghi PHRTIDR bi cc kch xung sau: mt trng thi thp, mt cnh xung, mt cnh ln, hay c hai cnh ca chn IRQ14. Chc nng chn c chuyn i thng qua vic thit lp bit PHnDDR. Tn module Chc nng chn Thit lp SSO0_OE 1 0 0 Cng IO PD0DDR --1 0
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Cng IO PHnDDR Port xut nhp PHn xut PHn nhp (trng thi khi u) Ghi ch n = 0 n 7 6.2.10 Cng J PJ7/TIOCA8/TIOCB8/TCLKH: Chc nng ca chn c thay i thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port A, TPU_8, v bit PJ7DDR Thit lp TPU_8 Tn module TPU_8 Port I/O Chc nng chn TIOCB8 xut PJ7 xut PJ7 nhp(trng thi khi u) TIOCB8_OE 1 0 0 Cng I/O PJ7DDR --1 0 1 0
PJ6/TIOCA8: Chc nng ca chn c thay i thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port A, TPU_8, v bit PJ6DDR Thit lp TPU_8 Tn module TPU_8 Port I/O Chc nng chn TIOCA8 xut PJ6 xut PJ6 nhp(trng thi khi u) TIOCA8_OE 1 0 0 Cng I/O PJ6DDR --1 0
PJ5/TIOCA7/TIOCB7/TCLKG: Chc nng ca chn c thay i thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port A, TPU_7, v bit PJ5DDR Tn module Chc nng chn Thit lp
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TPU_7 TIOCB7_OE TPU_7 Port I/O TIOCB7 xut PJ5 xut PJ5 nhp(trng thi khi u) 1 0 0
Cng I/O PJ5DDR --1 0
PJ4/TIOCA7: Chc nng ca chn c thay i thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port A, TPU_7, v bit PJ4DDR Thit lp TPU_7 Tn module TPU_7 Port I/O Chc nng chn TIOCA7 xut PJ4 xut PJ4 nhp(trng thi khi u) TIOCA7_OE 1 0 0 Cng I/O PJ4DDR --1 0
PJ3/TIOCC6/TIOCD6/TCLKF: Chc nng ca chn c thay i thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port A, TPU_6, v bit PJ3DDR Thit lp TPU_6 Tn module TPU_6 Port I/O Chc nng chn TIOCD6 xut PJ3 xut PJ3 nhp(trng thi khi u) TIOCD6_OE 1 0 0 Cng I/O PJ3DDR --1 0
PJ2/TIOCC6/TCLKE: Chc nng ca chn c thay i thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port A, TPU_6, v bit PJ2DDR Thit lp Tn module Chc nng chn TPU_6 Cng I/O
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TIOCC6_OE TPU_6 Port I/O TIOCC6 xut PJ2 xut PJ2 nhp(trng thi khi u) 1 0 0
PJ2DDR --1 0
PJ1/TIOCA6/TIOCB6: Chc nng ca chn c thay i thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port A, TPU_6, v bit PJ1DDR Thit lp TPU_6 Tn module TPU_6 Port I/O Chc nng chn TIOCB6 xut PJ1 xut PJ1 nhp(trng thi khi u) TIOCB6_OE 1 0 0 Cng I/O PJ1DDR --1 0
PJ0/TIOCA6: Chc nng ca chn c thay i thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port A, TPU_6, v bit PJ0DDR Thit lp TPU_6 Tn module TPU_6 Port I/O Chc nng chn TIOCA6 xut PJ0 xut PJ0 nhp(trng thi khi u) 6.2.11 Cng K PK7/TIOCA11/TIOCB11: Chc nng ca chn c thay i thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port A, TPU_11, v bit PK7DDR Thit lp TPU_11 Tn module Chc nng chn TIOCB11_OE Cng I/O PK7DDR TIOCA6_OE 1 0 0 Cng I/O PJ0DDR --1 0
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TPU_11 Port I/O
TIOCB11 xut PK7 xut
1 0
--1 0
PK7 nhp(trng thi khi u) 0
PK6/TIOCA11: Chc nng ca chn c thay i thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port A, TPU_11, v bit PK6DDR Thit lp TPU_11 Tn module TPU_11 Port I/O Chc nng chn TIOCA11 xut PK6 xut TIOCA11_OE 1 0 Cng I/O PK6DDR --1 0
PK5/TIOCA10/TIOCB10: Chc nng ca chn c thay i thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port A, TPU_10, v bit PK5DDR Thit lp TPU_10 Tn module TPU_10 Port I/O Chc nng chn TIOCB10 xut PK5 xut TIOCB10_OE 1 0 Cng I/O PK5DDR --1 0
PK4/TIOCA10: Chc nng ca chn c thay i thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port A, TPU_10, v bit PK4DDR Thit lp TPU_10 Tn module TPU_10 Port I/O Chc nng chn TIOCA10 xut PK4 xut TIOCA10_OE 1 0 Cng I/O PK4DDR --1
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PK4 nhp(trng thi khi u)
PK3/TIOCC9/TIOCD9: Chc nng ca chn c thay i thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port A, TPU_9, v bit PK3DDR Thit lp TPU_9 Tn module TPU_9 Port I/O Chc nng chn TIOCD9 xut PK3 xut TIOCD9_OE 1 0 Cng I/O PK3DDR --1 0
PK2/TIOCC9: Chc nng ca chn c thay i thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port A, TPU_9, v bit PK2DDR Thit lp TPU_9 Tn module TPU_9 Port I/O Chc nng chn TIOCC9 xut PK2 xut TIOCC9_OE 1 0 Cng I/O PK2DDR --1 0
PK1/TIOCA6/TIOCB6: Chc nng ca chn c thay i thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port A, TPU_9, v bit PK1DDR Thit lp TPU_9 Tn module TPU_9 Port I/O Chc nng chn TIOCB6 xut PK1 xut TIOCB6_OE 1 0 Cng I/O PK1DDR --1 0
PK0/TIOCA9: Chc nng ca chn c thay i thng qua s kt hp ca vic thit lp thanh ghi iu khin chc nng port A, TPU_9, v bit PK0DDR
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Thit lp TPU_9 Tn module TPU_9 Port I/O Chc nng chn TIOCA9 xut PK0 xut PK0 nhp(trng thi khi u) TIOCA9_OE 1 0 0 Cng I/O PK0DDR --1 0
Bng 6.4 Cc tn hiu xut hp l v vic thit lp cho mi cng Cng Tn tn hiu c t xut 1 Tn tn hiu xut Thit lp thanh ghi la chn tn hiu Thit lp module ngoi vi
P3
TIOCB0_ TIOCB OE 0
TPU.TIORH_0.IOB3 = 0, TPU.TIORH_0.IOB[1,0] = 01/10/11
PO9_OE 0 TIOCA0 _OE
PO9 TIOCA 0
NDERH.NDER9 = 1 TPU.TIORH_0.IOA3 = 0, TPU.TIORH_0.IOA[1,0] = 01/10/11
PO8_OE P6 2 SCK4_O E
PO8 SCK4
NDERH.NDER8 = 1 Khi SCMR_4.SMIF = 1: SCR_4.TE = 1 hay SCR_4.RE = 1 khi SMR_4.GM = 0, SCR_4.CKE [1, 0] = 01 hay khi SMR_4.GM = 1 Khi SCMR_4.SMIF = 0: SCR_4.TE = 1 hay SCR_4.RE = 1 khi SMR_4.C/A = 0, SCR_4.CKE [1, 0] = 01 hay khi SMR_4.C/A = 1, SCR_4.CKE 1 = 0
143
0 PA 7
TxD4_O E B _OE
TxD4 B
SCR.TE = 1 PADDR.PA7DDR = 1, SCKCR.PSTOP1 = 0, SCKCR.POSEL1 = 0
SSO2_O E
SSO2
Khi SSU.SSCRL_2.SSUMS = 0, SSU.SSCRH_2.MSS = 1: SSU.SSCRH_2.BIDE = 0, SSU.SSER_2.TE = 1 hay SSU.SSCRH_2.BIDE = 1, SSU.SSER_2.RE = 0, SSU.SSER_2.TE = 1 Khi SSU.SSCRL_2.SSUMS = 0, SSU.SSCRH_2.MSS = 0: SSU.SSCRH_2.BIDE = 1, SSU.SSER_2.RE = 0, SSU.SSER_1.TE = 1 Khi SSU.SSCRL_2.SSUMS = 1: SSU.SSER_2.TE = 1
SSI2_OE
SSI2
SSU.SSCRL_2SSUMS = 0, SSU.SSCRH_2.MSS = 0 SSU.SSCRH_2.BIDE = 0, SSU.SSER_2.TE = 1
1 PD 7
SSCK2_ OE
SCS1 _O
SSCK2
SSU.SSCRH_2.MSS = 1, SSU.SSCRH_2.SCKS = 1 SSU.SSCRH_0.CSS1 = 1, SSU.SSCRH_0.CSS0 = 0 hay SSU.SSCRH_0.CSS1 = 1, SSU.SSCRH_0.CSS0 = 1 khi SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 1
SCS1
SSCK1_ OE
SSCK1
SSU.SSCRH_1.MSS = 1, SSU.SSCRH_1.SCKS = 1
144
SSI1_OE
SSI1
SSU.SSCRL_1.SSUMS = 0, SSU.SSCRH_1.MSS = 0 SSU.SSCRH_1.BIDE = 0, SSU.SSER_1.TE = 1
SSO1_O E
SSO1
Khi SSU.SSCRL_1.SSUMS = 0, SSU.SSCRH_1.MSS = 1: SSU.SSCRH_1.BIDE = 0, SSU.SSER_1.TE = 1 hay SSU.SSCRH_1.BIDE = 1, SSU.SSER_1.RE = 0, SSU.SSER_1.TE = 1 Khi SSU.SSCRL_1.SSUMS = 0, SSU.SSCRH_1.MSS = 0: SSU.SSCRH_1.BIDE = 1, SSU.SSER_1.RE = 0, SSU.SSER_1.TE = 1 Khi SSU.SSCRL_1.SSUMS = 1: SSU.SSER_1.TE = 1
SCS0 _O
SCS0
SSU.SSCRH_0.CSS1 = 1, SSU.SSCRH_0.CSS0 = 0 hay SSU.SSCRH_0.CSS1 = 1, SSU.SSCRH_0.CSS0 = 1 khi SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 1
2 1
SSCK0_ O SSI0_OE
SSCK0 SSI0
SSU.SSCRH_0.MSS = 1, SSU.SSCRH_0.SCKS = 1 SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 0 SSU.SSCRH_0.BIDE = 0, SSU.SSER_0.TE = 1
SSO0_O E
SSO0
Khi SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 1: SSU.SSCRH_0.BIDE = 0, SSU.SSER_0.TE = 1 hay SSU.SSCRH_0.BIDE = 1,
145
SSU.SSER_0.RE = 0, SSU.SSER_0.TE = 1 Khi SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 0: SSU.SSCRH_0.BIDE = 1, SSU.SSER_0.RE = 0, SSU.SSER_0.TE = 1 Khi SSU.SSCRL_0.SSUMS = 1: SSU.SSER_0.TE = 1 PJ 7 6 5 4 3 TIOCB8_ TIOCB OE 8 TIOCA8 _OE TIOCA 8 TPU.TIOR_8.IOB3 = 0, TPU.TIOR_8.IOB[1, 0] = 01/10/11 TPU.TIOR_8.IOA3 = 0, TPU.TIOR_8.IOA[1, 0] = 01/10/11 TPU.TIOR_7.IOB3 = 0, TPU.TIOR_7.IOB[1, 0] = 01/10/11 TPU.TIOR_7.IOA3 = 0, TPU.TIOR_7.IOA[1, 0] = 01/10/11 TPU.TMDR_6.BFB = 0, TPU.TIORL_6.IOD3 = 0 TPU.TIORL_6.IOD[1, 0] = 01/10/11 2 TIOCC6_ TIOCC OE 6 TPU.TMDR_6.BFA = 0, TPU.TIORL_6.IOC3 = 0 TPU.TIORL_6.IOC[1, 0] = 01/10/11 1 0 PK 7 6 5 TIOCB6_ TIOCB OE 6 TIOCA6 _OE TIOCA 6 TPU.TIORH_6.IOB3 = 0, TPU.TIORH_6.IOB[1, 0] = 01/10/11 TPU.TIORH_6.IOA3 = 0, TPU.TIORH_6.IOA[1, 0] = 01/10/11 TPU.TIOR_11.IOB3 = 0, TPU.TIOR_11.IOB[1, 0] = 01/10/11 TPU.TIOR_11.IOA3 = 0, TPU.TIOR_11.IOA[1, 0] = 01/10/11 TPU.TIOR_10.IOB3 = 0, TPU.TIOR_10.IOB[1, 0] = 01/10/11
146
TIOCB7_ TIOCB OE 7 TIOCA7 _OE TIOCD6 _OE TIOCA 7 TIOCD 6
TIOCB11 TIOCB _OE 11 TIOCA1 1_OE TIOCA 11
TIOCB10 TIOCB _OE 10
4 3
TIOCA1 0_OE TIOCD9 _OE
TIOCA 10 TIOCD 9
TPU.TIOR_10.IOA3 = 0, TPU.TIOR_10.IOA[1, 0] = 01/10/11 TPU.TMDR_9.BFB = 0, TPU.TIORL_9.IOD3 = 0 TPU.TIORL_9.IOD[1, 0] = 01/10/11
TIOCC9_ TIOCC OE 9
TPU.TMDR_9.BFA = 0, TPU.TIORL_9.IOC3 = 0 TPU.TIORL_9.IOC[1, 0] = 01/10/11
1 0
TIOCB9_ TIOCB OE 9 TIOCA9 _OE TIOCA 9
TPU.TIOR_9.IOB3 = 0, TPU.TIOR_9.IOB[1, 0] = 01/10/11 TPU.TIOR_9.IOA3 = 0, TPU.TIOR_9.IOA[1, 0] = 01/10/11
6.3 B iu khin chc nng ca cng

B iu khin chc nng port iu khin cc port xut nhp B iu khin chc nng port kt hp cht ch cc thanh ghi sau: Thanh ghi iu khin chc nng port 9 (PFCR9) Thanh ghi iu khin chc nng port A (PFCRA) Thanh ghi iu khin chc nng port B (PFCRB) 6.3.1 Thanh ghi iu khin chc nng cng 9 (PFCR9) Thanh ghi PFCR9 la chn nhiu chc nng cho cc chn xut nhp TPU (n v 0).
Bit
Tn Bit
Gi tr khi u 0
R/W
c t
TPUMS5
R/W
La chn chc nng cho chn a nng. La chn chc nng TIOCA5 0: chn P27 (bit 7 ca port 2) s dng vi chc nng xut output compare v nhp input capture 1: Chn P27 c s dng vi chc nng nhp tn hiu input capture v P26 s dng vi chc nng 147
xut output compare. 6 TPUMS4 0 R/W La chn chc nng cho chn a nng. La chn chc nng TIOCA4 0: chn P25 (bit 5 ca port 2) s dng vi chc nng xut output compare v nhp input capture 1: Chn P24 c s dng vi chc nng nhp tn hiu input capture v P25 s dng vi chc nng xut output compare. 5 TPUMS3 A 0 R/W La chn chc nng cho chn a nng. La chn chc nng TIOCA3 0: chn P21 (bit 1 ca port 2) s dng vi chc nng xut output compare v nhp input capture 1: Chn P21 c s dng vi chc nng nhp tn hiu input capture v P20 s dng vi chc nng xut output compare. 4 TPUMS3 B 0 R/W La chn chc nng cho chn a nng. La chn chc nng TIOCC3 0: chn P22 (bit 2 ca port 2) s dng vi chc nng xut output compare v nhp input capture 1: Chn P23 c s dng vi chc nng nhp tn hiu input capture v P22 s dng vi chc nng xut output compare. 3 TPUMS2 0 R/W La chn chc nng cho chn a nng. La chn chc nng TIOCA2 0: chn P36 (bit 6 ca port 3) s dng vi chc nng xut output compare v nhp input capture 1: Chn P37 c s dng vi chc nng nhp tn hiu input capture v P36 s dng vi chc nng xut output compare. 2 TPUMS1 0 R/W La chn chc nng cho chn a nng. La chn chc nng TIOCA1 0: chn P34 (bit 4 ca port 3) s dng vi chc nng xut output compare v nhp input capture 1: Chn P35 c s dng vi chc nng nhp tn hiu input capture v P34 s dng vi chc nng xut output compare. 1 TPUMS0 0 R/W TPU I/O Pin Multiplex Function Select
148
Selects TIOCA0 function 0: Specifies P30 as output compare output and input capture 1: Specifies P31 as input capture input and P30 as output compare
TPUMS0 B
R/W
La chn chc nng cho chn a nng. La chn chc nng TIOCC0 0: chn P32 (bit 2 ca port 3) s dng vi chc nng xut output compare v nhp input capture 1: Chn P33 c s dng vi chc nng nhp tn hiu input capture v P32 s dng vi chc nng xut output compare.
6.3.2 Thanh ghi iu khin chc nng cng A (PFCRA)
Thanh ghi PFCRA la chn nhiu chc nng cho cc chn xut nhp TPU (n v 1).
Bit Tn Bit Gi tr R/W c t khi u 0 R/W La chn chc nng cho chn a nng. La chn chc nng TIOCA11 0: chn PK6 (bit 6 ca port K) s dng vi chc nng xut output compare v nhp input capture 1: Chn PK7 c s dng vi chc nng nhp tn hiu input capture v PK6 s dng vi chc nng xut output compare. 6 TPUMS10 0 R/W La chn chc nng cho chn a nng. La chn chc nng TIOCA10 0: chn PK4 (bit 4 ca port K) s dng vi chc nng xut output compare v nhp input capture 1: Chn PK5 c s dng vi chc nng nhp tn hiu input capture v PK4 s dng vi chc nng xut output compare.
TPUMS11
149
TPUMS9A 0
R/W
La chn chc nng cho chn a nng. La chn chc nng TIOCA9 0: chn PK0 (bit 0 ca port K) s dng vi chc nng xut output compare v nhp input capture 1: Chn PK1 c s dng vi chc nng nhp tn hiu input capture v PK0 s dng vi chc nng xut output compare.
TPUMS9B 0
R/W
La chn chc nng cho chn a nng. La chn chc nng TIOCC9 0: chn PK2 (bit 2 ca port K) s dng vi chc nng xut output compare v nhp input capture 1: Chn PK3 c s dng vi chc nng nhp tn hiu input capture v PK2 s dng vi chc nng xut output compare.
TPUMS8
R/W
La chn chc nng cho chn a nng. La chn chc nng TIOCA8 0: chn PJ6 (bit 6 ca port J) s dng vi chc nng xut output compare v nhp input capture 1: Chn PJ7 c s dng vi chc nng nhp tn hiu input capture v PJ6 s dng vi chc nng xut output compare.
TPUMS7
R/W
TPUMS6A 0
R/W
TPUMS6B 0
R/W
La chn chc nng cho chn a nng. La chn chc nng TIOCC6
150
0: chn PJ2 (bit 2 ca port J) s dng vi chc nng xut output compare v nhp input capture 1: Chn PJ3 c s dng vi chc nng nhp tn hiu input capture v PJ2 s dng vi chc nng xut output compare.
6.3.3 Thanh ghi iu khin chc nng cng B (PFCRB) Thanh ghi PFCRB la chn cc chn nhp cho IRQ15 v IRQ8
Bit 7
Tn Bit ITS15
Gi tr khi u 0
R/W R/W
c t La chn mt chn nhp ca IRQ15 0: Chn P27 khng thc hin chc nng l mt port nhp IRQ15 -A 1: Chn P67 c s dng l port nhp IRQ15 - B
ITS14
R/W
La chn mt chn nhp ca IRQ14 0: Chn P26 khng thc hin chc nng l mt port nhp IRQ14 -A 1: Chn P66 c s dng l port nhp IRQ14 - B
ITS13
R/W
ITS12
R/W
ITS11
R/W
La chn mt chn nhp ca IRQ11 0: Chn P23 khng thc hin chc nng l mt port
151
nhp IRQ11 -A 1: Chn P63 c s dng l port nhp IRQ11 - B 2 ITS10 0 R/W La chn mt chn nhp ca IRQ10 0: Chn P22 khng thc hin chc nng l mt port nhp IRQ10 -A 1: Chn P62 c s dng l port nhp IRQ10 - B 1 ITS9 0 R/W La chn mt chn nhp ca IRQ9 0: Chn P21 khng thc hin chc nng l mt port nhp IRQ9 -A 1: Chn P61 c s dng l port nhp IRQ9 - B 0 ITS8 0 R/W La chn mt chn nhp ca IRQ8 0: Chn P20 khng thc hin chc nng l mt port nhp IRQ8 -A 1: Chn P60 c s dng l port nhp IRQ8 - B
6.4 Cc ch cch s dng

6.4.1 Cc ch v vic thit lp thanh ghi iu khin buffer nhp (ICR) Khi thit lp ca thanh ghi ICR b thay i, th vi iu khin ny c th gp s c bi mt xung tn hiu c pht ra thng qua cc trng thi ca chn. thay i s thit lp ca thanh ghi ICR, th phi c nh chn mc cao hay v hiu ha chc nng nhp tng ng vi chn bng cch thit lp cc thanh ghi module trn chip. Nu mt tn hiu nhp c cho php bng cch thit lp thanh ghi ICR trong khi nhiu chc nng nhp c p vo chn, th cc trng thi ca chn s c phn hi trong tt c cc tn hiu nhp ca cc module khc nhau. Phi cn thn v vic thit lp cc chc nng nhp khng c s dng trn mi module. Khi mt chn c s dng vi vai tr l mt port xut, th d liu xut t chn ny s b cht li nh l trng thi ca chn nu chc nng nhp ca chn ny c cho php. s dng chn vi vai tr l port xut, th nn cm chc nng nhp cho chn ny bng vic thit lp ICR 6.4.2 Cc ch trong vic thit lp thanh ghi iu khin chc nng cng (PFCR) PFC iu khin cc port xut nhp. ch nh chc nng ca mi chn, la
152
chn chc nng cho n trc khi thit lp chc nng xut hay nhp. Khi chc nng b thay i bi cc bit tng ng, mt cnh xung s xy ra nu mc tn hiu trc ca chn khc vi mc tn hiu ca chn sau khi thay i. thay i chc nng chn mt cch trc tip th thc hin theo quy trnh sau: o Tt chc nng nhp ca chn tng ng o La chn chc nng nhp bng vic thit lp thanh ghi PFCR o M chc nng nhp cho chn Nu mt chn c c bt la chn chc nng v bit la chn xut nhp th u tin l la chn chc nng trc, sau mi la chn xut nhp cho chn.
153
Chng 7 B nh thi 16-bit (TPU)

Vi iu khin ny c 2 b nh thi 16-bit trn chip: l b nh thi 0 (unit 0) v b nh thi 1 (unit 1). Mi b nh thi gm c 6 knh b m 16-bit, v vy m vi iu khin c n tng cng 12 knh m. Bng 7.1 s cho thy cu hnh b m cho mi sn phm.Bng 12 l tp hp cc chc nng v hnh v 7.1 l mt s khi cho b nh thi 0. Bng 7.3 v hnh 7.2 l cho b nh thi 1. Phn ny s c t b nh thi 0, b nh thi m c cng chc nng vi b nh thi cn li
7.1 Cc tnh cht

Xut/nhp n 16-xung La chn ca 8 b m xung clocl nhp cho mi knh Cc thao tc sau c th c thit lp cho mi knh: o Xut dng sng cho tn hiu compare match o Chc nng input capture o Tc v xa b m o Cc tc v ng b ha: Nhiu b m c th c ghi mt cch ng thi Vic xa mt cch ng thi bi compare match v input capture C th xut nhp ng thi cho cc thanh ghi bi tc v ng b ha b m Ti a c th xut n 15-phase PWM bng s kt hp vi hot ng ng b ha C th thit lp hot ng buffer cho cc knh 0 v 3 C th thit lp ch m phase mt cch c lp cho cc knh 1, 2, 4, v 5 Hot ng cascaded Truy xut nhanh thng qua bus ni 16-bit C 26 ngun ngt B truyn d liu t ng B to xung c th lp trnh c PPG B chuyn i A/D c th c kch hot (ch h tr vi b nh thi 0) Ch dng module c th c thit lp Bng 7.1 Cu hnh b m cho mi sn phm
154
Sn phm H8SX/1582
Cu hnh b nh thi B nh thi 0 (unit 0) B nh thi 1 (unit 1)
Cu hnh knh knh 0 n knh 5 knh 6 n knh 11
Bng 7.2 Cc chc nng ca TPU (b nh thi 0)

Item ng h m knh 0 P /1 P /4 P /16 P /64 TCLKA TCLKB TCLKC TCLKD Cc thanh ghi a nng (TGR) Cc thanh ghi a nng/cc thanh ghi b m Cc chn xut /nhp TGRA_0 TGRB_0 TGRC_0 TGRD_0 TGRA_1 TGRB_1 --knh 1 P /1 P /4 P /16 P /64 P /256 TCLKA TCLKB knh 2 P /1 P /4 P /16 P /64 P /1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 --knh 3 P /1 P /4 P /16 P /64 P /256 P /1024 P /4096 TCLKA TGRA_3 TGRB_3 TGRC_3 TGRD_3 TGRA_4 TGRB_4 --knh 4 P /1 P /4 P /16 P /64 P /1024 TCLKA TCLKC knh 5 P /1 P /4 P /16 P /64 P /256 TCLKA TCLKC TCLKD TGRA_5 TGRB_5 ---
TIOCA0 TIOCB0 TIOCC0 TIOCD0
TIOCA1 TIOCB1
TIOCA2 TIOCB2
TIOCA4 TIOCB4
TIOCA5 TIOCB5
Chc nng xa b m
TGR compare match/ input capture
TGR compare match/ input capture O O
TGR compare match / input capture O O
So sn h
Xut 0 Xut 1
O O
155
ng xut
o tn hiu xut
Chc nng gi O tn hiu nhp Tc v ng b ha Ch PWM Ch m pha Tc v buffer S kch hot DTC O O --O TGR compare match/ input capture S kch hot DMAC TGRA_0 compare match/ input capture Trnh chuyn i A/D TGRA_0 compare match / input capture PPG trigger TGRA_0 / TGRB_0 compare match / input capture
O O O O --TGR compare match/ input capture TGRA_1 compare match/ input capture TGRA_1 compare match / input capture TGRA_1/ TGRB_1 compare match / input capture
O O O O --TGR compare match/ input capture TGRA_2 compare match/ input capture TGRA_2 compare match / input capture TGRA_2/ TGRB_2 compare match / input capture
O O O --O TGR compare match/ input capture TGRA_3 compare match/ input capture TGRA_3 compare match / input capture TGRA_3 / TGRB_3 compare match / input capture
O O O O --TGR compare match/ input capture TGRA_4 compare match/ input capture TGRA_4 compare match / input capture ---
O O O O --TGR compare match/ input capture TGRA_5 compare match/ input capture TGRA_5 compare match / input capture ---
156
Cc ngun ngt
5 sources: 1.Compa re match / input capture 0A 2.Compa re match / input capture 0B 3.Compa re match / input capture 0C 4.Compa re match / input capture 0D 5.Overfl ow
4 sources: 1.Compar e match / input capture 1A 2.Compar e match / input capture 1B 3.Overflo w 4.Underfl ow
4 sources 1.Compar e match / input capture 2A 2.Compar e match / input capture 2B 3.Overflo w 4.Underfl ow
5 sources 4 sources 4 sources : : : 1.Compa re match / input capture 3A 2.Compa re match / input capture 3B 3.Compa re match / input capture 3C 4.Compa re match / input capture 3D 5.Overflo w 1.Compar e match / input capture 4A 2.Compar e match / input capture 4B 3.Overflo w 4.Underfl ow 1.Compar e match / input capture 5A 2.Compar e match / input capture 5B 3.Overflo w 4.Underfl ow
Ghi ch: O: C th thc hin c --- : khng th thc hin c Bng 7.2 Cc chc nng ca TPU (b nh thi 1)
Item Xung ng h m knh 6 P /1 knh 7 P /1 knh 8 P /1 knh 9 P /1 knh 10 P /1 knh 11 P /1
157
P /4 P /16 P /64 TCLKE TCLKF TCLKG TCLKH Cc thanh ghi a nng (TGR) TGRA_6 TGRB_6
P /4 P /16 P /64 P /256 TCLKE TCLKF
P /4 P /16 P /64 P /1024 TCLKE TCLKF TCLKG
P /4 P /16 P /64 P /256 P /1024 P /4096 TCLKE TGRA_9 TGRB_9 TGRC_9 TGRD_9
P /4 P /16 P /64 P /1024 TCLKE TCLKG
P /4 P /16 P /64 P /256 TCLKE TCLKG TCLKH
TGRA_7 TGRB_7 ---
TGRA_8 TGRB_8 ---
TGRA_10 TGRA_11 TGRB_10 TGRB_11 -----
Cc thanh ghi TGRC_6 a nng/cc TGRD_6 thanh ghi buffer Cc chn xut /nhp TIOCA6 TIOCB6 TIOCC6 TIOCD6 Chc nng xa b m TGR compare match hay input capture So snh ng xut Xut 0 Xut 1 o tn hiu xut O O O
TIOCA7 TIOCB7
TIOCA8 TIOCB8
TIOCA10 TIOCB10
TIOCA11 TIOCB11
TGR compare
TGR compare
TGR compare
TGR compare input capture O O O
TGR compare input capture O O O
match hay match hay match hay input input capture O O O capture O O O input capture O O O
match hay match hay
Chc nng gi O tn hiu nhp Tc v ng O
O O
O O
O O
O O
O O
158
b ha Ch PWM Ch m giai on Tc v buffer S kch hot DTC O --O TGR compare match / input capture S kch hot DMAC TGRA_6 compare match / input capture Cc ngun ngt O O --TGR compare match / input capture TGRA_7 compare match / input capture O O --TGR compare match / input capture TGRA_8 compare match / input capture 4 sources 1.Compar e match / input capture 8A 2.Compar e match / input capture 8B 3.Overflo w 4.Underfl ow O --O TGR compare match / input capture TGRA_9 compare match / input capture 5 sources 1.Compa re match / input capture 9A 2.Compa re match / input capture 9B 3.Compa re match / input capture 9C 4.Compa 159 O O --TGR compare match / input capture O O --TGR compare match / input capture
TGRA_10 TGRA_11 compare match / input capture 4 sources 1.Compar e match / input capture 10A 2.Compar e match / input capture 10B 3.Overflo w 4.Underfl ow compare match / input capture 4 sources 1.Compar e match / input capture 11A 2.Compar e match / input capture 11B 3.Overflo w 4.Underfl ow
5 sources 4 sources 1.Compa re match / input capture 6A 2.Compa re match / input capture 6B 3.Compa re match / input capture 6C 4.Compa 1.Compar e match / input capture 7A 2.Compar e match / input capture 7B 3.Overflo w 4.Underfl ow
re match / input capture 6D 5.Overfl ow
re match / input capture 9D 5.Overflo w
Ghi ch: O: C th thc hin c --- : khng th thc hin c
160
Hnh 7.1 S khi ca TPU (b nh thi 0)
161
Hnh 7.2 S khi ca TPU (b nh thi 1)
7.2 Cc chn xut nhp

Bng 7.3 Cu hnh cc chn
B nh thi (unit) Knh K hiu Xut nhp Chc nng
162
Tt c
TCLKA
Nhp
Chn nhp xung ng h ngoi A (Tn hiu nhp A-phase cho ch m phase ca knh 1 v 5)
TCLKB
Nhp
Chn nhp xung ng h ngoi B (Tn hiu nhp B-phase cho ch m phase ca knh 1 v 5)
TCLKC
Nhp
Chn nhp xung ng h ngoi C (Tn hiu nhp A-phase cho ch m phase ca knh 2 v 4)
TCLKD
Nhp
Chn nhp xung ng h ngoi D (Tn hiu nhp B-phase cho ch m phase ca knh 2 v 4)
TIOCA0
Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRA_0 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRB_0 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRC_0 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRD_0 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRA_1 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRB_1 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRA_2 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRB_2
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
163
TIOCA3
Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRA_3 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRB_3 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRC_3 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRD_3 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRA_4 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRB_4 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRA_5 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRB_5 Nhp Chn nhp xung ng h ngoi A (Tn hiu nhp A-phase cho ch m phase ca knh 7 v 11)
TIOCB3
TIOCC3
TIOCD3
TIOCA4
TIOCB4
TIOCA5
TIOCB5
Tt c
TCLKE
TCLKF
Nhp
Chn nhp xung ng h ngoi B (Tn hiu nhp B-phase cho ch m phase ca knh 7 v 11)
TCLKG
Nhp
Chn nhp xung ng h ngoi C (Tn hiu nhp A-phase cho ch m phase ca knh 8 v 10)
TCLKH
Nhp
Chn nhp xung ng h ngoi D (Tn hiu nhp B-phase cho ch m phase ca knh 8 v 10)
164
TIOCA6
Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRA_6 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRB_6 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRC_6 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRD_6 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRA_7 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRB_7 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRA_8 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRB_8 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRA_9 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRB_9 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRC_9 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRD_9
TIOCB6
TIOCC6
TIOCD6
TIOCA7
TIOCB7
TIOCA8
TIOCB8
TIOCA9
TIOCB9
TIOCC9
TIOCD9
10
TIOCA10 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM 165
TGRA_10 TIOCB10 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRB_10 11 TIOCA11 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRA_11 TIOCB11 Xut/nhp Chn nhp tn hiu input capture/ Chn xut output compare/Chn xut tn hiu PWM TGRB_11
7.3 c t thanh ghi

TPU c cc thanh ghi sau trong mi ch Cc thanh ghi cho b m 0 v b m 1 cc cng chc nng tr bit 7 (bit TTGE i vi b m 0 v bit d tr i vi b m 1) trong thanh ghi TIER. y l phn c t cc thanh ghi ca b m 0. B m 0: Ch 0: Thanh ghi iu khin b m 0 (TCR_0) Thanh ghi ch 0 (TMDR_0) Thanh ghi iu khin xut/nhp b m H_0 (TIORH_0) Thanh ghi iu khin xut/nhp b m L_0 (TIORL_0) Thanh ghi cho php ngt b m 0 (TIER_0) Thanh ghi trng thi b m 0 (TSR_0) Thanh ghi cha bin m ca b m 0 (TCNT_0) Thanh ghi a dng A_0 (TGRA_0) Thanh ghi a dng B_0 (TGRB_0) Thanh ghi a dng C_0 (TGRC_0) Thanh ghi a dng D_0 (TGRD_0) Ch 1: Thanh ghi iu khin b m 1 (TCR_1) Thanh ghi ch 1 (TMDR_1) Thanh ghi iu khin xut/nhp b m 1 (TIOR_1) Thanh ghi cho php ngt b m 1 (TIER_1)
166
Thanh ghi trng thi b m 1 (TSR_1) Thanh ghi cha bin m ca b m 1 (TCNT_1) Thanh ghi a dng A_1 (TGRA_1) Thanh ghi a dng B_1 (TGRB_1) Ch 2: Thanh ghi iu khin b m 2 (TCR_2) Thanh ghi ch 2 (TMDR_2) Thanh ghi iu khin xut/nhp b m 2 (TIOR_2) Thanh ghi cho php ngt b m 2 (TIER_2) Thanh ghi trng thi b m 2 (TSR_2) Thanh ghi cha bin m ca b m 2 (TCNT_2) Thanh ghi a dng A_2 (TGRA_2) Thanh ghi a dng B_2 (TGRB_2) Ch 3: Thanh ghi iu khin b m 3 (TCR_3) Thanh ghi ch 3 (TMDR_3) Thanh ghi iu khin xut/nhp b m H_3 (TIORH_3) Thanh ghi iu khin xut/nhp b m L_3 (TIORL_3) Thanh ghi cho php ngt b m 3 (TIER_3) Thanh ghi trng thi b m 3 (TSR_3) Thanh ghi cha bin m ca b m 3 (TCNT_3) Thanh ghi a dng A_3 (TGRA_3) Thanh ghi a dng B_3 (TGRB_3) Thanh ghi a dng C_3 (TGRC_3) Thanh ghi a dng D_3 (TGRD_3) Ch 4: Thanh ghi iu khin b m 4 (TCR_4) Thanh ghi ch 4 (TMDR_4) Thanh ghi iu khin xut/nhp b m 4 (TIOR_4) Thanh ghi cho php ngt b m 4 (TIER_4) Thanh ghi trng thi b m 4 (TSR_4) Thanh ghi cha bin m ca b m 4 (TCNT_4) Thanh ghi a dng A_4 (TGRA_4)
167
Thanh ghi a dng B_4 (TGRB_4) Ch 5: Thanh ghi iu khin b m 5 (TCR_5) Thanh ghi ch 5 (TMDR_5) Thanh ghi iu khin xut/nhp b m 5 (TIOR_5) Thanh ghi cho php ngt b m 5 (TIER_5) Thanh ghi trng thi b m 5 (TSR_5) Thanh ghi cha bin m ca b m 5 (TCNT_5) Thanh ghi a dng A_5 (TGRA_5) Thanh ghi a dng B_5 (TGRB_5) Thanh ghi a dng C_5 (TGRC_5) Thanh ghi a dng D_5 (TGRD_5) Cc thanh ghi thng thng: Thanh ghi bt u b m (TSTR) Thanh ghi ng b b m (TSYR) B m 1 Ch 6: Thanh ghi iu khin b m 6 (TCR_6) Thanh ghi ch 6 (TMDR_6) Thanh ghi iu khin xut/nhp b m H_6 (TIORH_6) Thanh ghi iu khin xut/nhp b m L_6 (TIORL_6) Thanh ghi cho php ngt b m 6 (TIER_6) Thanh ghi trng thi b m 6 (TSR_6) Thanh ghi cha bin m ca b m 6 (TCNT_6) Thanh ghi a dng A_6 (TGRA_6) Thanh ghi a dng B_6 (TGRB_6) Thanh ghi a dng C_6 (TGRC_6) Thanh ghi a dng D_6 (TGRD_6) Ch 7: Thanh ghi iu khin b m 7 (TCR_7) Thanh ghi ch 7 (TMDR_7) Thanh ghi iu khin xut/nhp b m 7 (TIOR_7) Thanh ghi cho php ngt b m 7 (TIER_7)
168
Thanh ghi trng thi b m 7 (TSR_7) Thanh ghi cha bin m ca b m 7 (TCNT_7) Thanh ghi a dng A_7 (TGRA_7) Thanh ghi a dng B_7 (TGRB_7) Ch 8: Thanh ghi iu khin b m 8 (TCR_8) Thanh ghi ch 8 (TMDR_8) Thanh ghi iu khin xut/nhp b m 8 (TIOR_8) Thanh ghi cho php ngt b m 8 (TIER_8) Thanh ghi trng thi b m 8 (TSR_8) Thanh ghi cha bin m ca b m 8 (TCNT_8) Thanh ghi a dng A_8 (TGRA_8) Thanh ghi a dng B_8 (TGRB_8) Ch 9: Thanh ghi iu khin b m 9 (TCR_9) Thanh ghi ch 9 (TMDR_9) Thanh ghi iu khin xut/nhp b m H_9 (TIORH_9) Thanh ghi iu khin xut/nhp b m L_9 (TIORL_9) Thanh ghi cho php ngt b m 9 (TIER_9) Thanh ghi trng thi b m 9 (TSR_9) Thanh ghi cha bin m ca b m 9 (TCNT_9) Thanh ghi a dng A_9 (TGRA_9) Thanh ghi a dng B_9 (TGRB_9) Thanh ghi a dng C_9 (TGRC_9) Thanh ghi a dng D_9 (TGRD_9) Ch 10: Thanh ghi iu khin b m 10 (TCR_10) Thanh ghi ch 10 (TMDR_10) Thanh ghi iu khin xut/nhp b m 10 (TIOR_10) Thanh ghi cho php ngt b m 10 (TIER_10) Thanh ghi trng thi b m 10 (TSR_10) Thanh ghi cha bin m ca b m 10 (TCNT_10) Thanh ghi a dng A_10 (TGRA_10)
169
Thanh ghi a dng B_10 (TGRB_10) Ch 11: Thanh ghi iu khin b m 11 (TCR_11) Thanh ghi ch 11 (TMDR_11) Thanh ghi iu khin xut/nhp b m 11 (TIOR_11) Thanh ghi cho php ngt b m 11 (TIER_11) Thanh ghi trng thi b m 11 (TSR_11) Thanh ghi cha bin m ca b m 11 (TCNT_11) Thanh ghi a dng A_11 (TGRA_11) Thanh ghi a dng B_11 (TGRB_11) Thanh ghi a dng C_11 (TGRC_11) Thanh ghi a dng D_11 (TGRD_11) Cc thanh ghi thng thng: Thanh ghi bt u b m (TSTRB) Thanh ghi ng b b m (TSYRB) 7.3.1 Thanh ghi iu khin b m (TCR) Thanh ghi TCR iu khin s hot ng ca thanh ghi TCNT i vi tng ch . TPU c tng cng 6 thanh ghi TCR, mi knh c 1 thanh ghi. Vic thit lp trn thanh ghi TCR ch nn c thc hin trong khi hot ng ca thanh ghi TCNT b dng.
Bit
Tn bit
Gi tr khi u 0 0 0 0 0
R/W
c t
7 6 5 4 3
CCLR2 CCLR1 CCLR0 CKEG1 CKEG0
R/W R/W R/W R/W R/W
Bit xa b m 2 n 0 Nhng bit ny la chn cch xa b m cho thanh ghi TCNT. Tham kho chi tit bng 7.5 v 7.6
Bt la chn cnh xung clock 1 n 0 Cc bit ny la chn cnh xung clock nhp. Chi tit, tham kho bng 7.7. Khi xung clock c m s dng c hai cnh (ln v xung), th chu k ca xung
170
clock nhp s b chia i (ngha l P /4 c hai cnh = P /2 cnh ln). Nu ch m nhm (phase counting) c s dng trn knh 1, 2, 4, v 5 th s thit lp ny s b b qua v s thit lp ch phase counting c u tin hn. S chn la xung cnh xung ng h l hp l khi m xung nhp l P /4 hoc thp hn.S thit lp ny s b qua khi xung ng h nhp l P /1, hay khi c mt s trn/thiu ca mt knh khc c chn. 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Timer Prescaler 2 to 0 Cc bit ny la chn xung ng h cho thanh ghi TCNT. Xung ng h ngun c th c chn mt cch c lp i vi tng knh (channel). Tham kho cc bng 7.8 v 7.13 bit thm chi tit. la chn xung cho TCNT l xung ng h ngoi, th bit DDR v ICR tng ng i vi tng chn phi c thit lp l 0 v 1. Chi tit, tham kho Chng 6 port xut nhp
Bng 7.5 CCLR2 n CCLR0 (i vi knh 0 v 3)

Knh 0,3 0 0 Bit 7: CCLR2 0 0 Bit 6: CCLR1 0 1 Bit 5: CCLR0 c t Vic xa TCNT b cm Thanh ghi TCNT c xa bi vic compare match/input capture trn thanh ghi TGRA Thanh ghi TCNT c xa bi vic compare match/input capture trn thanh ghi TGRB Thanh ghi TCNT c xa ng b do vic xa thanh ghi TCNT ca mt knh khc*1 Vic xa TCNT b cm Thanh ghi TCNT c xa bi vic compare match/input capture trn thanh ghi TGRC*2 Thanh ghi TCNT c xa bi vic compare match/input capture trn
1 1
0 0
0 1
171
thanh ghi TGRD*2 1 1 1 Thanh ghi TCNT c xa ng b do vic xa thanh ghi TCNT ca mt knh khc*1
Ch : 1. Cc thao tc ng b ch c hiu lc khi m bit SYNC tng ng vi mi ch trong thanh ghi TSYR c thit lp l 1. 2. Khi thanh ghi TGRC hay TGRD c s dng nh l mt thanh ghi buffer, th TCNT khng c xa bi v vic thit lp thanh ghi buffer c u tin cao hn, v vic compare match/input capture s khng xy ra. (chi tit s c ni n trong phn thao tc buffer) Bng 7.6 CCLR2 n CCLR0 (i vi knh 1, 2, 4 v 5)
Knh 1, 2, 0 4, 5 0 Bit 7: CCLR2*2 0 0 Bit 6: CCLR1 0 1 Bit 5: CCLR0 c t Vic xa TCNT b cm Thanh ghi TCNT c xa bi vic compare match/input capture trn thanh ghi TGRA Thanh ghi TCNT c xa bi vic compare match/input capture trn thanh ghi TGRB Thanh ghi TCNT c xa ng b do vic xa thanh ghi TCNT ca mt knh khc*1
Ch : 1. Cc thao tc ng b ch c hiu lc khi m bit SYNC tng ng vi mi ch trong thanh ghi TSYR c thit lp l 1. 2. Bit 7 c d tr trong knh 1, 2, 4, v 5. N l bit ch c v khng th thay i. Bng 7.7 La chn cnh xung ng h nhp
La chn cnh xung ng h CKEG1 0 0 CKEG0 0 1 Xung ng h nhp Xung ng h trong (Internal Clock) m ti cnh xung m ti cnh ln Xung ng h ngoi (External Clock) m ti cnh xung m ti cnh ln
172
m ti c hai cnh
m ti c hai cnh
Ghi ch: X: khng quan tm Bng 7.8 TPSC2 n TPSC0 (knh 0)

Knh 0 0 0 0 0 1 1 1 1 Bit 2: TPSC2 Bit 1: TPSC1 0 0 1 1 0 0 1 1 Bit 0: TPSC0 0 1 0 1 0 1 0 1 c t Xung ng h trong: m trn P /1 Xung ng h trong: m trn P /4 Xung ng h trong: m trn P /16 Xung ng h trong: m trn P /64 Xung ng h ngoi: m trn chn nhp TCLKA Xung ng h ngoi: m trn chn nhp TCLKB Xung ng h ngoi: m trn chn nhp TCLKC Xung ng h ngoi: m trn chn nhp TCLKD
Bng 7.9 TPSC2 n TPSC0 (knh 1)

Knh 0 0 0 0 0 1 1 Bit 2: TPSC2 Bit 1: TPSC1 0 0 1 1 0 0 Bit 0: TPSC0 0 1 0 1 0 1 c t Xung ng h trong: m trn P /1 Xung ng h trong: m trn P /4 Xung ng h trong: m trn P /16 Xung ng h trong: m trn P /64 Xung ng h ngoi: m trn chn nhp TCLKA Xung ng h ngoi: m trn chn nhp TCLKB
173
1 1
1 1
0 1
Xung ng h trong: m trn P /256 m trn s trn/thiu ca thanh ghi TCNT2
Ch : s thit lp ny s b b qua khi knh 1 nm trong ch m pha (phase counting) Bng 7.10 TPSC2 n TPSC0 (knh 2)
Knh 0 0 0 0 0 1 1 1 1 Bit 2: TPSC2 Bit 1: TPSC1 0 0 1 1 0 0 1 1 Bit 0: TPSC0 0 1 0 1 0 1 0 1 c t Xung ng h trong: m trn P /1 Xung ng h trong: m trn P /4 Xung ng h trong: m trn P /16 Xung ng h trong: m trn P /64 Xung ng h ngoi: m trn chn nhp TCLKA Xung ng h ngoi: m trn chn nhp TCLKB Xung ng h ngoi: m trn chn nhp TCLKC Xung ng h trong: m trn P /1024
Knh 0 0 0 0 0 1 Bit 2: TPSC2 Bit 1: TPSC1 0 0 1 1 0 Bit 0: TPSC0 0 1 0 1 0 c t Xung ng h trong: m trn P /1 Xung ng h trong: m trn P /4 Xung ng h trong: m trn P /16 Xung ng h trong: m trn P /64 Xung ng h ngoi: m trn chn nhp TCLKA
174
1 1 1
0 1 1
1 0 1
Xung ng h trong: m trn P /1024 Xung ng h trong: m trn P /256 Xung ng h trong: m trn P /4096
Bng 7.12 TPSC2 n TPSC0 (knh 4)

Knh 0 0 0 0 0 1 1 1 1 Bit 2: TPSC2 Bit 1: TPSC1 0 0 1 1 0 0 1 1 Bit 0: TPSC0 0 1 0 1 0 1 0 1 c t Xung ng h trong: m trn P /1 Xung ng h trong: m trn P /4 Xung ng h trong: m trn P /16 Xung ng h trong: m trn P /64 Xung ng h ngoi: m trn chn nhp TCLKA Xung ng h ngoi: m trn chn nhp TCLKC Xung ng h trong: m trn P /1024 m trn s trn/thiu ca thanh ghi TCNT5
Knh 0 0 0 0 0 1 1 Bit 2: TPSC2 Bit 1: TPSC1 0 0 1 1 0 0 Bit 0: TPSC0 0 1 0 1 0 1 c t Xung ng h trong: m trn P /1 Xung ng h trong: m trn P /4 Xung ng h trong: m trn P /16 Xung ng h trong: m trn P /64 Xung ng h ngoi: m trn chn nhp TCLKA Xung ng h ngoi: m trn chn nhp TCLKC
175
1 1
1 1
0 1
Xung ng h trong: m trn P /256 Xung ng h ngoi: m trn chn nhp TCLKD
Ch : s thit lp ny s b b qua khi knh 4 nm trong ch m pha (phase counting) 7.3.2 Thanh ghi ch b m (TMDR) Thang ghi TMDR thit lp ch hot ng cho mi knh. B nh thi c 6 thanh ghi TMDR, mi ci dnh cho mi knh. S thit lp thanh ghi TMDR nn c thc hin khi m hot ng ca thanh ghi b m TCNT dng.
Bit 7, 6
Tn bit ---
Gi tr khi u Tt c l 1
R/W c t R Khng dng y l nhng bit ch c v khng th thay i gi tr ca n
BFB
R/W
Hot ng b m B Bit ny ch ra rng liu thanh ghi TGRB ang trong ch hot ng bnh thng hay TGRB v TGRD ang c s dng vi vai tr l cc thanh ghi buffer. Khi Thanh ghi TGRD c s dng nh l mt thanh ghi buffer, th vic input capture/outputcompare trn thanh ghi ny s khng th thc hin (v c u tin thp hn). Trong cc knh 1, 2, 4, v 5 khng c thanh ghi TGRD, th bit 5 c d tr, N s l bit ch c v khng th thay i gi tr. 0: Thanh ghi TGRB hot ng ch bnh thng 1: Thanh ghi TGRB v TGRD c s dng vi nhau vi vai tr l thanh ghi buffer.
BFA
R/W
Hot ng buffer A Bit ny ch ra rng liu thanh ghi TGRA ang trong ch hot ng bnh thng hay TGRA v TGRC ang c s dng vi vai tr l cc thanh ghi buffer. Khi Thanh ghi TGRC c s dng nh l mt thanh ghi buffer, th vic input capture/outputcompare trn
176
thanh ghi ny s khng th thc hin (v c u tin thp hn). Trong cc knh 1, 2, 4, v 5 khng c thanh ghi TGRC, th bit 4 c d tr, N s l bit ch c v khng th thay i gi tr. 0: Thanh ghi TGRA hot ng ch bnh thng 1: Thanh ghi TGRA v TGRC c s dng vi nhau vi vai tr l thanh ghi buffer. 3 2 1 0 MD3 MD2 MD1 MD0 0 0 0 0 R/W R/W R/W R/W Cc ch 3 n 0 Cc bit ny dng thit lp trng thi hot ng ca b m MD3 l bit d tr. Gi tr c ghi vo bit ny lun lun l 0. Tham kho bng 7.14 bit thm chi tit.
Bng 7.14 MD3 n MD0

Bit 3: MD3*1 0 0 0 0 0 0 0 0 1 Bit 2: MD2*2 0 0 0 0 1 1 1 1 X Bit 1: MD1 0 0 1 1 0 0 1 1 X Bit 0: MD0 0 1 0 1 0 1 0 1 X c t Ch bnh thng Khng dng Ch PWM 1 Ch PWM 2 Ch m phase 1 Ch m phase 2 Ch m phase 3 Ch m phase 4 ---
Ghi ch: X: khng quan tm Ch : 1. MD3 l mt bit d tr. Gi tr ca n lun lun l 0 2. Ch m phase khng th thit lp cho knh 0 v 3. Trong trng hp ny, gi tr ghi vo lun lun l 0.
177
7.3.3 Thanh ghi iu khin xut nhp ca b m (TIOR) Thanh ghi TIOR iu khin cc thanh ghi TGR. B nh thi c 8 thanh ghi TIOR, ch 0 c 2 thanh ghi, ch 3 c 2 thanh ghi v mi ch 1, 2, 4, v 5 c 1 thanh ghi. Thanh ghi TIOR b nh hng bi thanh ghi TMDR. Gi tr xut ban u ca cc chn c ch nh bi thanh ghi TIOR l hp l khi m b m dng (Bit CST trong thanh ghi TSTR b xa xung 0). Ch rng, trong ch PWM 2, tn hiu xut ti im m b m c xa xung 0 l c xc nh. Khi m thanh ghi TGRC hay TGRD c ch nh cho hot ng buffer, th s thit lp ny (s thit ca thanh ghi TIOR) l khng cn hp l v cc thanh ghi ny s hot ng nh l nhng thanh ghi buffer. xc nh chn input capture trong thanh ghi TIOR, th bit DDR v ICR tng ng vi chn s c thit lp l 0 v 1 tng ng. Chi tit tham kho chng 6 cc cng xut nhp. TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5
TIORL_0, TORL_3
TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5

Bit 7 6 5 4 3 2 1 0 Tn bit IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Gi tr khi u 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W iu khin xut nhp A3 n A0 Ch nh chc nng ca thanh ghi TGRA Chi tit, tham kho bng 7.23, 7.25, 7.26, 7.27, 7.29, v 7.30 c t iu khin xut nhp B3 n B0 Ch nh chc nng ca thanh ghi TGRB Chi tit, tham kho bng 7.15, 7.17, 7.18, 7.19, 7.21, v 7.22
178
TIORL_0, TIORL_3:
Bit 7 6 5 4 3 2 1 0 Tn bit IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Gi tr khi u 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W iu khin xut nhp C3 n C0 Ch nh chc nng ca thanh ghi TGRA Chi tit, tham kho bng 7.24, 7.28 c t iu khin xut nhp D3 n D0 Ch nh chc nng ca thanh ghi TGRD Chi tit, tham kho bng 7.16, 7.20
Bng 7.15 TIORH_0

Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 Chc nng TGRB_0 Thanh ghi output compare c t Chc nng chn TIOCB0 Tn hiu xut b cm Khi ng gi tr xut l 0 Xut ra 0 nu compare match (so snh trng vi thanh ghi TCNT) 0 0 1 0 Khi ng gi tr xut l 0 Xut ra 1 nu compare match 0 0 1 1 Khi ng gi tr xut l 0 o tn hiu xut nu compare match 0 0 1 1 0 0 0 1 Tn hiu xut b cm Khi ng gi tr xut l 1 Xut ra 0 nu compare match 0 1 1 0 Khi ng gi tr xut l 1 Xut ra 1 nu compare match
0 0
0 0
0 0
0 1
179
Khi ng gi tr xut l 1 o tn hiu xut nu compare match
Thanh ghi Input capture
Tn hiu nhp ca input capture l chn TIOCB0. V hot ng input capture thc hin cnh ln Tn hiu nhp ca input capture l chn TIOCB0. V hot ng input capture thc hin cnh xung Tn hiu nhp ca input capture l chn TIOCB0. V hot ng input capture thc hin c cnh ln v cnh xung Tn hiu nhp ca input capture l knh 1/ xung m clock. V hot ng input capture thc hin khi TCNT_1 m ln/m xung*
Ghi ch: X: khng quan thm Ch :Khi m cc bit TPSC2 n TPSC0 trong thanh ghi TCR_1 c thit lp l B000 v P /1 c s dng vi vai tr l xung ng h, th vic thit lp ny l khng hp l v vic input capture s khng xy ra. Bng 7.16 TIORL_0
Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 Chc nng TGRD_0 Thanh ghi output compare*2 c t Chc nng chn TIOCD0 Tn hiu xut b cm Khi ng gi tr xut l 0 Xut ra 0 nu compare match (so snh trng vi thanh ghi TCNT) 0 0 1 0 Khi ng gi tr xut l 0 Xut ra 1 nu compare match 0 0 1 1 Khi ng gi tr xut l 0 o tn hiu xut nu compare match 0 1 0 0 Tn hiu xut b cm
0 0
0 0
0 0
0 1
180
Khi ng gi tr xut l 1 Xut ra 0 nu compare match
Thanh ghi Input capture*2
Tn hiu nhp ca input capture l chn TIOCD0. V hot ng input capture thc hin cnh ln Tn hiu nhp ca input capture l chn TIOCD0. V hot ng input capture thc hin cnh xung Tn hiu nhp ca input capture l chn TIOCD0. V hot ng input capture thc hin c cnh ln v cnh xung Tn hiu nhp ca input capture l knh 1/ xung m clock. V hot ng input capture thc hin khi TCNT_1 m ln/m xung*1
Ch : 1. Khi cc bit TPSC2 n TPSC2 trong TCR_1 c thit lp l B000 v P /1 c s dng nh l xung ng h ca TCNT_1, th vic thit lp ny l hp l v vic input capture s khng xy ra. 2. Khi m bit BFB trong thanh ghi TMDR_0 c thit lp l 1 v TGRD_0 c s dng vi vai tr l thanh ghi buffer, th vic thit lp ny l hp l v vic input capture/output compare s khng xy ra. Bng 7.17 TIOR_1
Bit 7 IOB3
Bit 6 IOB2
Bit 5 IOB1
Bit 4 IOB0 Chc nng TGRB_1 Thanh ghi output
c t Chc nng chn TIOCB1 Tn hiu xut b cm Khi ng gi tr xut l 0
0 0
0 0
0 0
0 1
181
compare 0 0 1 0
Xut ra 0 nu compare match (so snh trng vi thanh ghi TCNT) Khi ng gi tr xut l 0 Xut ra 1 nu compare match
0 0
1 1
0 0
0 1
Tn hiu xut b cm Khi ng gi tr xut l 1 Xut ra 0 nu compare match
Tn hiu nhp ca input capture l chn TIOCB1. V hot ng input capture thc hin cnh ln Tn hiu nhp ca input capture l chn TIOCB1. V hot ng input capture thc hin cnh xung Tn hiu nhp ca input capture l chn TIOCB1. V hot ng input capture thc hin c cnh ln v cnh xung Compare match/input capture trn thanh ghi TGRC_0 Hot ng input capture s thc thin khi mt compare match/input capture trn TGRC_0
Ghi ch: X: khng quan tm Bng 7.18 TIOR_2

Bit 7 Bit 6 Bit 5 Bit 4 c t
182
IOB3
IOB2
IOB1
IOB0
Chc nng TGRB_2 Thanh ghi output compare
Chc nng chn TIOCB2 Tn hiu xut b cm Khi ng gi tr xut l 0 Xut ra 0 nu compare match (so snh trng vi thanh ghi TCNT)
0 0
0 0
0 0
0 1
0 0
1 1
0 0
0 1
Tn hiu nhp ca input capture l chn TIOCB2. V hot ng input capture thc hin cnh ln Tn hiu nhp ca input capture l chn TIOCB2. V hot ng input capture thc hin cnh xung Tn hiu nhp ca input capture l chn TIOCB2. V hot ng input capture thc hin c cnh ln v cnh xung
Bng 7.19 TIORH_3

Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 Chc nng TGRB_3 Thanh ghi c t Chc nng chn TIOCB3 Tn hiu xut b cm
183
output compare
Khi ng gi tr xut l 0 Xut ra 0 nu compare match (so snh trng vi thanh ghi TCNT) Khi ng gi tr xut l 0 Xut ra 1 nu compare match
0 0
1 1
0 0
0 1
Tn hiu nhp ca input capture l chn TIOCB3. V hot ng input capture thc hin cnh ln Tn hiu nhp ca input capture l chn TIOCB3. V hot ng input capture thc hin cnh xung Tn hiu nhp ca input capture l chn TIOCB3. V hot ng input capture thc hin c cnh ln v cnh xung Tn hiu nhp ca input capture l knh 4/ xung m clock. V hot ng input capture thc hin khi TCNT_4 m ln/m xung*
Ch : khi cc bit TPSC2 n TPSC0 trong thanh ghi TCR_4 c thit lp l B000 v P /1 c s dng vi vai tr l xung ng h ca TCNT_4, th vic thit lp ny s hp l v hot ng input capture s khng xy ra. Bng 7.20 TIORL_3
Bit 7 Bit 6 Bit 5 Bit 4 c t
184
IOD3
IOD2
IOD1
IOD0
Chc nng TGRD_3 Thanh ghi output compare*2
Chc nng chn TIOCD3 Tn hiu xut b cm Khi ng gi tr xut l 0 Xut ra 0 nu compare match (so snh trng vi thanh ghi TCNT)
0 0
0 0
0 0
0 1
0 0
1 1
0 0
0 1
Tn hiu nhp ca input capture l chn TIOCD3. V hot ng input capture thc hin cnh ln Tn hiu nhp ca input capture l chn TIOCD3. V hot ng input capture thc hin cnh xung Tn hiu nhp ca input capture l chn TIOCD3. V hot ng input capture thc hin c cnh ln v cnh xung Tn hiu nhp ca input capture l knh 4/ xung m clock. V hot ng input capture thc hin khi TCNT_4 m ln/m xung*1
Ch :
185
1. Khi cc bit TPSC2 n TPSC0 trong thanh ghi TCR_4 c thit lp l B000 v P /1 c s dng vi vai tr l xung ng h ca TCNT_4, th vic thit lp ny s hp l v hot ng input capture s khng xy ra. 2. Khi bit BFB trong thanh ghi TMDR_3 c thit lp l 1 v thanh ghi TGRD_3 c s dng nh l thanh ghi buffer, th vic thit lp ny s hp l, v hot ng input capture/output compare s khng xy ra. Bng 7.21 TIOR_4
Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 Chc nng TGRB_4 Thanh ghi output compare c t Chc nng chn TIOCB4 Tn hiu xut b cm Khi ng gi tr xut l 0 Xut ra 0 nu compare match (so snh trng vi thanh ghi TCNT) 0 0 1 0 Khi ng gi tr xut l 0 Xut ra 1 nu compare match 0 0 1 1 Khi ng gi tr xut l 0 o tn hiu xut nu compare match 0 0 1 1 0 0 0 1 Tn hiu xut b cm Khi ng gi tr xut l 1 Xut ra 0 nu compare match 0 1 1 0 Khi ng gi tr xut l 1 Xut ra 1 nu compare match 0 1 1 1 Khi ng gi tr xut l 1 o tn hiu xut nu compare match 1 0 0 0 Thanh ghi Input capture Tn hiu nhp ca input capture l chn TIOCB4. V hot ng input capture thc hin cnh ln Tn hiu nhp ca input capture l chn TIOCB4. V hot ng input capture thc hin cnh xung Tn hiu nhp ca input capture l chn TIOCB4. V hot ng input
0 0
0 0
0 0
0 1
186
capture thc hin c cnh ln v cnh xung 1 1 x x Compare match/input capture trn thanh ghi TGRC_3. V hot ng input capture s thc thin khi mt compare match/input capture trn TGRC_3
Bng 7.22 TIOR_5

Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 Chc nng TGRB_5 Thanh ghi output compare c t Chc nng chn TIOCB5 Tn hiu xut b cm Khi ng gi tr xut l 0 Xut ra 0 nu compare match (so snh trng vi thanh ghi TCNT) 0 0 1 0 Khi ng gi tr xut l 0 Xut ra 1 nu compare match 0 0 1 1 Khi ng gi tr xut l 0 o tn hiu xut nu compare match 0 0 1 1 0 0 0 1 Tn hiu xut b cm Khi ng gi tr xut l 1 Xut ra 0 nu compare match 0 1 1 0 Khi ng gi tr xut l 1 Xut ra 1 nu compare match 0 1 1 1 Khi ng gi tr xut l 1 o tn hiu xut nu compare match 1 X 0 0 Thanh ghi Input capture Tn hiu nhp ca input capture l chn TIOCB5. V hot ng input capture thc hin cnh ln Tn hiu nhp ca input capture l chn TIOCB5. V hot ng input capture thc hin cnh xung
0 0
0 0
0 0
0 1
187
Tn hiu nhp ca input capture l chn TIOCB5. V hot ng input capture thc hin c cnh ln v cnh xung
Bng 7.23 TIORH_0

Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 Chc nng TGRA_0 Thanh ghi output compare c t Chc nng chn TIOCA0 Tn hiu xut b cm Khi ng gi tr xut l 0 Xut ra 0 nu compare match (so snh trng vi thanh ghi TCNT) 0 0 1 0 Khi ng gi tr xut l 0 Xut ra 1 nu compare match 0 0 1 1 Khi ng gi tr xut l 0 o tn hiu xut nu compare match 0 0 1 1 0 0 0 1 Tn hiu xut b cm Khi ng gi tr xut l 1 Xut ra 0 nu compare match 0 1 1 0 Khi ng gi tr xut l 1 Xut ra 1 nu compare match 0 1 1 1 Khi ng gi tr xut l 1 o tn hiu xut nu compare match 1 0 0 0 Thanh ghi Input capture Tn hiu nhp ca input capture l chn TIOCA0. V hot ng input capture thc hin cnh ln Tn hiu nhp ca input capture l chn TIOCA0. V hot ng input capture thc hin cnh xung Tn hiu nhp ca input capture l chn TIOCA0. V hot ng input capture thc hin c cnh ln v cnh xung
0 0
0 0
0 0
0 1
188
Tn hiu nhp ca input capture l knh 1/ xung m clock. V hot ng input capture* thc hin khi TCNT_1 m ln/m xung
Ch : Khi cc bit TPSC2 n TPSC0 trong thanh ghi TCR_1 c thit lp l B000 v P /1 c s dng vi vai tr l xung ng h ca TCNT_1, th vic thit lp ny s hp l v hot ng input capture s khng xy ra. Bng 7.24 TIORL_0
Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 Chc nng TGRC_0 Thanh ghi output compare*2 c t Chc nng chn TIOCC0 Tn hiu xut b cm Khi ng gi tr xut l 0 Xut ra 0 nu compare match (so snh trng vi thanh ghi TCNT) 0 0 1 0 Khi ng gi tr xut l 0 Xut ra 1 nu compare match 0 0 1 1 Khi ng gi tr xut l 0 o tn hiu xut nu compare match 0 0 1 1 0 0 0 1 Tn hiu xut b cm Khi ng gi tr xut l 1 Xut ra 0 nu compare match 0 1 1 0 Khi ng gi tr xut l 1 Xut ra 1 nu compare match 0 1 1 1 Khi ng gi tr xut l 1 o tn hiu xut nu compare match 1 0 0 0 Thanh ghi Input capture*2 Tn hiu nhp ca input capture l chn TIOCC0. V hot ng input capture thc hin cnh ln Tn hiu nhp ca input capture l chn TIOCC0. V hot ng input capture thc hin cnh xung
0 0
0 0
0 0
0 1
189
Tn hiu nhp ca input capture l chn TIOCC0. V hot ng input capture thc hin c cnh ln v cnh xung Tn hiu nhp ca input capture l knh 1/ xung m clock. V hot ng input capture*1 thc hin khi TCNT_1 m ln/m xung
Ch : 1. Khi cc bit TPSC2 n TPSC0 trong thanh ghi TCR_1 c thit lp l B000 v P /1 c s dng vi vai tr l xung ng h ca TCNT_1, th vic thit lp ny s hp l v hot ng input capture s khng xy ra. 2. Khi bit BFA trong thanh ghi TMDR_0 c thit lp l 1 v thanh ghi TGRC_0 c s dng nh l thanh ghi buffer, th vic thit lp ny s hp l, v hot ng input capture/output compare s khng xy ra. Bng 7.25 TIOR_1
Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 Chc nng TGRA_1 Thanh ghi output compare c t Chc nng chn TIOCA1 Tn hiu xut b cm Khi ng gi tr xut l 0 Xut ra 0 nu compare match (so snh trng vi thanh ghi TCNT) 0 0 1 0 Khi ng gi tr xut l 0 Xut ra 1 nu compare match 0 0 1 1 Khi ng gi tr xut l 0 o tn hiu xut nu compare match 0 0 1 1 0 0 0 1 Tn hiu xut b cm Khi ng gi tr xut l 1 Xut ra 0 nu compare match 0 1 1 0 Khi ng gi tr xut l 1 Xut ra 1 nu compare match 0 1 1 1 Khi ng gi tr xut l 1
0 0
0 0
0 0
0 1
190
o tn hiu xut nu compare match 1 0 0 0 Thanh ghi Input capture Tn hiu nhp ca input capture l chn TIOCA1. V hot ng input capture thc hin cnh ln Tn hiu nhp ca input capture l chn TIOCA1. V hot ng input capture thc hin cnh xung Tn hiu nhp ca input capture l chn TIOCA1. V hot ng input capture thc hin c cnh ln v cnh xung Compare match/input capture trn thanh ghi TGRA_0. V hot ng input capture s thc thin khi mt compare match/input capture trn TGRA_0
Bng 7.26 TIOR_2

Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 Chc nng TGRA_2 Thanh ghi output compare c t Chc nng chn TIOCA2 Tn hiu xut b cm Khi ng gi tr xut l 0 Xut ra 0 nu compare match (so snh trng vi thanh ghi TCNT) 0 0 1 0 Khi ng gi tr xut l 0 Xut ra 1 nu compare match 0 0 1 1 Khi ng gi tr xut l 0 o tn hiu xut nu compare match 0 0 1 1 0 0 0 1 Tn hiu xut b cm Khi ng gi tr xut l 1 Xut ra 0 nu compare match 0 1 1 0 Khi ng gi tr xut l 1 Xut ra 1 nu compare match
0 0
0 0
0 0
0 1
191
Tn hiu nhp ca input capture l chn TIOCA2. V hot ng input capture thc hin cnh ln Tn hiu nhp ca input capture l chn TIOCA2. V hot ng input capture thc hin cnh xung Tn hiu nhp ca input capture l chn TIOCA2. V hot ng input capture thc hin c cnh ln v cnh xung
Bng 7.27 TIORH_3

Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 Chc nng TGRA_3 Thanh ghi output compare c t Chc nng chn TIOCA3 Tn hiu xut b cm Khi ng gi tr xut l 0 Xut ra 0 nu compare match (so snh trng vi thanh ghi TCNT) 0 0 1 0 Khi ng gi tr xut l 0 Xut ra 1 nu compare match 0 0 1 1 Khi ng gi tr xut l 0 o tn hiu xut nu compare match 0 0 1 1 0 0 0 1 Tn hiu xut b cm Khi ng gi tr xut l 1 Xut ra 0 nu compare match 0 1 1 0 Khi ng gi tr xut l 1 Xut ra 1 nu compare match 0 1 1 1 Khi ng gi tr xut l 1 o tn hiu xut nu compare match 1 0 0 0 Thanh ghi Tn hiu nhp ca input capture l
0 0
0 0
0 0
0 1
192
Input capture 1 0 0 1
chn TIOCA3. V hot ng input capture thc hin cnh ln Tn hiu nhp ca input capture l chn TIOCA3. V hot ng input capture thc hin cnh xung Tn hiu nhp ca input capture l chn TIOCA3. V hot ng input capture thc hin c cnh ln v cnh xung Tn hiu nhp ca input capture l knh 4/ xung m clock. V hot ng input capture* thc hin khi TCNT_4 m ln/m xung
Ch : Khi cc bit TPSC2 n TPSC0 trong thanh ghi TCR_4 c thit lp l B000 v P /1 c s dng vi vai tr l xung ng h ca TCNT_4, th vic thit lp ny s hp l v hot ng input capture s khng xy ra. Bng 7.28 TIORL_3
Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 Chc nng TGRC_3 Thanh ghi output compare*2 c t Chc nng chn TIOCC3 Tn hiu xut b cm Khi ng gi tr xut l 0 Xut ra 0 nu compare match (so snh trng vi thanh ghi TCNT) 0 0 1 0 Khi ng gi tr xut l 0 Xut ra 1 nu compare match 0 0 1 1 Khi ng gi tr xut l 0 o tn hiu xut nu compare match 0 0 1 1 0 0 0 1 Tn hiu xut b cm Khi ng gi tr xut l 1 Xut ra 0 nu compare match 0 1 1 0 Khi ng gi tr xut l 1 Xut ra 1 nu compare match
0 0
0 0
0 0
0 1
193
Tn hiu nhp ca input capture l chn TIOCC3. V hot ng input capture thc hin cnh ln Tn hiu nhp ca input capture l chn TIOCC3. V hot ng input capture thc hin cnh xung Tn hiu nhp ca input capture l chn TIOCC3. V hot ng input capture thc hin c cnh ln v cnh xung Tn hiu nhp ca input capture l knh 4/ xung m clock. V hot ng input capture*1 thc hin khi TCNT_4 m ln/m xung
Ch : 1. Khi cc bit TPSC2 n TPSC0 trong thanh ghi TCR_4 c thit lp l B000 v P /1 c s dng vi vai tr l xung ng h ca TCNT_4, th vic thit lp ny s hp l v hot ng input capture s khng xy ra. 2. Khi bit BFA trong thanh ghi TMDR_3 c thit lp l 1 v thanh ghi TGRC_3 c s dng nh l thanh ghi buffer, th vic thit lp ny s hp l, v hot ng input capture/output compare s khng xy ra. Bng 7.29 TIOR_4
Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 Chc nng TGRA_4 Thanh ghi output compare c t Chc nng chn TIOCA4 Tn hiu xut b cm Khi ng gi tr xut l 0 Xut ra 0 nu compare match (so snh trng vi thanh ghi TCNT) 0 0 1 0 Khi ng gi tr xut l 0 Xut ra 1 nu compare match 0 0 1 1 Khi ng gi tr xut l 0 o tn hiu xut nu compare match
0 0
0 0
0 0
0 1
194
0 0
1 1
0 0
0 1
Tn hiu nhp ca input capture l chn TIOCA4. V hot ng input capture thc hin cnh ln Tn hiu nhp ca input capture l chn TIOCA4. V hot ng input capture thc hin cnh xung Tn hiu nhp ca input capture l chn TIOCA4. V hot ng input capture thc hin c cnh ln v cnh xung Compare match/input capture trn thanh ghi TGRA_3. V hot ng input capture s thc thin khi mt compare match/input capture trn TGRA_3
Bng 7.30 TIOR_5

Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 Chc nng TGRA_5 Thanh ghi output compare c t Chc nng chn TIOCA5 Tn hiu xut b cm Khi ng gi tr xut l 0 Xut ra 0 nu compare match (so snh trng vi thanh ghi TCNT) 0 0 1 0 Khi ng gi tr xut l 0 Xut ra 1 nu compare match 0 0 1 1 Khi ng gi tr xut l 0
0 0
0 0
0 0
0 1
195
o tn hiu xut nu compare match 0 0 1 1 0 0 0 1 Tn hiu xut b cm Khi ng gi tr xut l 1 Xut ra 0 nu compare match 0 1 1 0 Khi ng gi tr xut l 1 Xut ra 1 nu compare match 0 1 1 1 Khi ng gi tr xut l 1 o tn hiu xut nu compare match 1 X 0 0 Thanh ghi Input capture Tn hiu nhp ca input capture l chn TIOCA5. V hot ng input capture thc hin cnh ln Tn hiu nhp ca input capture l chn TIOCA5. V hot ng input capture thc hin cnh xung Tn hiu nhp ca input capture l chn TIOCA5. V hot ng input capture thc hin c cnh ln v cnh xung
7.3.4 Thanh ghi cho php ngt b m (TIER) Thanh ghi TIER iu khin vic cho php hay cm tn hiu yu cu ngt qung cho mi knh. B nh thi c 6 thanh ghi TIER, mi thanh ghi mt knh.
Ch : Bit 7 trong thanh ghi TIER ca unit 1 l bit d tr v n lun lun c gi tr l 0.

Bit 7 Tn bit TTGE* Gi tr khi u 0 R/W R/W c t Cho php yu cu khi ng chuyn i A/D Cho php/cm s pht sinh yu cu khi ng trnh chuyn i A/D bi vic input capture/compare match trn thanh ghi TGRA. 0: Cm 1: cho php
196
---
Khng dng Bit ny l mt bit ch c v khng th thay i gi tr.
TCIEU
R/W
Ngt qung sinh ra khi c s thiu (underflow) Bit ny cho php/cm cc yu cu ngt qung c to ra bi c TCFU khi m c ny trong thanh ghi TSR c thit lp l 1 trong knh 1, 2, 4, v 5. Trong cc knh 0 v 3 th bi ny l bit d tr. N l bit ch c v khng th thay i 0: Cm cc yu cu ngt qung t TCFU (TCIU) 1: Cho php cc yu cu ngt qung t TCFU (TCIU)
TCIEV
R/W
Ngt qung trn (overflow) Bit ny cho php/cm cc yu cu ngt qung c to ra t c TCFV (c trn) khi m c ny trong thanh ghi TSR c thit lp ln 1. 0: Cm cc yu cu ngt qung t TCFV (TCIV) 1: Cho php cc yu cu ngt qung t TCFV (TCIV)
TGIED
R/W
Ngt qung TGR D Bit ny cho php/cm cc yu cu ngt qung n t bit TGFD khi m bit TGFD trong thanh ghi TSR c thit lp ln 1 trong cc ch 0 v 3 (khi m hot ng input capture/output compare xy ra, n s thit lp bit TGFD trong TSR ln 1 ng thi pht ra tn hiu ngt qung). Trong cc ch cn li 1, 2, 4, v 5 th n l bit d tr. V n l bit ch c 0: Cm cc yu cu ngt qung t TGFD (TGID) 1: Cho php cc yu cu ngt qung t TGFD (TGID)
TGIEC
R/W
Ngt qung TGR C Bit ny cho php/cm cc yu cu ngt qung n t bit TGFC khi m bit TGFC trong thanh
197
ghi TSR c thit lp ln 1 trong cc ch 0 v 3 (khi m hot ng input capture/output compare xy ra, n s thit lp bit TGFC trong TSR ln 1 ng thi pht ra tn hiu ngt qung). Trong cc ch cn li 1, 2, 4, v 5 th n l bit d tr. V n l bit ch c 0: Cm cc yu cu ngt qung t TGFC (TGIC) 1: Cho php cc yu cu ngt qung t TGFC (TGIC) 1 TGIEB 0 R/W Ngt qung TGR B Bit ny cho php/cm cc yu cu ngt qung n t bit TGFB khi m bit TGFB trong thanh ghi TSR c thit lp ln 1 (khi m hot ng input capture/output compare xy ra, n s thit lp bit TGFB trong TSR ln 1 ng thi pht ra tn hiu ngt qung). 0: Cm cc yu cu ngt qung t TGFB (TGIB) 1: Cho php cc yu cu ngt qung t TGFB (TGIB) 0 TGIEA 0 R/W Ngt qung TGR A Bit ny cho php/cm cc yu cu ngt qung n t bit TGFA khi m bit TGFA trong thanh ghi TSR c thit lp ln 1 (khi m hot ng input capture/output compare xy ra, n s thit lp bit TGFA trong TSR ln 1 ng thi pht ra tn hiu ngt qung). 0: Cm cc yu cu ngt qung t TGFA (TGIA) 1: Cho php cc yu cu ngt qung t TGFA (TGIA)
Ch : Bit 7 trong thanh ghi TIER cho unit 1 l mt bit d tr v n lun lun c gi tr l 0. 7.3.5 Thanh ghi trng thi b m (TSR) Thanh ghi TSR xc nh cc trng thi cho mi b m. B nh thi TPU c 6 thanh ghi TSR, mi thanh ghi cho mi ch .
198
Ch : * Ch c th ghi gi tr 0 vo cc bit t bit 5 n bit 0, xa cc c

Bit 7 Tn bit TCFD Gi tr khi u 1 R/W R C hng m Trng thi ca c ny s ch ra hng m TCNT s m trong cc knh 1, 2, 4, v 5 Trong knh 0 v 3 th bit 7 l bit d tr. N l mt bit ch c v khng th hiu chnh gi tr. 0: TCNT m xung 1: TCNT m ln 6 --1 R Khng dng y l mt bit ch c v n khng th b thay i gi tr. 5 TCFU 0 R/(W)* C thiu (underflow) Trng thi ca c ny s ch nh rng mt TCNT xy ra hin tng underflow khi cc knh 1, 2, 4, v 5 c thit lp ch m phase Trong knh 0 v 3, th bit 5 l bit d tr. V n s l bit ch c, gi tr ca n khng th thay i [iu kin thit lp] (iu khin c c thit lp l 1) Khi m gi tr trong TCNT xy ra underflow (tc l gi tr chuyn t H0000 xung HFFFF) [iu kin xa] (iu khin xa c) Khi m mt gi tr 0 c ghi vo TCFU sau khi c TCFU=1. Lu ch c gi tr 0 mi c ghi vo c ny nhm mc ch xa n. 4 TCFV 0 R/(W)* C trn (overflow) Trng thi ca c ch ra rng c mt s trn mt TCNT. [iu kin thit lp] (TCFV=1) Khi m gi tr ca mt TCNT b trn (ngha l chuyn t HFFFF ln H0000) c t
199
[iu kin xa] (TCFV=0) Khi m gi tr 0 c ghi vo TCFV sau khi c c TCFV=1. 3 TGFD 0 R/(W)* C input capture/compare D Trng thi ca c ny ch ra rng c mt hnh ng input capture trn TGRD hay mt s compare match trn thanh ghi ny trong cc ch 0 v 3. Trong ch 1, 2, 4, v 5 th bit 3 l bit d tr. V n l bit ch c v khng th thay i gi tr ca n. [iu kin thit lp] (TGFD=1) Khi m gi tr trong TCNT = gi tr trong TGRD vi iu kin l TGRD c chc nng l mt thanh ghi output compare Khi m gi tr trong TCNT c chuyn sang (capture) trong thanh ghi TGRD bi mt tn hiu nhp (input capture) vi iu kin l thanh ghi ny ang c chc nng l mt thanh ghi input capture [iu kin xa] (TGFD=0) Khi m b iu khin truyn d liu DTC c kch hot bi mt tn hiu ngt qung TGID vi iu kin l bit DISEL trong thanh ghi MRB ca DTC c gi tr l 0 Khi m mt gi tr 0 c ghi vo TGFD sau khi c TGFD=1 2 TGFC 0 R/(W)* C input capture/compare C Trng thi ca c ny ch ra rng c mt hnh ng input capture trn TGRC hay mt s compare match trn thanh ghi ny trong cc ch 0 v 3. Trong ch 1, 2, 4, v 5 th bit 3 l bit d tr. V n l bit ch c v khng th thay i gi tr ca n. [iu kin thit lp] (TGFC=1) Khi m gi tr trong TCNT = gi tr trong TGRC vi iu kin l TGRC c chc nng l mt thanh ghi output compare Khi m gi tr trong TCNT c chuyn sang (capture) trong thanh ghi TGRC bi mt tn hiu nhp (input capture) vi iu kin l thanh ghi ny ang c chc nng l 200
mt thanh ghi input capture [iu kin xa] (TGFC=0) Khi m b iu khin truyn d liu DTC c kch hot bi mt tn hiu ngt qung TGIC vi iu kin l bit DISEL trong thanh ghi MRB ca DTC c gi tr l 0 Khi m mt gi tr 0 c ghi vo TGFC sau khi c TGFC=1 1 TGFB 0 R/(W)* C input capture/compare B Trng thi ca c ny ch ra rng c mt hnh ng input capture trn TGRC hay mt s compare match trn thanh ghi ny. [iu kin thit lp] (TGFB=1) Khi m gi tr trong TCNT = gi tr trong TGRB vi iu kin l TGRB c chc nng l mt thanh ghi output compare Khi m gi tr trong TCNT c chuyn sang (capture) trong thanh ghi TGRB bi mt tn hiu nhp (input capture) vi iu kin l thanh ghi ny ang c chc nng l mt thanh ghi input capture [iu kin xa] (TGFB=0) Khi m b iu khin truyn d liu DTC c kch hot bi mt tn hiu ngt qung TGIB vi iu kin l bit DISEL trong thanh ghi MRB ca DTC c gi tr l 0 Khi m mt gi tr 0 c ghi vo TGFB sau khi c TGFB=1 0 TGFA 0 R/(W)* C input capture/compare A Trng thi ca c ny ch ra rng c mt hnh ng input capture trn TGRC hay mt s compare match trn thanh ghi ny. [iu kin thit lp] (TGFA=1) Khi m gi tr trong TCNT = gi tr trong TGRA vi iu kin l TGRA c chc nng l mt thanh ghi output compare Khi m gi tr trong TCNT c chuyn sang (capture) trong thanh ghi TGRA bi mt tn hiu nhp (input capture) vi iu kin l thanh ghi ny ang c chc nng l
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mt thanh ghi input capture [iu kin xa] (TGFA=0) Khi m b iu khin truyn d liu DTC c kch hot bi mt tn hiu ngt qung TGIA vi iu kin l bit DISEL trong thanh ghi MRB ca DTC c gi tr l 0 Khi m mt gi tr 0 c ghi vo TGFA sau khi c TGFA=1
Ch : * ch c gi tr 0 mi c th ghi vo cc bit ny xa c 7.3.6 Thanh ghi b m (TCNT) Thanh ghi TCNT l mt thanh ghi b m 16-bit c th c/ghi. B nh thi TPU c 6 thanh ghi TCNT, mi thanh cho mt knh. Thanh ghi TCNT c khi u gi tr l H0000 bi hot ng reset hay mt hot ng standby phn cng. Thanh ghi TCNT khng th truy xut theo n v 8-bit. TCNT phi lun lun c truy xut theo n v 16-bit.
7.3.7 Thanh ghi m rng (TGR) Thanh ghi TGR l mt thanh ghi 16-bit c th c/ghi, n c hai chc nng l: thanh ghi output compare v thanh ghi input capture. B nh thi TPU c 16 thanh ghi TGR, mi knh c 2 thanh ghi ring knh 0 v 3 mi knh c 4 thanh ghi. Thanh ghi TGRC v TGRD ca knh 0 v 3 cng c th c s dng nh l cc thanh ghi buffer. Cc thanh ghi TGR khng b th truy theo n v 8-bit, chng phi lun lun c truy xut theo n v 16-bit. S kt hp ca TGR v thanh ghi buffer trong sut hot ng buffer l TGRA-TGRC v TGRB-TGRD.
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7.3.8 Thanh ghi khi ng b m (TSTR) Thanh ghi TSTR khi ng hay dng hot ng m i vi cc knh 0 n 5. Khi thit lp ch hot ng trong thanh ghi TMDR hay thit lp xung ng h trong thanh ghi TCR, th vic u tin l phi dng hot ng m trong thanh ghi TCNT trc.
Bit 7, 6
Tn bit ---
R/W R/W Khng dng
c t
Cc bit ny lun lun mang gi tr l 0. Gi tr ghi vo nn lun lun l 0 5 4 3 2 1 0 CST5 CST4 CST3 CST2 CST1 CST0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Khi ng b m 5 n 0 Chng l nhng bit la chn vic hot ng hay dng cho hot ng m TCNT. Nu gi tr 0 c ghi vo CST trong sut hot ng vi chn TIOC l chn xut, th b m s dng nhng tn hiu xut output compare ca chn xut TIOC th vn c c php xut. Nu TIOR c vit vo khi m bit CST c xa xung 0, th mc tn hiu xut ra ng xut s c cp nht li gi tr. 0: hot ng m ca TCNT_5 n TCNT_0 s dng 1: hot ng m ca TCNT_5 n TCNT_0 s hot ng
7.3.9 Thanh ghi ng b b m (TSYR) Thanh ghi TSYR la chn hot ng xa b m cho cc knh 0 n 5 theo hnh thc c lp hay l ng b. Mt knh thc hin vic xa ng b khi m bit tng ng vi n trong thanh ghi TSYR c thit lp l 1.
Bit 7, 6
Tn bit ---
R/W R/W Khng dng
c t
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Cc bit ny lun lun mang gi tr l 0. Gi tr ghi vo nn lun lun l 0 5 4 3 2 1 0 SYNC5 0 SYNC4 0 SYNC3 0 SYNC2 0 SYNC1 0 SYNC0 0 R/W R/W R/W R/W R/W R/W ng b b m 5 n 0 Cc bit ny la chn liu hot ng s c lp hay ng b vi cc ch khc. Khi m hot ng ng b c chn, synchronous presetting (vic ghi li ng b) ca nhiu knh, v synchronous clearing (vic xa ng b) thng qua vic xa b m trn mt knh khc l c th xy ra. thit lp hot ng ng b, th bit SYNC ca t nht hai knh phi c thit lp l 1. thit lp ch xa ng b, bn cnh vic thit lp SYNC, th vic xa thanh ghi TCNT ngun phi c thit lp ngha l vic thit lp cc bit CCLR2 n CCLR0 trong thanh ghi TCR 0: hot ng m c lp gia cc knh t 5 n 0 (vic xa/ghi li ca cc knh khng lin quan n nhau) 1: hot ng ng b gia cc knh 5 n 0 (vic xa hay ghi li ng b l c th xy ra)
7.4 Hot ng
7.4.1 Cc chc nng c bn Mi mt knh c mt thanh ghi TCNT v thanh ghi TGR. TCNT thc hin vic m ln, v cng c kh nng thc hin vic m t do (free-running), m tun hon, v m s kin bn ngoi. Mi thanh ghi TGR c th c s dng nh l mt thanh ghi input capture hay l mt thanh ghi output compare. Hot ng m (Counter operation): Khi mt trong nhng bit CST0 n CST5 c thit lp ln 1 trong thanh ghi TSTR, th thanh ghi TCNT ca knh tng ng s bt u m. Cc knh ny c th l mt b m t do (free-running), mt b m tun hon (periodic counter), 1. V d v qu trnh thit lp hot ng m: Hnh 7.3 s trnh by mt v d ca qu trnh thit lp hot ng m.
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Hnh 7.3 V d ca qu trnh thit lp hot ng m. [1] La chn xung ng h vi cc bit TPSC2 n TPSC0 trong thanh ghi TCR. ng thi la chn cnh xung ng h vi cc bit CKEG1 v CKEG0 trong thanh ghi TCR [2] Vi hot ng m tun hon, la chn thanh ghi TGR s dng cho vic xa gi tr m trong TCNT vi cc bit CCLR2 n CCLR0 trong thanh ghi TCR. [3] Xc nh thanh ghi TGR c la chn trong bc 2 l mt thanh ghi output compare thng qua thanh ghi TIOR [4] Thit lp chu k tun hon cho b m trong thanh ghi TGR la chn trong bc 2 (np gi tr tun hon vo thanh ghi TGR chn) [5] Thit lp bit CST trong thanh ghi TSTR ln 1 khi ng ch m. 2. hot ng m t do v hot ng m tun hon. Ngay lp tc sau khi reset, tt c b m trong TPU u c khi ng ch m t do. Khi cc bit lin quan trong thanh ghi TSTR c thit lp ln 1 th cc b m tng ng s c khi chy ch m t do. Khi m gi tr trong TCNT b trn (ngha l gi tr chuyn t HFFFF sang H0000), th bit TCFV (c trn) trong thanh ghi TSR c thit lp ln 1. Nu gi tr ca bit TCIEV tng ng trong thanh ghi TIER l 1 ti thi im ny, th cc yu cu ngt qung TPU s pht sinh. Sau khi trn th TCNT s bt u m li t H0000. Hnh 7.4 s minh ha hot ng m t do
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Hnh 7.4 Hot ng m t do Khi vic xa b m c la chn l hot ng compare match (so snh trng), th b m s thc hin vic m tun hon. Thanh ghi TGR s cha chu k ca vic m tun hon bng cch xa b m mi khi so snh gi tr trong TCNT bng vi gi tr trong thanh ghi TGR. Vic la chn thanh ghi TGR cho hot ng output compare ny thng qua cc bit CCLR2 n CCLR0 trong thanh ghi TCR. Nu gi tr ca cc bit TGIE trong thanh ghi TIER tng ng c thit lp l 1 vo thi im ny, th TPU s yu cu mt ngt qung. Sau khi mt hot ng so snh trng (compare match) th TCNT s c m li t H0000. Hnh 7.5 s minh ha hot ng m tun hon
Hnh 7.5 Hot ng m tun hon Dng sng xut bi hot ng compare match (so snh trng): TPU c th thc hin xut 0, 1, hay o trng thi cc ng xut khi xy ra compare match 1. V d v qu trnh thit lp cho mt dng sng xut thng qua compare match Hnh 7.6 s trnh by mt v d ca mt qu trnh thit lp cho mt dng sng xut thng qua mt compare match
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Hnh 7.6 V d ca mt qu trnh thit lp cho mt dng sng xut thng qua mt compare match [1] La chn gi tr khi to cho ng xut thng qua vic thit lp thanh ghi TIOR. Gi tr khi to s tn ti cho n khi hot ng compare match u tin xy ra. [2] Thit lp thi gian cho hot ng compare match trong thanh ghi TGR [3] Thit lp bit CST trong thanh ghi TSTR ln 1 bt u m 2. V d v dng sng ng xut Hnh 7.8 s trnh by mt v d v xut 0 v xut 1 Trong v d ny, thanh ghi TCNT c thit lp ch m t do, v thit lp xut ra ng xut l 1 khi m so snh trng vi thanh ghi TGRQ, v xut ra 0 khi m so snh trng vi thanh ghi TGRB. Khi m gi tr ng xut v gi tr xut ra l nh nhau th iu ny c ngha l gi tr ca chn xut khng i (xem hnh)
Hnh 7.7 V d v hot ng xut 0 v xut 1 Hnh 7.8 s trnh by mt v d v hot ng o tn hiu xut Trong v d ny th TCNT c thit lp l ch m tun hon (vi hot ng xa b m c thc hin bi hot ng so snh trng vi thanh ghi TGRB compare match B), v thit lp o tn hiu xut vi c hai hot ng compare match A v B.
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Hnh 7.8 V d v hot ng o tn hiu xut Chc nng input capture: Gi tr trong TCNT c th c chuyn sang (thu li) vo thanh ghi TGR thng qua tn hiu nhp t chn TIOC Tn hiu cnh ln, cnh xung, hay c hai c th c chn lm xung d tm. Vi cc knh 0, 1, 3 v 4, th n c th ch nh tn hiu xung ng h m ca mt knh khc hay cc tn hiu compare match lm vi tr ca ngun tn hiu input capture. Ch : Khi cc tn hiu xung ng h ca mt knh khc c s dng nh l cc tn hiu input capture cho cc knh 0 v 3, th P /1 khng nn c chn lm tn hiu xung ng h m m c s dng lm tn hiu nhp cho vic input capture. Hot ng input capture s khng xy ra nu nh P /1 c chn. 1. V d v qu trnh thit lp cho hot ng input capture Hnh 7.9 s cho thy mt v d v qu trnh thit lp cho hot ng input capture.
Hnh 7.9 V d v qu trnh thit lp cho hot ng input capture. [1] Thit lp thanh ghi TGR l thanh ghi input capture thng qua thanh ghi TIOR, v la chn ngun tn hiu input capture v cnh xung tn hiu (cnh ln, cnh xung, hay c hai) [2] Thit lp bit CST trong thanh ghi TSTR xung 1 bt u m. 2. V d v hot ng input capture Hnh 7.10 s trnh by mt v d v hot ng input capture Trong v d ny, c cnh ln v cnh xung u c la chn lm cnh xung tn hiu tch cc input capture ti chn TIOCA, v cnh xung c la chn lm cnh xung tn hiu tch cc cho hot ng input capture ti chn TIOCB, v b m c xa bi hot ng input capture trn TGRB.
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Hnh 7.10 V d v hot ng input capture 7.4.2 Hot ng ng b Trong ch hot ng ng b, th cc gi tr trong nhiu thanh ghi b m TCNT c th c ghi li (rewrite) mt cch ng thi (synchronous presetting). V n cng c th b xa mt cch ng thi (synchronous clearing) thng qua vic thit lp trong thanh ghi TCR. Cc knh 0 n 5 c th c ch nh cho hot ng ng b. V d v qu trnh thit lp hot ng ng b: Hnh 7.11 s ch ra mt v d v qu trnh thit lp hot ng ng b
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Hnh 7.11 V d v qu trnh thit lp hot ng ng b [1] Thit lp bit SYNC trong thanh ghi TSYR tng ng vi tng knh ln 1 ch ra rng knh s hot ng ch ng b. [2] Khi m thanh ghi b m TCNT ca bt k mt knh no c s dng trong ch ng b c ghi vo, th gi tr c ghi vo ny s lp tc c ghi vo thanh ghi b m TCNT ca nhng knh cn li [3] S dng cc bit CCLR2 n CCLR0 trong thanh ghi TCR xc nh cch thc xa thanh ghi b m TCNT (xa bng input capture hay output compare hay .) [4] S dng cc bit CCLR2 n CCLR0 trong thanh ghi TCR xc nh liu vic xa cc b m c ng b hay khng [5] Thit lp cc c CST trong thanh ghi TSTR ca cc knh lin quan ln 1 khi ng cc knh . V d v hot ng ng b: Hnh 7.12 s trnh by mt v d v hot ng ng b. Trong v d ny, hot ng ng b v ch m PWM 1 s c la chn cho knh 0 n 2, hot ng xa b m trong knh 0 l hot ng compare match TGRB_0, v hot ng xa b m cho knh 1 v 2 l hot ng xa ng b. Dng sng three-phase PWM xut ra cc chn TIOCA0, TIOCA1, v TIOCA2. ng thi, vic ghi li ng b v hot ng xa ng b bi hot ng TGRB_0 s c
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thc hin cho cc b m ca knh 0 n 2, v d liu nm trong thanh ghi TGRB_0 c s dng nh l chu k ca PWM. Chi tit tham kho cc ch PWM, chng 7.4.5.
Hnh 7.12 V d v hot ng ng b 7.4.3 Hot ng buffer Hot ng buffer, c cung cp cho knh 0 v 3, n cho php cc thanh ghi TGRC v TGRD ca cc knh ny c s dng nh l cc thanh ghi buffer. Hot ng buffer l khc nhau v ty thuc vo thanh ghi TGR c chn lm thanh ghi input capture hay compare match. Bng 7.31 Cc nhm thanh ghi c s dng trong hot ng buffer
Knh 0 Thanh ghi m rng TGRA_0 TGRB_0 3 TGRA_3 TGRB_3 TGRC_0 TGRD_0 TGRC_3 TGRD_3 Thanh ghi buffer
Khi thanh ghi TGR c s dng vi vai tr l thanh ghi output compare Khi m mt hot ng compare match xy ra, th gi tr trong thanh ghi buffer s c chuyn vo thanh ghi a dng Hot ng ny c minh ha trong hnh 7.13
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Hnh 7.13 Hot ng compare match buffer Khi thanh ghi TGR c s dng vi vai tr l thanh ghi input capture Khi m hot ng input capture xy ra, th gi tr trong thanh ghi TCNT c chuyn vo thanh ghi TGR (thanh ghi a dng) v gi tr trc c gi trong thanh ghi ny s chuyn sang thanh ghi buffer Hot ng ny s c minh ha trong hnh 7.14
Hnh 7.14 Hot ng input capture buffer V d v qu trnh thit lp hot ng buffer: Hnh 7.15 s trnh by mt v d v qu trnh thit lp hot ng buffer.
Hnh 7.15 V d v qu trnh thit lp hot ng buffer. [1] La chn thanh ghi TGR l thanh ghi input capture hay thanh ghi output compare thng qua thanh ghi TIOR. [2] Ch nh TGR cho hot ng buffer thng qua cc bit BFA v BFB trong thanh ghi TMDR [3] Thit lp bit CST trong thanh ghi TSTR ln 1 khi ng hot ng m V d cho hot ng buffer: 1. Khi m TGR l mt thanh ghi output compare Hnh 7.16 trnh by mt hot ng m trong ch m PWM 1 c chn cho knh 0, v hot ng buffer c chn cho thanh ghi TGRA v TGRC. Vic thit
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lp hot ng xa b m trong v d ny l bi hot ng compare match B, v xut 1 nu compare match A, v xut 0 nu compare match B. Khi m hot ng buffer c thit lp, th nu hot ng compare match A xy ra, th tn hiu xut s thay i v ng thi gi tr trong thanh ghi TGRCs c chuyn vo thanh ghi TGRA. Hot ng ny s lp i lp li mi khi hot ng compare match A xy ra. Chi tit xem thm chng 7.4.5 trong ch PWM
Hnh 7.16 V d ca hot ng buffer (1) 2. Khi m TGR c s dng nh l mt thanh ghi input capture Hnh 7.17 s trnh by hot ng m trong thanh ghi TGRA c chn lm thanh ghi input capture, v hot ng buffer c chn cho cp thanh ghi TGRA v TGRC. B m c xa bi hot ng input caputre TGRA, cnh tch cc ca tn hiu nhp input capture c la chn l c cnh ln v cnh xung ti chn TIOCA. Khi m hot ng buffer c thit lp, th nu gi tr trong thanh ghi TCNT s c lu vo TGRA khi c xut hin tn hiu tch cc input capture, v ng thi gi tr lu gi trong thanh ghi TGRA trc s c chuyn sang TGRC.
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Hnh 7.17 V d ca hot ng buffer (2) 7.4.4 Hot ng xp tng (cascaded operation) Trong hot ng cascaded, hai thanh ghi 16-bit ca hai ch khc nhau c s dng vi nhau to thnh mt b m 32-bit. Chc nng ny hot ng bng cch knh 1(knh 4) s m mi khi c mt tn hiu trn/thiu ca knh 2 (knh 5) thng qua vic thit lp cc bit TPSC2 n TPSC0 trong thanh ghi TCR. S thiu (underflow) xy ra ch khi 16-bit thp TCNT trong ch m phase Bng 7.32 trnh by cc cp thanh ghi c s dng cho ch xp tng (cascaded operation) Ch : khi m ch m phase c thit lp cho knh 1 hay 4 th vic thit lp xung b m l khng hp l v hot ng m mt cch c lp trong ch m phase (v thit lp cho 16 bit cao). Bng 7.32 Cc cp xp tng
T hp Knh 1 v 2 Knh 4 v 5 16 bit cao TCNT_1 TCNT_4 16 bit thp TCNT_2 TCNT_5
V d v qu trnh thit lp hot ng xp tng (cascaded): hnh 7.18 trnh by mt v d v qu trnh thit lp hot ng cascaded
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Hnh 7.18 V d v qu trnh thit lp hot ng cascaded [1] Thit lp cc bit TPSC2 n TPSC0 trong thanh ghi TCR ca knh 1 (knh 4) l B111 chn vic m trn/thiu ca knh 2 (knh 5) [2] Thit lp bit CST trong thanh ghi TSTR ca b m cao v b m thp ln 1 bt u m V d v hot ng cascaded: Hnh 7.19 minh ha hot ng m trn xung trn/thiu trn knh 2 cho knh 1, thanh ghi TGRA_1 v TGRA_2 c chn lm cc thanh ghi input capture, v cnh ln ca chn TIOC c chn lm tn hiu input capture. Khi mt cnh ln c pht sinh chn TIOCA1 v TIOCA2 xy ra ng thi, th 16 bit cao ca b m 32 bit s c chuyn sang thanh ghi TGRA_1, v 16 bit thp s c chuyn sang TGRA_2
Hnh 7.19 V d v hot ng cascaded (1) Hnh 7.20 minh ha hot ng m da vo s trn/thiu trong TCNT_2 ca TCNT_1, v ch m phase c thit lp cho knh 2. TCNT_1 c tng bi tn hiu trn TCNT_2 v gim bi tn hiu thiu (underflow) TNCT_2.
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Hnh 7.20 V d v hot ng cascaded (2) 7.4.5 Cc ch PWM Trong ch PWM, th dng sng PWM c xut ra cc chn xut. Xut 0, 1, hay o c th c chn lm tn hiu xut p ng li cc hot ng compare match ca mi TGR. Vic thit lp cc thanh ghi TGR c th xut ra mt dng sng PWM trong phm v lm vic t 0% n 100%. Vic ch nh hot ng compare match TGR l hot ng xa b m cho php chu k ca ch PWM c thit lp trong cc thanh ghi TGR ny. Tt c cc knh u c th thit lp ch PWM mt cch c lp. Hot ng ng b cng c th thit lp trong cc ch ny. C 2 ch PWM, nh din t di y. 1. Ch PWM 1 Tn hiu xut ca ch PWM c xut ra cc chn TIOCA v TIOCC bi tn hiu compare match ca cc cp TGRA vi TGRB v TGRC vi TGRD. Tn hiu xut c ch nh bi cc bit IOA3 n IOA0 v IOC3 n IOC0 trong thanh ghi TIOR v cc tn hiu xut trn cc chn TIOCA v TIOCC khi c hot ng compare match tng ng ti cc thanh ghi TGRA v TGRC. Tn hiu xut c ch nh bi cc bit IOB3 n IOB0 v IOD3 n IOD0 trong thanh ghi TIOR v cc tn hiu xut trn cc chn TIOCA v TIOCC khi c hot ng compare match tng ng ti cc thanh ghi TGRB v TGRD. Gi tr xut khi u l gi tr c thit lp trong TGRA v TGRC. Nu gi tr trong cc cp TGR l ging ht nhau, th gi tr xut s khng thay i mt khi c hot ng compare match xy ra. Trong ch PWM 1, th c th c ti a PWM xut 8 pha. 2. Ch PWM 2 Tn hiu xut PWM c sinh ra bng cch s dng mt thanh ghi TGR vi vai tr l chu k hot ng v cc thanh ghi TGR khc ng vai tr l cc thanh ghi cha chu k thc hin cng vic (thc hin nhim v). Tn hiu xut c ch nh thng qua thanh ghi TIOR v n s xut ra ng xut mt khi c mt hot ng compare match xy ra. Nh hot ng xa b m bi mt hot ng xa ng b compare math, m gi tr xut ca mi chn l gi tr khi u c thit lp bi thanh ghi TIOR.Nu gi tr thit lp trong thanh ghi chu k ca ch v gi tr trong cc thanh
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ghi cha chu k lm vic l ging nhau th tn hiu xut s khng thay i khi c hot ng compare match xy ra. Trong ch PWM 2, th ti a c th xut n n 15-phase PWM bi vic kt hp s dng vi cc hot ng ng b Cc chn xut trong ch PWM tng ng vi cc thanh ghi c trnh by trong bng 7.33 Bng 7.33 Cc thanh ghi xut PWM v cc chn xut
Cc chn xut Knh 0 Cc thanh ghi TGRA_0 TGRB_0 TGRC_0 TGRD_0 1 TGRA_1 TGRB_1 2 TGRA_2 TGRB_2 3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TGRA_4 TGRB_4 5 TGRA_5 TGRB_5 TIOCA5 TIOCA4 TIOCC3 TIOCA3 TIOCA2 TIOCA1 TIOCC0 Ch PWM 1 TIOCA0 Ch PWM 2 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5
Ch : Trong ch PWM 2, th tn hiu xut ca PWM l khng th xut ra thanh ghi TGR m cha chu k hot ng. V d v qu trnh thit lp ch PWM: Hnh 7.21 trnh by mt v d v qu trnh thit lp ch PWM.
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Hnh 7.21 V d v qu trnh thit lp ch PWM. [1] La chn xung ng h vi cc bit TPSC2 n TPSC0 trong thanh ghi TCR. ng thi la chn cnh xung tch cc vi cc bit CKEG1 v CKEG0 trong thanh ghi TCR. [2] S dng cc bit CCLR2 n CCLR0 trong thanh ghi TCR la chn thanh ghi TGR c s dng cho vic xa TCNT. [3] S dng thanh ghi TIOR xc nh thanh ghi TGR l mt thanh ghi output compare, v la chn ga tr ban u v gi tr s xut ra cho cc ng xut [4] Thit lp chu k trong thanh ghi TGR chn trong bc [2], v thit lp khong thi gian thc hin nhim v (duty) trong thanh ghi TGR cn li. [5] La chn ch PWM vi cc bit MD3 n MD0 trong thanh ghi TMDR [6] Thit lp bit CST trong thanh ghi TSTR ln 1 bt u m V d v hot ng ca ch PWM: Hnh 7.22 trnh by mt v d v hot ng ca ch PWM 1 Trong v d ny, th hot ng compare match TGRA c thit lp l hot ng xa b m, gi tr 0 s c thit lp cho gi tr khi u ban u v gi tr xut khi c tn hiu compare match TGRA, v gi tr 1 s c thit lp cho port xut khi c tn hiu compare match TGRB. Trong trng hp ny, th gi tr thit lp trong thanh ghi TGRA c s dng vi vai tr l chu k, v gi tr c thit lp trong thanh ghi TGRB ng vai tr l chu k thc hin nhim v (duty cycle).
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Hnh 7.22 V d hot ng ca ch PWM (1) Hnh 7.23 trnh by mt v d ca ch hot ng PWM 2 Trong v d ny, th hot ng ng b c thit lp cho knh 0 v 1, hot ng compare match trn TGRB_1 c thit lp l hot ng xa b m, v gi tr 0 s l gi tr khi u cho ng xut v gi tr 1 l gi tr xut mi khi c tn hiu compare match trn cc TGR cn li (TGRA_0 n TGRD_0, TGRA_1)., xut ra mt dng sng PWM 5-phase Trong trng hp ny, th gi tr trong thanh ghi TGRB_1 c s dng nh l chu k ca hot ng, v gi tr c thit lp cho cc thanh ghi TGR cn li ng vai tr l chu k thc hin nhim v (duty cycle)
Hnh 7.23 V d hot ng ca ch PWM (2) Hnh 7.24 trnh by cc v d v dng sng xut ca PWM vi chu k lm vic 0% v 100% trong ch PWM.
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Hnh 7.24 V d hot ng ca ch PWM (3) 7.4.6 Ch m phase: Trong ch m phase, th hai tn hiu nhp xung ng h ngoi (TCLKA vi TCLKB, TCLKC vi TCLKD) s c kim tra v quyt nh liu TCNT s tng hay gim n v. Ch ny c th thit lp cho cc knh 1, 2, 4, v 5. Khi m ch m phase c thit lp, th mt xung ng h ngoi c s dng nh l xung ng h m cho TCNT v vic m ln/xung khng ph thuc vo vic thit lp cc bit TPSC2 n TPSC0 v cc bit CKEG1 v CKEG0 trong thanh ghi TCR. Tuy nhin, cc bit CCLR1 v CCLR0 trong thanh ghi TCR, v cc thanh ghi TIOR, TIER, v TGR vn cn hp l, v cc chc nng input capture/compare match v ngt qung vn c th c s dng . Ch m ny c th s dng cho two-phase encoder pulse input.
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Khi m hot ng trn (overflow) xy ra trong khi TCNT ang m ln, th c TCFV trong thanh ghi TSR c thit lp, khi hot ng thiu (underflow). Trong khi TCNT ang m xung th c TCFU c thit lp Bit TCFD trong thanh ghi TSR l mt c hng m. Vic c c TCFD s cho thy liu b m ang m ln hay m xung. Bng 7.34 trnh by cc chn xung ng h bn ngoi tng ng vi cc knh trong ch m phase Bng 7.34 Cc chn tn hiu nhp xung ng h trong ch m phase
Cc chn xung ng h ngoi Cc knh Khi knh 1 hay 5 c thit lp ch m phase Khi knh 2 hay 4 c thit lp ch m phase A-phase TCLKA TCLKC B-phase TCLKB TCLKD
V d v qu trnh thit lp ch m phase: Hnh 7.25 trnh by mt v d ca qu trnh thit lp ch m phase.
Hnh 7.25 V d ca qu trnh thit lp ch m phase. [1] La chn ch m phase vi cc bit MD3 n MD0 trong thanh ghi TMDR. [2] Thit lp bit CST trong thanh ghi TSTR ln 1 bt u hot ng m Cc v d ca hot ng m phase: Trong ch m phase, th TCNT m ln hot m xung ty theo cc phase khc nhau gia hai xung clock ng h ngoi. C 4 ch m phase ty theo iu kin m. 1. Ch m phase 1 Hnh 7.26 trnh by mt v d ca hot ng m phase 1, v bng 7.35 l tng kt cc iu kin m ln/xung ca TCNT.
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Hnh 7.26 V d ca hot ng m phase 1 Bng 7.35 Cc iu kin m ln/xung ca TCNT trong ch m phase 1.
TCLKA (Cc knh 1 v 5) TCLKC (Cc knh 2 v 4) Mc cao Mc thp Mc cao Mc thp TCLKB (Cc knh 1 v 5) TCLKD (Cc knh 2 v 4) Mc thp Mc Cao Mc cao Mc thp m xung Hot ng m ln
Ghi ch: : Cnh ln : Cnh xung 2. Ch m phase 2 Hnh 7.27 trnh by mt v d ca hot ng m phase 2, v bng 7.36 s tng kt cc iu kin m ln/xung ca TCNT.
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TCLKA (Cc knh 1 v 5) TCLKC (Cc knh 2 v 4) Mc cao Mc thp Mc cao Mc thp TCLKB (Cc knh 1 v 5) TCLKD (Cc knh 2 v 4) Mc thp Mc Cao Mc cao Mc thp Hot ng Khng quan tm Khng quan tm Khng quan tm m ln Khng quan tm Khng quan tm Khng quan tm m xung
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TCLKA (Cc knh 1 v 5) TCLKC (Cc knh 2 v 4) Mc cao Mc thp Mc cao Mc thp TCLKB (Cc knh 1 v 5) TCLKD (Cc knh 2 v 4) Mc thp Mc Cao Mc cao Mc thp Hot ng Khng quan tm Khng quan tm Khng quan tm m ln m xung Khng quan tm Khng quan tm Khng quan tm
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TCLKA (Cc knh 1 v 5) TCLKC (Cc knh 2 v 4) Mc cao Mc thp Mc cao Mc thp TCLKB (Cc knh 1 v 5) TCLKD (Cc knh 2 v 4) Mc thp Mc Cao Mc cao Mc thp Khng quan tm m xung Khng quan tm m ln Hot ng
Ghi ch: : Cnh ln : Cnh xung V d vic ng dng ch m phase: Hnh 7.30 trnh by mt v d m trong ch m phase c thit lp cho knh 1, v knh 1 c kt hp vi knh 0 nhp servo motor 2-phase encoder pulses kim tra v tr v tc . Knh 1 c thit lp ch m phase, v cc cc xung gii m A-phase v Bphase c nhp vo t cc TCLKA v TCLKB. Hot ng xa TCNT ca knh 0 l hot ng compare match t TGRC_0, cc thanh ghi TGRA_0 v TGRC_0 c s dng cho chc nng compare match (dng xa TCNT_0 v dng lm tn hiu input capture cho TGRA_1 v TGRB_1) ng thi n c thit lp l chu k iu khin tc v v tr. TGRB_0 c s dng l
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thanh ghi input capture, TGRD_0 c s dng trong ch buffer, v n gi vai tr l thanh ghi buffer cho TGRB_0. Xung nhp b m knh 1 c ch nh l tn hiu input capture cho TGRB_0, v cc xung vi 2-phase encoder 4-multiplication pulses c kim tra. Thanh ghi TGRA_1 v TGRB_1 ca knh 1 c s dng l cc thanh ghi input capture, cc tn hiu compare match TGRA_0 v TGRC_0 ca knh 0 c chn l tn hiu ngun ca hot ng input capture cho knh 1, v gi tr m ln/xung cho vic iu khin chu k c lu gi.
Hnh 7.30 V d v vic ng dng ch m phase
7.5 Cc ngun ngt qung

C 3 loi ngun ngt qung ca TPU: input capture/compare match TGR, trn (overflow) TCNT, v thiu TCNT (underflow). Mi ngun ngt c mt c trng thi v bit cm/cho php, cho php sinh ra cc tn hiu yu cu ngt qung l cm hay cho php mt cch ring r. Khi mt tn hiu yu cu ngt qung c pht sinh, th trng c trng thi tng ng trong TSR c thit lp ln 1. Nu bit cm/cho php tng ng trong thanh ghi TIER c gi tr l 1 ti thi im , th mt ngt qung s c yu cu. Tn hiu yu cu ngt qung c xa bi vic xa c trng thi xung 0. Cc cp u tin lin quan c th c thay i bi b iu khin ngt, nhng u tin trong mt knh l c nh. Chi tit tham kho phn 5, b iu khin ngt. Bng 7.39 Ngt TPU
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Knh Tn
Ngun ngt
C ngt
S kch hot DTC
S kch hot DMAC C th Khng th Khng th Khng th Khng th C th Khng th Khng th Khng th C th Khng th Khng th Khng th C th Khng th Khng th Khng th
TGI0A TGI0B TGI0C TGI0D TCI0V
TGRA_0 input capture/compare match TGRB_0 input capture/compare match TGRC_0 input capture/compare match TGRD_0 input capture/compare match TCNT_0 trn (overflow) TGRA_1 input capture/compare match TGRB_1 input capture/compare match TCNT_1 trn (overflow) TCNT_1 thiu (underflow) TGRA_2 input capture/compare match TGRB_2 input capture/compare match TCNT_2 trn (overflow) TCNT_2 thiu (underflow) TGRA_3 input capture/compare match TGRB_3 input capture/compare match TGRC_3 input capture/compare match TGRD_3 input capture/compare match
TGFA_0 C th TGFB_0 C th TGFC_0 C th TGFD_0 C th TCFV_0 Khng th TGFA_1 C th TGFB_1 Khng th TCFV_1 Khng th TCFU_1 C th TGFA_2 C th TGFB_2 Khng th TCFV_2 Khng th TCFU_2 C th TGFA_3 C th TGFB_3 C th TGFC_3 C th TGFD_3 C th
TGI1A TGI1B TCI1V TCI1U
TGI2A TGI2B TCI2V TCI2U
TGI3A TGI3B TGI3C TGI3D
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TCI3V 4 TGI4A TGI4B TCI4V TCI4U 5 TGI5A TGI5B TCI5V TCI5U 6 TGI6A TGI6B TGI6C TGI6D TCI6V 7 TGI7A TGI7B TCI7V TCI7U 8 TGI8A TGI8B
TCNT_3 trn (overflow) TGRA_4 input capture/compare match TGRB_4 input capture/compare match TCNT_4 trn (overflow) TCNT_4 thiu (underflow) TGRA_5 input capture/compare match TGRB_5 input capture/compare match TCNT_5 trn (overflow) TCNT_5 thiu (underflow) TGRA_0 input capture/compare match TGRB_0 input capture/compare match TGRC_0 input capture/compare match TGRD_0 input capture/compare match TCNT_0 trn (overflow) TGRA_1 input capture/compare match TGRB_1 input capture/compare match TCNT_1 trn (overflow) TCNT_1 thiu (underflow) TGRA_2 input capture/compare match TGRB_2 input
TCFV_3 Khng th TGFA_4 C th TGFB_4 C th TCFV_4 Khng th TCFU_4 Khng th TGFA_5 C th TGFB_5 C th TCFV_5 Khng th TCFU_5 Khng th TGFA_0 C th TGFB_0 C th TGFC_0 C th TGFD_0 C th TCFV_0 Khng th TGFA_1 C th TGFB_1 Khng th TCFV_1 Khng th TCFU_1 C th TGFA_2 C th TGFB_2 Khng th
Khng th C th Khng th Khng th Khng th C th Khng th Khng th Khng th C th Khng th Khng th Khng th Khng th C th Khng th Khng th Khng th C th Khng th
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capture/compare match TCI8V TCI8U 9 TGI9A TGI9B TGI9C TGI9D TCI9V 10 TCNT_2 trn (overflow) TCNT_2 thiu (underflow) TGRA_3 input capture/compare match TGRB_3 input capture/compare match TGRC_3 input capture/compare match TGRD_3 input capture/compare match TCNT_3 trn (overflow) TCFV_2 Khng th TCFU_2 C th TGFA_3 C th TGFB_3 C th TGFC_3 C th TGFD_3 C th TCFV_3 Khng th TGFA_4 C th TGFB_4 C th TCFV_4 Khng th TCFU_4 Khng th TGFA_5 C th TGFB_5 C th TCFV_5 Khng th TCFU_5 Khng th Khng th Khng th C th Khng th Khng th Khng th Khng th C th Khng th Khng th Khng th C th Khng th Khng th Khng th
TGI10A TGRA_4 input capture/compare match TGI10B TGRB_4 input capture/compare match TCI10V TCNT_4 trn (overflow) TCI10U TCNT_4 thiu (underflow)
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TGI11A TGRA_5 input capture/compare match TGI11B TGRB_5 input capture/compare match TCI11V TCNT_5 trn (overflow) TCI11U TCNT_5 thiu (underflow)
Ch : Bng ny trnh by cc trng thi khi u ngay sau hot ng reset. Cc cp th t u tin ca cc knh c th thay i bi b iu khin ngt. Ngt input capture/compare match: Mt ngt qung c yu cu nu bit TGIE trong thanh ghi TIER c gi tr l 1 trong khi c TGF trong thanh ghi TSR c thit lp l 1 bi mt s kin input capture/compare match trn mt knh. Tn hiu yu cu ngt qung c xa bi vic xa c TGF xung 0. TPU c 16 tn hiu ngt input capture/compare match, cc knh 0 v 3 mi knh c 4 tn hiu, v cc knh cn li 1, 2, 4, v 5 mi knh c 2.
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Ngt trn (overflow): Mt ngt c yu cu nu bit TCIEV trong thanh ghi TIER c c gi tr l 1 v c TCFV trong thanh ghi TSR c thit lp l 1 bi mt s kin trang trn mt knh no . Tn hiu yu cu ngt qung c xa bi vic xa c TCFV xung 0. TPU c 6 tn hiu ngt qung trn, mi knh c 1 tn hiu. Ngt qung thiu (underflow): Mt ngt qung thiu s c yu cu nu bit TCIEU trong thanh ghi TIER c gi tr l 1 v c TCFU trong thanh ghi TSR c thit lp ln 1 bi mt s kin thiu (underflow) trn mt knh no . Tn hiu ngt qung s c xa bi vic xa c TCFU xung 0. TPU c 4 tn hiu ngt thiu, mi knh 1, 2, 4, v 5 c mt tn hiu.
7.6 S kch hot DTC

B iu khin truyn d liu DTC c th c kch hot bi ngt qung input capture/compare match TGR ca mt knh no . Chi tit tham kho phn 8, B lun chuyn d liu DTC C tng cng 16 ngt qung input capture/compare match ca TPU c th s dng nh l mt ngun kch hot b DTC, cc knh 0 v 3 mi knh c 4, v 2 cho mi knh 1, 2, 4, v 5.
7.7 S kch hot b iu khin DMA (DMAC)

B iu khin DMA c th c kch hot bi tn hiu ngt input caputre/compare match TGR ca mt knh no . Chi tit tham kho phn 7, b iu khin DMA (DMAC) C tng cng 6 tn hiu ngt input capture/compare match c th c s dng kch hot DMAC, 1 cho mi knh.
7.8 S kch hot trnh chuyn i A/D

Hot ng input capture/compare match ca cc knh thuc b nh thi 0 (unit 0). C th kch hot trnh chuyn i A/D (tnh nng ny khng c b nh thi 1 (unit 1)). Nu bit TTGE trong thanh ghi TIER c gi tr l 1 th khi c TGFA trong thanh ghi TSR c thit lp l 1 bi mt s kin input capture/compare match TGRA trn mt knh c bit, th mt yu cu khi ng trnh chuyn i A/D s c gi n trnh chuyn i A/D. Nu tn hiu khi ng trnh chuyn i ca TPU c la chn trn trnh chuyn i A/D, th trnh chuyn i A/D s khi ng. Trong b nh thi TPU, c tng cng 6 ngt input capture/compare match TGRA c th s dng lm ngun khi ng cho trnh chuyn i A/D, 1 cho mi knh. Trnh chuyn i A/D khng th c kch hot bi b nh thi 1 (unit 1).
7.9 Operation Timing (nh gi cc hot ng)

7.9.1 phn tch thi gian hot ng xut nhp (Input/Output Timing)
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Phn tch thi gian hot ng m TCNT: Hnh 7.31 trnh by s tng quan v mt thi gian trong hot ng m vi xung clock trong, v hnh 7.32 trnh by s tng quan v mt thi gian trong hot ng m vi xung clock ngoi.
Hnh 7.31 Tng quan v mt thi gian trong hot ng m vi xung clock trong
Hnh 7.32 Tng quan v mt thi gian trong hot ng m vi xung clock ngoi. Phn tch thi gian hot ng xut ca out compare: Mt tn hiu compare match s sinh ra trong trng thi cui cng trng thi m trong gi tr trong thanh ghi TCNT v thanh ghi TGR l ging nhau. Khi m mt tn hiu compare match c sinh ra, th gi tr xut c thit lp trong thanh ghi s l gi tr xut ti chn xut output compare (TIOC pin). Sau khi c s so trng ca TCNT v TGR, th tn hiu compare match vn cha xut ra cho n khi m xung ng h nhp ca TCNT c sinh ra (xem hnh)
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Hnh 7.33 Tng quan v thi gian trong hot ng xut output compare. Phn tch thi gian hot ng input capture: Hnh 7.34 Tng quan v mt thi gian ca cc tn hiu trong hot ng input capture.
Hnh 7.34 Tng quan v mt thi gian ca cc tn hiu trong hot ng input capture. Phn tch thi gian cho hot ng xa b m bi cc hot ng compare match/input capture: Hnh 7.35 trnh by s phn tch thi gian khi m b m c xa bi s kin compare match v hnh 7.36 trnh by s phn tch thi gian khi m b m c xa bi s kin input capture.
Hnh 7.35 Phn tch thi gian hot ng xa b m (compare match)
Hnh 7.36 Phn tch thi gian hot ng xa b m (input capture)
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Phn tch thi gian hot ng buffer: Hnh 7.37 v 7.38 trnh by s phn tch thi gian cc hot ng buffer
Hnh 7.37 Phn tch thi gian hot ng buffer (compare match)
Hnh 7.38 Phn tch thi gian hot ng buffer (input capture) 7.9.2 Phn tch thi gian tn hiu ngt: Phn tch thi gian hot ng thit lp c TGF trong trng hp compare match: Hnh 7.39 trnh by vic phn tch thi gian cho hot ng ca c TGF trong thanh ghi TSR bi s kin compare match, phn tch thi gian tn hiu ngt qung TGI.
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Hnh 7.39 Phn tch thi gian hot ng ngt TGI (compare match) Phn tch thi gian vic thit lp c TGF trong trng hp Input Capture: Hnh 7.40 trnh by qu trnh phn tch thi gian ca c TGF trong thanh ghi TSR bi s kin input capture, v phn tch thi gian tn hiu yu cu ngt TGI.
Hnh 7.40 Phn tch thi gian hot ng ngt TGI (input capture) Phn tch thi gian ca vic thit lp c TCFU/TCFV: Hnh 7.41 trnh by vic phn tch thi gian ca qu trnh thit lp c TCFV trong thanh ghi TSR bi hot ng trn (overflow), v vic phn tch thi gian ca tn hiu yu cu ngt TCIV. Hnh 7.42 trnh by vic phn tch thi gian ca qu trnh thit lp c TCFU trong thanh ghi TSR bi hot ng thiu (underflow), v vic phn tch thi gian ca tn hiu yu cu ngt TCIU.
Hnh 7.41 Phn tch thi gian ca hot ng ngt TCIV
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Hnh 7.42 Phn tch thi gian ca hot ng ngt TCIU Phn tch thi gian hot ng xa c trng thi: Sau khi mt c trng thi c c l 1 bi CPU, th n c xa bi vic ghi gi tr 0 vo n. Khi m b iu khin DTC hay DMAC c kch hot, th c c xa mt cch t ng. Hnh 7.43 trnh by s tng quan v mt thi gian ca cc tn hiu trong vic xa c trng thi bi CPU, v hnh 7.44 trnh by s tng quan v mt thi gian ca cc tn hiu trong vic xa c trng thi bi DTC hay DMAC.
Hnh 7.43 Phn tch thi gian ca hot ng xa c trng thi bi CPU Cc c trng thi v cc tn hiu yu cu ngt qung s b xa ng b vi P sau khi DTC hay DMAC khi ng, nh hnh 7.44. Nu mu thun xy ra cho vic xa c trng thi v tn hiu yu cu ngt qung v s kch hot nhiu hot ng truyn DTC hay DMAC, n s mt 5 chu k clock P cho hot ng xa chng, nh trnh by trong hnh 7.45. ln yu cu truyn tip theo s c s dng mt chu k di hn hoc kt thc qu trnh truyn hin ti hoc l mt chu k di 5 chu k P k t trng thi bt u. Ch rng trong qu trnh truyn DTC, th cc c trng thi c th b xa trong sut qu trnh xut a ch ch.
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Hnh 7.44 Phn tch thi gian cho hot ng xa c trng thi bi s kch hot DMAC (1)
Hnh 7.45 Phn tch thi gian cho hot ng xa c trng thi bi s kch hot DMAC (2)
7.10 Ch cch s dng

7.10.1 Module Stop Mode Setting: Hot ng ca TPU c th cm hay cho php vic s dng thanh ghi iu khin dng module. Vic thit lp gi tr ban u l vi hot ng ca CPU b dng. S truy xut thanh ghi c cho php bng vic xa ch dng module. Chi tit, tham kho phn 19, Ch Power-down. 7.10.2 Gii hn xung ng h nhp: rng ca xung ng h nhp t nht phi rng 1.5 trng thi trong trng hp tn hiu tch cc l n cnh (ch mt cnh tch cc: cnh ln hoc cnh xung), v 2.5 trng thi trong trng hp tn hiu tch cc c hai trng thi. TPU s hot ng khng ng nu nh rng xung nh hn cc rng buc ny. Trong ch m phase, phase khc nhau (phase difference) v phase trng nhau (phase overlap) gia hai tn hiu xung ng h nhp phi c rng t nht l 1.5 trng thi, v rng xung (pulse width) phi t nht l 2.5 trng thi. Hnh 7.46 trnh by cc iu kin ca xung ng h nhp trong ch m phase.
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Hnh 7.46 Phase khc (Phase Difference), phase trng (Overlap) v rng xung (Pulse Width) trong ch m phase 7.10.3 Cnh bo trong vic thit lp chu k Khi hot ng xa b m c thc hin bi s kin compare match, th TCNT s c xa trong trng thi cui cng trng thi m trong gi tr ca n trng vi gi tr ca thanh ghi TGR. Do , tn s thc s ca b m c cho bi cng thc sau:
f p N 1
f : Tn s b m P : Tn s hot ng N : Gi tr thit lp cho TGR 7.10.4 Mu thun gia hot ng ghi vo TCNT v hot ng xa b m Nu tn hiu xa b m c pht sinh vo trng thi T2 ca chu k ghi vo TCNT, th hot ng xa b m s c u tin hn v hot ng ghi vo TCNT s khng c thc hin. Hnh 7.47 s trnh by hot ng phn tch thi gian trong trng hp ny.
Hnh 7.47 Mu thun gia hot ng ghi TCNT v hot ng xa b m
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7.10.5 Mu thun gia hot ng ghi vo TCNT v hot ng tng b m: Nu hot ng tng xy ra trong trng thi T2 ca chu k ghi, th hot ng ghi vo TCNT s c u tin cao hn v TCNTs khng tng gi tr. Hnh 7.48 s trnh by biu thi gian ca hot ng ny.
Hnh 7.48 Mu thun gia hot ng ghi TCNT v hot ng tng b m 7.10.6 Mu thun gia hot ng ghi vo TGR v hot ng compare match Nu hot ng compare match xy ra trong trng thi T2 ca chu k ghi, th hot ng ghi TGR s c u tin hn v tn hiu compare match s b cm. Hot ng compare match cng khng xy ra ngay khi gi tr ghi vo TGR ging vi gi tr m TGR cha trc . Hnh 7.49 trnh by vic phn tch thi gian trong trng hp ny.
Hnh 7.49 Mu thun gia hot ng ghi TGR v hot ng compare match 7.10.7 Mu thun gia hot ng ghi vo thanh ghi buffer v hot ng compare match
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Nu mt hot ng compare match xy ra trong trng thi T2 ca chu k c, th gi tr chuyn vo TGR bi hot ng buffer s l gi tr ghi vo. Hnh 7.50 s trnh by tng quan thi gian ca cc tn hiu trong trng hp ny.
Hnh 7.50 Mu thun gia hot ng ghi vo thanh ghi buffer v hot ng compare match 7.10.8 Mu thun gia hot ng c TGR v hot ng input capture Nu tn hiu input capture c sinh ra trong trng thi T1 ca chu k c TGR, th d liu m c c s l d liu sau qu trnh input capture Hnh 7.51 trnh by tng quan v mt thi gian ca cc tn hiu trong trng hp ny
Hnh 7.51 Mu thun gia hot ng c TGR v hot ng input capture 7.10.9 Mu thun gia hot ng ghi vo TGR v hot ng input capure Nu tn hiu input capture c pht sinh trong trng thi T2 ca chu k c, th hot ng input capture s c u tin hn v hot ng ghi vo TGR s khng c thc hin.
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Hnh 7.52 trnh by s tng quan v mt thi gian ca cc tn hiu trong trng hp ny.
Hnh 7.52 Mu thun gia hot ng ghi vo TGR v hot ng input capture 7.10.10 Mu thun gia hot ng ghi vo thanh ghi bufer v hot ng input capture Nu tn hiu input capture c sinh ra trong trng thi T2 ca chu k ghi vo thanh ghi buffer, th hot ng buffer s c u tin hn v hot ng ghi vo thanh ghi buffer s khng c hot ng Hnh 7.53 s trnh by tng quan v cc tn hiu trong trng hp ny
Hnh 7.53 Mu thun gia hot ng ghi vo thanh ghi buffer v hot ng input capture 7.10.11 Mu thun gia hot ng trn/thiu (overflow/underflow) v hot ng xa b m
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Nu hot ng trn/thiu v hot ng xa b m xy ra ng thi th c TCFV/TCFU (c trn/c thiu) trong thanh ghi TSR s khng c thit lp v hot ng xa TCNT s c u tin hn. Hnh 7.54 trnh by hot ng phn tch thi gian khi hot ng compare match TGR c chn l hot ng xa b nh, v gi tr c np vo TGR l HFFFF.
Hnh 7.54 Mu thun gia hot ng trn v hot ng xa b m 7.10.12 Mu thun gia hot ng ghi vo TCNT v hot ng trn/thiu (overflow/underflow) Nu mt hot ng trn/thiu xy ra v hot ng tng/gim trong trng thi T2 ca chu k ghi vo TCNT, th hot ng ghi vo TCNT s c u tin hn v cc c TCFV/TCFV (c trn/c thiu) trong thanh ghi TSR s khng c thit lp. Hnh 7.55 trnh by hot ng phn tch thi gian khi c mt s mu thun gia vic ghi vo TCNT v hot ng trn
Hnh 7.55 Mu thun gia hot ng ghi vo TCNT v hot ng trn (overflow) 7.10.13 Cc chn xut nhp c nhiu chc nng
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Trong Vi iu khin ny th chn nhp TCLKA cn c s dng vi chc nng ca chn xut nhp TIOCC0, chn nhp TCLKB vi chn xut nhp TIOCD0, chn TCLKC vi TIOCB1, v TCLKD vi TIOCB2. Khi m mt tn hiu nhp xung ng h bn ngoi c nhp vo th tn hiu xut ca compare match s khng c thc hin t cc chn c nhiu chc nng ny. 7.10.14 Ngt qung v ch dng module Nu CPU vo ch dng module khi m mt ngt qung c yu cu th khng th xa ngun ngt qung ca CPU, cc ngun kch hot DMAC hay DTC. Chnh v vy m cc ngt qung s b cm trc khi vo ch dng module.
242
Chng 8 B chuyn tun t - s (A/D)

Vi iu khin ny c hai b chuyn A/D 10 bit k tip ging nhau (b 0 v b 1) c th cho php ta la chn ti 16 knh ng nhp tun t. Hnh 8.1 v 8.2 ln lt l s khi ca cc b 0 v b 1. Phn di y s m t v b 0, b 1 cng c cng chc nng nh vy.
8.1
Cc c im
phn gii 10 bit 16 knh ng nhp (8 cho b 0 v 8 cho b 1) Thi gian chuyn i: 7.4 s mi knh (hot ng 35MHz) Hai ch hot ng: o Ch n: Chuyn i A/D n knh o Ch scan: Chuyn i A/D lin tc trn 1 n 4 knh, hoc trn 1 n 8 knh. 16 thanh ghi d liu (8 thanh ghi cho b 0 v 8 cho b 1). Kt qu chuyn A/D s c lu trong mt thanh ghi 16 bit mi knh. Chc nng gi v ly mu Ba cch khi ng b chuyn i: Khi ng bng phn mm, khi ng bng b xung nh th 16 bit (TPU), hay bng mt tn hiu ngoi. Ngun ngt qung: Yu cu ngt qung kt thc b chuyn A/D c th c pht ra. Ch dng module c th c thit lp
243
Hnh 8.1: S khi ca b chuyn A/D (b 0 / AD_0)
244
Hnh 8.2: S khi ca b chuyn A/D (b 1 / AD_1)
8.2
Cc chn nhp/xut
Bng 8.1 Cu hnh chn

B Vit tt 0 AD_0 Tn chn Chn nhp tun t 0 Chn nhp tun t 1 Chn nhp tun t 2 Chn nhp tun t 3 Chn nhp tun t 4 Chn nhp tun t 5 K hiu AN0 AN1 AN2 AN3 AN4 AN5 I/O Chc nng
Nhp Ng nhp tun t Nhp Nhp Nhp Nhp Nhp
245
Chn nhp tun t 6 Chn nhp tun t 7 Chn nhp trigger ngoi A/D 0 Chn cp ngun 0 1 AD_1 Chn nhp tun t 8 Chn nhp tun t 9
AN6 AN7
Nhp Nhp
ADTRG0 Nhp Ng nhp trigger ngoi khi ng b A/D AVCC0 AN8 AN9 Nhp Cp ngun cho khi tun t Nhp Ng nhp tun t Nhp Nhp Nhp Nhp Nhp Nhp Nhp
Chn nhp tun t 10 AN10 Chn nhp tun t 11 AN11 Chn nhp tun t 12 AN12 Chn nhp tun t 13 AN13 Chn nhp tun t 14 AN14 Chn nhp tun t 15 AN15 Chn nhp trigger ngoi A/D 1 Chn cp ngun 1 Chung Chn t (ground)
ADTRG1 Nhp Ng nhp trigger ngoi khi ng b A/D AVCC1 AVSS Nhp Cp ngun cho khi tun t Nhp Tip t cho khi tun t
8.3
M t thanh ghi
B chuyn A/D gm cc thanh ghi sau: Cc thanh ghi cho b 0 v b 1 u c cng chc nng. Trong m t di y, cc thanh ghi AN8 ti AN15 s tng ng vi AN0 ti AN7. __ B 0 (AD_0) Thanh ghi d liu A/D A_0 (ADDRA_0) Thanh ghi d liu A/D B_0 (ADDRB_0) Thanh ghi d liu A/D C_0 (ADDRC_0) Thanh ghi d liu A/D D_0 (ADDRD_0) Thanh ghi d liu A/D E_0 (ADDRE_0)
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Thanh ghi d liu A/D F_0 (ADDRF_0) Thanh ghi d liu A/D G_0 (ADDRG_0) Thanh ghi d liu A/D H_0 (ADDRH_0) Thanh ghi iu khin/trng thi A/D 0 (ADCSR_0) Thanh ghi iu khin A/D 0 (ADCR_0) __ B 1 (AD_1) Thanh ghi d liu A/D A_1 (ADDRA_1) Thanh ghi d liu A/D B_1 (ADDRB_1) Thanh ghi d liu A/D C_1 (ADDRC_1) Thanh ghi d liu A/D D_1 (ADDRD_1) Thanh ghi d liu A/D E_1 (ADDRE_1) Thanh ghi d liu A/D F_1 (ADDRF_1) Thanh ghi d liu A/D G_1 (ADDRG_1) Thanh ghi iu khin/trng thi A/D 1 (ADCSR_1) Thanh ghi iu khin A/D 1 (ADCR_1) B chuyn A/D c mt thanh ghi iu khin pull-down MOS cho cc chn nhp tun t. Thanh ghi iu khin pull-down port tun t (APPDCR). 8.3.1 Thanh ghi d liu A/D t A ti H (ADDRA ti ADDRH) C 8 thanh ghi ADDR 16 bit ch c, ADDRA ti ADDRH, dng cha kt qu ca b chuyn A/D. Cc thanh ghi ADDR s cha kt qu chuyn ca tng knh tng ng, c m t bng 8.2 D liu 10 bit chuyn c lu cc bit 15 ti 6. 6 bit d liu thp lun c c l 0. Bus d liu gia b chuyn A/D v CPU c rng 16 bit. D liu c th c c trc tip t CPU. ADDR khng c truy xut tng 8 bit mt m phi truy xut c 16 bit.
Bng 8.2
Knh nhp tun t v thanh ghi ADDR tng ng

Thanh ghi d liu A/D cha kt qu tr v ADDRA
Knh nhp tun t AN0
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AN1 AN2 AN3 AN4 AN5 AN6 AN7
ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH
8.3.2 Thanh ghi iu khin/trng thi A/D (ADCSR) ADCSR iu khin tc v chuyn A/D.
Ch : *Ch ghi c 0 vo y, xa c
Bit Tn bit 7 ADF Gi tr R/W khi to 0 M t
(R/W)* C kt thc A/D Mt c trng thi bo hiu kt thc chuyn A/D. [iu kin lp] _ Khi vic chuyn A/D kt thc trong ch n _ Khi vic chuyn A/D kt thc tt c cc knh ch nh trong ch scan. [iu kin xa] _ Khi 0 c vit sau khi c ADF = 1 _ Khi DTC hoc DMAC c kch hot bi mt ngt qung ADI v ADDR c c
ADIE
R/W
Cho php ngt qung A/D Khi bit ny c lp ln 1, ngt qung ADI bi ADF s c cho php.
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ADST
R/W
Bt u A/D Xa bit ny xung 0 s dng vic chuyn A/D, v b chuyn A/D chuyn sang trng thi ch. Lp bit ny ln 1 s bt u vic chuyn A/D. Trong ch n, bit ny s c t ng xa xung 0 khi vic chuyn A/D trn knh c ch nh kt thc. Trong ch scan, vic chuyn A/D tip tc ln lt trn cc knh c ch nh cho ti khi bit ny c xa bi phn mm, mt reset, hoc vic chuyn ti trng thi standby phn mm hoc chuyn ti ch standby phn mm, hoc ch dng module.
--
R/W
Khng dng y l bit ch c v khng th sa cha.
3 2 1 0
CH3 CH2 CH1 CH0
0 0 0 0
R/W R/W R/W R/W
Chn knh 3 ti 0 Chn ng nhp tun t i chung vi bit SCANE v SCANS trong ADCR. Khi SCANE = 0 v SCANS = X 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: AN4 0101: AN5 0110: AN6 0111: AN7 1XXX: Cm thit lp Khi SCANE = 1 v SCANS = 0 0000: AN0 0001: AN0 v AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN4 0101: AN4 v AN5
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0110: AN4 to AN6 0111: AN4 to AN7 1XXX: Cm thit lp Khi SCANE = 1 v SCANS = 1 0000: AN0 0001: AN0 v AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN0 to AN4 0101: AN0 to AN5 0110: AN0 to AN6 0111: AN0 to AN7 1XXX: Cm thit lp
8.3.3 Thanh ghi iu khin A/D (ADCR) ADCR cho php vic chuyn A/D c khi ng bi mt tn hiu ngoi
Bit 7 6
Tn bit TRGS1 TRGS0
Gi tr R/W M t khi to 0 0 R/W R/W Chn b m 1 v 0 Cc bit ny cho php hoc cm vic bt u chuyn A/D bi mt tn hiu trigger. 00: Chuyn A/D bt u bi tn hiu ngoi b cm 01: Chuyn A/D bt u bi tn hiu ngoi t TPU c cho php 10: Cm thit lp 11: Chuyn A/D bt u bi chn ADTRG c cho php*
5 4
SCANE SCANS
0 0
R/W R/W
Ch scan Cc bit ny chn ch hot ng chuyn A/D.
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0X: Ch n 10: Ch scan. Vic chuyn A/D c thc hin lin tc cho cc knh 1 ti 4. 11: Ch scan. Vic chuyn A/D c thc hin lin tc cho cc knh 1 ti 8. 3 2 CKS1 CKS0 0 0 R/W R/W Chn clock 1 v 0 Cc bit ny thit lp thi gian chuyn A/D. Lp cc bit CKS1 v CKS0 ch khi no vic chuyn A/D dng (ADST = 0). 00: Thi gian chuyn A/D= 530 chu k (ti a) 01: Thi gian chuyn A/D= 266 chu k (ti a) 10: Thi gian chuyn A/D= 134 chu k (ti a) 11: Thi gian chuyn A/D= 68 chu k (ti a) 1 0 -0 0 R R Khng dng. Cc bit ny ch c c.
251
8.3.4 Thanh ghi iu khin Pull-down port tng t (APPDCR) Thanh ghi APPDCR iu khin pull-down cho tn hiu nhp tng t t cc chn
Bit Tn bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Gi tr R/W khi to R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
M t Cc bit ny iu khin pull-down cho cc tn hiu tng t nhp. 0: Pull-down MOS: tt 1: Pull-down MOS: m
AN15PD 0 AN14PD 0 AN13PD 0 AN12PD 0 AN11PD 0 AN10PD 0 AN9PD AN8PD AN7PD AN6PD AN5PD AN4PD AN3PD AN2PD AN1PD AN0PD 0 0 0 0 0 0 0 0 0 0
8.4
Hot ng
B chuyn A/D hot ng vi phn gii xp x 10 bit. N c hai ch hot ng: ch n v ch scan. Khi chuyn ch hot ng hoc knh nhp tun t, ngn nga hot ng khng chnh xc, trc ht ta phi xa bit ADST trong thanh ghi ADCSR ngng vic chuyn A/D. Bit ADST c th c lp ln 1 cng lc vi vic chuyn ch hot ng hoc knh nhp tun t. 8.4.1 Ch n
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Trong ch n, vic chuyn A/D ch c thc hin mt ln trn ng nhp tun t l mt knh n c ch nh. 1. Vic chuyn A/D cho knh c chn bt u khi bit ADST c lp ln 1 bi phn mm hoc tn hiu ngoi. 2. Khi vic chuyn A/D hon thnh, kt qu s c tr v cho thanh ghi d liu A/D tng ng ca knh. 3. Khi vic chuyn A/D hon thnh, bit ADS trong ADCSR c lp ln 1. Nu bit ADIE c lp ln 1 trong cng thi im, mt yu cu ngt qung ADI s c pht ra. 4. Bit ADST vn l 1 trong khi chuyn A/D, v n t ng c xa v 0 khi vic chuyn A/D kt thc. B chuyn A/D vo trng thi ch. Nu bit ADST c xa v 0 trong khi ang chuyn, vic chuyn i s dng ngay lp tc v b chuyn vo trng thi ch.
Hnh 8.3 V d hot ng ca b chuyn A/D (Ch n, Chn knh 1) 8.4.2 Ch scan Trong ch scan, vic chuyn A/D s c thc hin ln lt trn 4 hoc 8 knh ng nhp tun t. 1. Khi bit ADST trong thanh ghi ADCSR c lp ln 1 bi phn mm, TPU, hoc mt tn hiu ngoi, vic chuyn A/D s bt u trn knh u tin ca nhm. Vic chuyn A/D lin tip ti 4 knh (SCANE v SCANS = B10) hoc ti 8 knh (SCANE v SCANS = B11) c th c chn. Khi vic chuyn A/D lin tip c thc hin trn 4 knh, chuyn A/D bt u t AN0 khi CH3 v CH2 = B00, trn AN4 khi CH3 v CH2 = B01, trn AN8 khi CH3 v CH2 = B10, trn AN12
253
khi CH3 v CH2 = B11. Khi vic chuyn A/D lin tip trn 8 knh, vic chuyn A/D bt u trn AN0 khi CH3 = B0 v trn AN8 khi CH3 = B1. 2. 3. Khi vic chuyn A/D trn tng knh c hon thnh, kt qu s c ghi vo cc thanh ghi ADDR tng ng ca tng knh. Khi vic chuyn A/D trn tng knh c hon thnh, bit ADF trong ADCSR c lp ln 1. Nu bit ADIE c lp ln 1 trong cng thi im, mt yu cu ngt qung ADI c pht ra. Vic chuyn A/D trn knh th nht ca nhm c bt u li.
4. Bit ADST khng c xa t ng, v bc [2] ti [3] s c lp li cho ti khi bit ADST vn cn l 1. Khi bit ADST c xa v 0, vic chuyn A/D s ngng v b chuyn A/D i vo trng thi ch. Nu bit ADST c lp ln 1, b chuyn s bt u li t knh u tin.
Hnh 8.4 V d vic chuyn A/D (Ch scan, 3 knh (AN0 ti AN2) c chn) 8.4.3 Ly mu ng nhp v thi gian chuyn i A/D B chuyn A/D c mt mch ly v gi mu gn trong. B chuyn A/D s ly mu tn hiu nhp tun t khi thi gian tr khi ng chuyn A/D chm dt sau khi bit ADST trong ADCSR c lp ln 1, sau bt u vic chuyn A/D. Hnh 8.5 cho thy vic nh thi chuyn A/D. Bng 8.3 cho thy thi gian chuyn A/D. Nh thy trong hnh 8.5, thi gian chuyn A/D (tCONV) bao gm tD v thi gian ly mu nhp (tSPI). di ca tD ty thuc vo thi gian ghi ADCSR. Tng thi gian chuyn v th m bin i trong khong xc nh bng 8.3.
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Hnh 8.5 A/D Thi gian chuyn i Trong ch scan, nhng gi tr trong bng 8.3 c p dng cho thi gian chuyn i u tin. Cc gi tr trong bng 8.4 c p dng cho cc chuyn i k tip. Trong tng trng hp, bit CKS1 v CKS0 trong ADCR nn c lp thi gian chuyn i nm trong khong c ch nh bi c im chuyn i A/D. Bng 8.3 Cc c im chuyn i A/D (Ch n)
Ch : Gi tr trong bng l s lng chu k. Bng 8.4 Cc c im chuyn A/D (Ch scan)
8.4.4 nh thi tn hiu ngoi B chuyn A/D c th c khi ng t bn ngoi. Khi cc bit TRGS1 v TRGS0 c lp ln 1 trong thanh ghi ADCR, mt tn hiu ngoi s c nhp t
255
chn ADTRG. Vic chuyn A/D khi ng khi bit ADST trong ADCSR c lp ln 1 bi cnh xung ca chn ADTRG. Cc tc v khc, trong c ch n v scan, l ging nhau khi bit ADST c lp ln 1 bi phn mm. Hnh 8.6 cho thy vic nh thi.
Hnh 8.6 nh thi ng nhp ngoi
8.5
Ngun ngt qung
B chuyn A/D pht ra ngt qung kt thc chuyn A/D (ADI) khi vic chuyn A/D kt thc. Lp bit ADIE ln 1 khi bit ADF trong ADCSR c lp ln 1 sau khi chuyn A/D hon tt s cho php yu cu ngt qung ADI. B iu khin DTC hay DMA c th c kch hot bi ngt qung ADI. Vic DTC hoc DMAC c d liu c chuyn i (p ng yu cu ca ADI) s khin b chuyn A/D tip tc lm vic m khng cn i phn mm. Bng 8.5 Ngun ngt qung b chuyn A/D Ngun ngt qung C ngt Kch hot Kch hot DTC DMAC C th C th C th C th
B Vit tt
0 1
ADI0 Kt thc chuyn A/D_0 ADI1 Kt thc chuyn A/D_1
ADF ADF
8.6
nh ngha chnh xc vic chuyn A/D

Vi iu khin ny c nhng nh ngha chnh xc vic chuyn A/D nh sau:
phn gii S lng m xut dng s ca b chuyn A/D Sai s lng t lch vn c ca b chuyn A/D, c cho l LSB(xem Hnh 8.7). Sai s offset lch ca gi tr in p ng nhp tun t vi gi tr l tng ca b chuyn A/D khi ng xut s thay i t gi tr in p ti thiu B0000000000 (H000) ti B0000000001 (H001) (xem hnh 8.8).
256
Sai s ti a lch ca gi tr in p ng nhp tun t so vi gi tr l tng ca b chuyn A/D khi tn hiu xut s thay i t B'1111111110 (H'3FE) ti B'1111111111 (H'3FF) (xem Hnh 8.8). Sai s phi tuyn tnh Sai s tng ng vi gi tr l tng ca b chuyn A/D gia in p 0 v in p ti a. Khng bao gm sai s offset, sai s ti a, hay sai s lng t (xem hnh 8.8). chnh xc tuyt i L sai s gia gi tr s v gi tr nhp tun t. Bao gm sai s offset, sai s ti a, sai s lng t v sai s phi tuyn tnh.
Hnh 8.7 Cc nh ngha chnh xc vic chuyn A/D
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Hnh 8.8 Cc nh ngha chnh xc vic chuyn A/D
8.7 Chc nng pull-down ca port tng t

Mi port tng t u c mt pull-down (ko xung). Bng cch thit lp cc bit AN15PD n AN0PD trong thanh ghi APPDCR ln 1, th chc nng pull-down trong chn tng ng s c m. Khi m hiu in th c p vo port tng t t mt mch bn ngoi (external circuit), th s kt ni gia port tng t v mch bn ngoi c th c kim tra bi trnh chuyn i A/D.
Hnh 8.9 S ca chc nng pull-down port tng t
8.8
Ch khi s dng
8.8.1 Thit lp ch ngng module Hot ng ca b chuyn A/D c th c cm hoc cho php s dng thanh ghi iu khin dng module. Thit lp khi u l ngng b chuyn A/D hot
258
ng. Truy cp thanh ghi c cho php bng cch xa ch ngng module. bit thm chi tit, xin xem phn 19. 8.8.2 Tr khng ngun tn hiu cho php Ng nhp tun t ca vi iu khin ny c thit k chnh xc chuyn i c bo m cho tr khng ngun tn hiu di 5 k. c im ny cung cp tnh nng np t cho mch nhp ly mu-gi trong thi gian ly mu; nu tr khng sensor ca ng xut vt qu 5 k, np t s khng m bo c chnh xc cho vic chuyn d liu. Tuy nhin, nu mt t ln c cung cp ngoi cho vic chuyn i trong ch n, ti ng nhp s ch bao gm in tr ng nhp ni 10k, v tr khng ngun tn hiu s b b qua. Mc d vy, bi v mt hiu ng lc low-pass c trong trng hp ny, tn hiu tun t cng khng c gn km theo h s vi sai ln (v d 5mV/us hoc ln hn) (xem hnh 8.10). Khi chuyn i 1 tn hiu tun t tc cao hay chuyn i trong ch scan, cn phi thm mt b m tr khng thp
Hnh 8.10 V d mch nhp tun t 8.8.3 nh hng ca chnh xc tuyt i Thm in dung ln nn c th gy nhiu trn nn dn ti vic suy gim chnh xc tuyt i. Hy chc chn rng n c ni vi mt nn n nh nh AVss. Cng cn phi chc rng tn hiu s s khng nh hng ti b lc, v b lc khng hot ng ging mt n ten. 8.8.4 Thit lp bin ca chn cp ngun v cc chn khc Nu iu kin di y khng c tha, tin cy ca Vi iu khin ny c th b gim xung. Bin in p ng nhp tun t in p ca ng nhp tun t ANn trong qu trnh chuyn A/D cn nm trong khong AVss VAN AVcc0 and AVss VAN AVcc1. Mi lin h gia AVcc0, AVcc1, AVss v Vcc, Vss
259
Thit lp AVcc0 = Vcc 0.3 V, AVcc1 = Vcc 0.3 V, v AVss = Vss. Nu b chuyn A/D khng c s dng, thit lp AVcc0 = Vcc, AVcc1 = Vcc, v AVss = Vss. 8.8.5 Cc ch v thit k board Trong vic thit k board, mch s v mch tng t cn phi c cch ly ln nhau cng nhiu cng tt, mch tn hiu s v mch tn hiu tng t cng nn c cch xa nhiu nht c th. Khng lm c nh vy, kt qu c th s l cc mch tun t s hot ng sai, gy ra bi t cm, tc ng nghch ti gi tr vic chuyn A/D. Mch s cn c cch ly vi cc ng nhp tun t (AN0 ti AN15) v ngun tun t (AVcc0 v AVcc1) bi ground (AVss). Hn na, AVss cng nn c ni ti nn n nh (Vss) trn board. 8.8.6 Cc ch v bin php chng nhiu Mt mch bo v c ni vo chng thit hi gy ra bi in p bt thng nh vic tng in p qu mc - ng nhp tun t (AN0 ti AN15) cn c ni gia AVcc0, AVcc1 v AVss nh trong hnh 8.11. Hn na, t r ni gia AVcc0 v AVcc1 v t lc ni gia chn AN0 ti AN15 phi c ni vi AVss. Nu c mt t lc c ni, dng nhp cc chn AN0 ti AN15 t trung bnh, v li c th xy ra. Ngoi ra, khi vic chuyn A/D c din ra u n, nh trong ch scan, nu dng np ngng np na bi in dung ca mch gi v ly mu trong b chuyn A/D vt qu dng nhp thng qua tr khng ng nhp, mt li in p ng nhp c th c pht sinh. Cn thn xem xt l cn thit khi quyt nh cc hng s mch.
Hnh 8.11 V d v mch bo v ng nhp tun t Bng 8.6 Cc c im chn tun t Mc Ti thiu Ti a n v
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in dung ng nhp tun t Tr khng ngun tn hiu cho php
---
20 5
pF k
Hnh 8.12 Mch tng ng ng nhp tun t 8.8.7 Chc nng gi ng nhp A/D trong Ch standby phn mm Khi con vi iu khin ny bc vo ch standby phn mm vi vic chuyn A/D c cho php, vic chuyn A/D vn c duy tr, v dng tun t s bng vi trc khi standby. Nu dng cp ngun tun t b ct gim trong ch standby, xa ADST, TRGS1, v TRGS0 s ngt vic chuyn A/D.
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Chng 9 B iu khin DMA (DMAC)

Thit b ny bao gm mt b iu khin DMA 4 knh (DMAC).
9.1 Cc tnh cht

C th truy xut khng gian a ch ti a 4-G byte b nh C th thit lp phng thc truyn d liu theo byte, word, hay long word C th thit lp vic truyn d liu ti a n 4-G byte (4,292,967,295) H tr ch free-running ch m khng cn thit lp kch thc khi d liu lun chuyn. Phng thc kch hot DMAC c th l: auto-request (t ng yu cu), module ngt on-chip, hay mt yu cu t bn ngoi Yu cu t ng (auto-request): CPU kch hot (c th la chn gia cycle stealing hoc burst access) Module ngt on-chip: Cc ngt qung do cc module ngoi vi on-chip c th c ng vai tr nh l cc ngun kch hot DMAC. Yu cn t bn ngoi*: Mt tn hiu thp hay mt cnh xung c p vo chn DREQ c th c s dng nh l mt ngun kch hot DMAC. C th la chn ch a ch i hay a ch n Ch a ch i: c a ch ngun v a ch ch u c ch nh bi cc a ch c th (thanh ghi DSAR v DDAR) Ch a ch n: a ch ngun hoc l a ch ch c ch nh bi tn hiu ch nh (tn hiu DACK ) v a ch cn li c ch nh bi thanh ghi a ch (thanh ghi DSAR hay DDAR). Cc ch truyn d liu c th c la chn l: bnh thng, lp (repeat), hay truyn theo khi (block). Ch truyn d liu bnh thng: Mt byte, mt word hay mt longword d liu s c truyn trong mt ln truyn n v (mt hot ng truyn) Ch lp: Mt byte, mt word hay mt longword d liu s c lun chuyn trong mt ln truyn n v (mt hot ng truyn) Khi ln lun chuyn phi nh hn 65536 (65536 byte/ word/ longword). Ch lun chuyn theo khi: mt khi d liu s c lun chuyn khi c mt tn hiu lun chuyn d liu (chuyn c khi ch trong mt ln ch cn c mt tn hiu lun chuyn). Kch thc ca mt khi d liu c th ln n 65536 byte/word/longword.
262
Cho php chc nng m rng vng lp, vng m lp li a ch trong mt vng c nh s dng a ch truyn vi cc bit cao c c nh. Vng lp m rng ca ngun v ch c th c thit lp ti a n 128Mbyte (27 bit). Vic cp nht a ch c th l hnh thc a ch c nh, cng thm offset, hay s tng hay gim 1, 2, hay 4 n v ca a ch a ch cp nht bi vic cng offset cho php truyn d liu t nhng a ch m nm khng lin tc (ri rc). D liu word hay longword c th c chuyn n mt a ch m khng tng ng vi kch thc d liu theo word hay longword (c th vng a ch bt u t mt a ch l i vi d liu word hay mt a ch c dng 4n + 2 i vi a ch longword) C hai loi ngt qung c th xy ra: Ngt qung kt thc vic lun chuyn c pht sinh khi m s lng d liu c ch nh bi b m truyn c truyn ht. Ngt qung thot khi vic lun chuyn c sinh ra khi m tng kch thc cn li l nh hn tng kch thc d liu lun chuyn, hoc khi m kch thc lp ca d liu lun chuyn c hon thnh, hay khi m vng lp m rng b trn. Ch : * Ch yu cu ngt ngoi v a ch n khng c h tr trong H8SX/1582 Mt s khi ca DMAC:
263
Hnh 9.1 S khi ca DMAC
9.2 Cc c t thanh ghi

B iu khin DMAC c cc thanh ghi sau. Knh 0: Thanh ghi a ch ngun DMAC (DSAR_0) Thanh ghi a ch ch ca DMAC (DDAR_0) Thanh ghi a ch offset ca DMAC (DOFR_0) Thanh ghi bin m ca DMAC (DTCR_0) Thanh ghi kch thc khi d liu ca DMA (DBSR_0) Thanh ghi iu khin ch ca DMA (DMDR_0) Thanh ghi iu khin a ch ca DMA (DACR_0) Thanh ghi la chn yu cu ngt qung ca DMA (DMRSR_0) Knh 1: Thanh ghi a ch ngun DMAC (DSAR_1) Thanh ghi a ch ch ca DMAC (DDAR_1) Thanh ghi a ch offset ca DMAC (DOFR_1) Thanh ghi bin m ca DMAC (DTCR_1) Thanh ghi kch thc khi d liu ca DMA (DBSR_1) Thanh ghi iu khin ch ca DMA (DMDR_1) Thanh ghi iu khin a ch ca DMA (DACR_1) Thanh ghi la chn yu cu ngt qung ca DMA (DMRSR_1) Knh 2: Thanh ghi a ch ngun DMAC (DSAR_2) Thanh ghi a ch ch ca DMAC (DDAR_2) Thanh ghi a ch offset ca DMAC (DOFR_2) Thanh ghi bin m ca DMAC (DTCR_2) Thanh ghi kch thc khi d liu ca DMA (DBSR_2) Thanh ghi iu khin ch ca DMA (DMDR_2) Thanh ghi iu khin a ch ca DMA (DACR_2) Thanh ghi la chn yu cu ngt qung ca DMA (DMRSR_2) Knh 3: Thanh ghi a ch ngun DMAC (DSAR_3)
264
Thanh ghi a ch ch ca DMAC (DDAR_3) Thanh ghi a ch offset ca DMAC (DOFR_3) Thanh ghi bin m ca DMAC (DTCR_3) Thanh ghi kch thc khi d liu ca DMA (DBSR_3) Thanh ghi iu khin ch ca DMA (DMDR_3) Thanh ghi iu khin a ch ca DMA (DACR_3) Thanh ghi la chn yu cu ngt qung ca DMA (DMRSR_3) 9.2.1 Thanh ghi a ch ngun ca DMA (DSAR) Thanh ghi DSAR l mt thanh ghi 32 bit c th c/ghi n ch ra a ch ngun d liu cn truyn. Thanh ghi DSAR cp nht gi tr a ch ngun sau mi ln truyn d liu. Trong ch a ch n nu thanh ghi DDAR c ch nh l mt a ch ch (bit DIRS trong thanh ghi DACR l 1), th thanh ghi DSAR s b b qua (do khi a ch ngun c ch nh bi tn hiu DACK ). Mc d thanh ghi DSAR lun lun c th c c bi CPU, nhng m n phi c c theo n v longword v khng c ghi trong khi d liu ca knh ang truyn
9.2.2 DMA Thanh ghi a ch ch (DDAR) Thanh ghi DDAR l mt thanh ghi 32-bit c th c/ghi n ch ra a ch ch ca vic truyn d liu. Thanh ghi DDAR cp nht a ch ch sau mi ln truyn d liu. Khi m thanh ghi DSAR c ch nh l thanh ghi a ch ngun (bit DIRS trong thanh ghi DASR c gi tr l 0) trong ch a ch n, th thanh ghi DDAR s b b qua.
265
Mc d thanh ghi DDAR lun lun c th c c bi CPU, nhng n phi lun c c vi n v l longword v khng c ghi vo thanh ghi ny trong khi d liu ang lun chuyn.
9.2.3 Thanh ghi a ch offset ca DMA (DOFR) Thanh ghi DOFR l mt thanh ghi 32-bit c th c/ghi n xc nh a ch cp nht li a ch ch v a ch ngun. Mc d cc gi tr khc nhau c ch nh cho tng knh, nhng gi tr cp nht cho a ch ch v a ch ngun l nh nhau i vi tng knh ring r.
9.2.4 Thanh ghi bin m lun chuyn ca DMA (DTCR) Thanh ghi DTCR l mt thanh ghi 32-bit c th c/ghi n xc nh kch thc d liu s c truyn (tng kch thc d liu truyn).
266
truyn 1-byte d liu, thit lp gi tr H0000 0001 trong thanh ghi DTCR. Khi gi tr c thit lp cho thanh ghi ny l H0000 0000, th iu ny c ngha l tng kch thc ca d liu lun chuyn khng c thit lp v b truyn d liu s dng li (khng hot ng) (ch chy t do free running mode). Khi gi tr c thit lp cho thanh ghi ny l HFFFF FFFF th tng kch thc c truyn l 4Gbyte (4,294,967,295), y l kch thc ln nht. Trong khi d liu ang c truyn th thanh ghi ny ch ra kch thc cn li ca khi d liu cn truyn. Gi tr ca n s c tr i sau mi ln chuyn d liu tng ng vi d liu truy xut (-1 nu n v chuyn l byte, -2 nu l word, v -4 nu l longword). Mc d thanh ghi DTCR lun lun c th c c bi CPU, nhng n phi lun c c theo n v longword v khng c ghi vo thanh ghi ny trong khi cc knh ang truyn d liu.
9.2.5 Thanh ghi kch thc ca khi (DBSR) Thanh ghi DBSR ch nh kch thc lp hay kch thc ca khi. Thanh ghi ny c cho php trong ch truyn lp v khi v n b cm trong ch bnh thng.
267
Bit 31 n 16
Tn bit
Gi tr khi ng
R/W
c t
BKSZH31 Khng xc nh n BKSZH16
R/W Xc nh kch thc lp hay kch thc khi. Khi gi tr c thit lp vo cc bit ny l H0001, th kch thc lp hay khi l mt byte, word hay longword. Khi gi tr c thit lp l H0000 th c ngha l gi tr ln nht (tham kho bng 9.1). Khi m DMA ang hot ng, th vic thit lp ny s b c nh (khng th thay i trong khi ang hot ng)
15 n 0
BKSZ15 n BKSZ0
Khng xc nh
R/W Cho bit kch thc lp hay khi cn li trong khi b DMA ang hot ng. Gi tr ny s gim 1 sau mi ln truyn. Khi m kch thc cn li l 0, th gi tr ca bit cc BKSZH s c chuyn vo cc bit BKSZ. Thit lp gi tr ging vi gi tr trong cc bit BKSZH.
Bng 9.1 Kch thc d liu, cc bit hp l v kch thc c th c thit lp Ch Kch thc d liu truy xut Cc bit BKSZH hp l Cc bit BKSZ hp l Kch thc c th thit lp
268
Truyn lp v truyn khi
Byte Word Longword
31 n 16
15 n 0
1 n 65 536 2 n 131 072 4 n 262 144
9.2.6 Thanh ghi iu khin ch ca DMA (DMDR) Thanh ghi DMDR iu khin ch hot ng ca b iu khin DMAC. DMDR_0
Ch : * Ch ghi gi tr 0 vo nhng bit ny sau khi c l 1, xo c. DMDR_1 to DMDR_3
Ch : * Chi ghi gi tr 0 vo nhng bit ny sau khi c c 1, xo c.
269
Bit
Tn bit
Gi tr khi ng 0
R/W
c t
31
DTE
R/W
Bit cho php truyn d liu. Bit ny cho php/cm vic truyn d liu ca tng knh tng ng. Bit ny bng 1 ngha l DMAC ang hot ng. Vic thit lp bit ny ln 1 s khi ng b truyn d liu khi m ch t ng yu cu (auto-request) c la chn. Khi cc module ngt qung trn chip hay cc yu cu bn ngoi c la chn, th mt yu cu truyn sau vic thit lp bit ny ln 1 s khi ng b truyn d liu. Trong khi m d liu ang c truyn th vic xo bit ny s lm dng hot ng truyn. Trong ch truyn khi, nu vic xo bit ny c thc hin trong khi d liu ang truyn th bit ny s b xo sau khi hot ng truyn hon tt vic truyn khi d liu ang truyn. Nu c mt s kin t bn ngoi dng b truyn trong khi n ang truyn d liu th bit ny s t ng xo dng hot ng truyn. 0: Khng truyn d liu 1: Cho php truyn d liu (DMA ang hot ng) [iu kin xo] Khi ton hot ng truyn hon tt Khi b truyn d liu b dng bi mt ngt qung trn kch thc vng lp Khi b truyn d liu b dng bi mt ngt qung trn kch thc vng lp m rng Khi b truyn d liu b dng bi ngt qung sai kch thc truyn Khi vic xo bit ny dng hot ng truyn
Trong ch truyn khi, th bit ny thay i gi tr sau khi truyn xong khi hin ti Khi ngt qung li a ch hay mt ngt qung ngoi NMI pht sinh
270
30 DACK E 0 R/W
Trong trng thi reset hay trong ch standby phn cng
Bit cho php tn hiu xut DACK Cho php/cm tn hiu xut DACK trong ch a ch n. Bit ny s b b qua trong ch a ch i. 0: Cho php tn hiu xut DACK 1: Cm tn hiu xut DACK Bit cho php tn hiu xut TEND Bit ny cho php/cm tn hiu xut TEND . 0: Cho php tn hiu xut TEND 1: Cm tn hiu xut TEND
29
TENDE 0
R/W
28 27
---
R/W R/W
Khng dng Bit ny lun c gi tr l 0. Bit la chn DREQ La chn liu mc thp hay cnh xung ca tn hiu DREQ c s dng trong ch yu cu ngoi s c kim tra. 0: Chn mc thp 1: Chn cnh xung
DREQS 0
26
NRD
R/W
Bit tr hon yu cu k tip Bit ny la chn thi khon cho php yu cu truyn k tip 0: Bt u cho php yu cu truyn k tip sau khi hon tt ln truyn hin ti 1: Bt u cho php yu cu truyn k tip sau khi ln truyn hin ti mt chu k (ngha l yu cu truyn k tip s b tr hon mt chu k).
25, 24 23
---
Khng dng y l nhng bit ch c v khng th hiu chnh gi tr ca n.
ACT
Trng thi kch hot Bit ny cho bit trng thi hot ng ca knh 0: ang ch yu cu truyn hay trong trng
271
thi cm do vic xo bit DTE 1: Trng thi kch hot 22 n 20 19 --0 R Khng dng Cc bit ny l cc bit ch c, gi tr ca n khng th b hiu chnh. ERRF 0 R/(W)* Bit c li h thng Bit ny ch ra rng mt ngt qung li a ch hay mt ngt qung NMI c pht sinh. Bit ch c trong thanh ghi DMDR_0. Vic thit lp bit ny ln 1 s cm vic ghi vo bit DTE ca tt c cc knh. Bit ny khng c dng i vi cc thanh ghi DMDR_1, DMDR_2 v DMDR_3, trong cc thanh ghi ny th bit ny lun c gi tr l 0 v khng th hiu chnh gi tr ca n. 0: Ngt qung li a ch hay NMI cha c pht sinh 1: Mt ngt qung li a ch hay NMI c pht sinh [iu kin xo] Khi xo bit ny. Khi c mt ngt qung li a ch hay mt ngt qung NMI pht sinh. [iu kin thit lp]
Tuy nhin, khi mt ngt qung li a ch hay NMI c pht sinh trong ch dng module, th bit ny s khng c thit lp. 18 --0 R Khng dng Bit ny l bit ch c v khng th hiu chnh gi tr ca n. 17 ESIF 0 R/(W)* Bit c ngt qung thot truyn Bit ny cho bit ngt qung thot khi hot ng truyn c yu cu. Mt thot truyn c ngha l hot ng truyn c kt thc trc khi m truyn t n gi tr 0. 0: Khng c ngt qung thot truyn 1: Mt ngt qung thot truyn c yu cu [iu kin xo]
272
16 DTIF 0 R/(W)*
Khi thit lp bit DTE ln 1 Khi xo n C mt ngt qung li a ch Khi c mt ngt qung kt thc kch thc lp Khi c mt ngt qung kt thc truyn do trn vng lp m rng.
[iu kin thit lp]
Bit c ngt qung truyn d liu Bit ny ch ra rng ngt qung kt thc truyn bi m truyn c yu cu. 0: Khng c ngt qung kt thc truyn do m truyn 1: C ngt qung kt thc truyn do m truyn [iu kin xo] Khi bit DTE c thit lp ln 1 Khi bit ny b xo (trc c gi tr l 1) Khi DTCR t n gi tr 0 v hot ng truyn c hon tt.
[iu kin thit lp]
15 14
DTSZ1 DTSZ0
0 0
R/W R/W
Cc bit kch thc d liu truy xut Cc bit ny cho php la chn kch thc d liu truy xut 00: kch thc byte 01: kch thc word 10: kch thc long word 11: cm thit lp
13 12
MDS1 MDS0
0 0
R/W R/W
Bit la chn ch truyn Cc bit ny cho php la chn ch truyn 00: ch truyn bnh thng 01: ch truyn khi 10: ch truyn lp 11: cm thit lp
11
TSEIE
R/W
Bit cho php ngt qung li kch thc truyn
273
Bit ny cm/cho php ngt qung li kch thc truyn. Khi ln truyn tip c yu cu trong khi bit ny c thit lp ln 1 v cc ni dung m truyn nh hn kch thc d liu s c truyn trong mt ln truyn, th bit DTE s b xo. Vo lc ny, bit ESIF c thit lp cho bit l c mt ngt qung li kch thc truyn c pht sinh. Cc ngun ca mt li kch thc truyn l: Trong ch truyn bnh thng hay ch lp, nu tng kch thc truyn c thit lp trong thanh ghi DTCR nh hn kch thc d liu truy xut. Trong ch truyn khi, m c tng kch thc d liu c thit lp trong DTCR nh hn kch thc khi.
0: Cm yu cu ngt qung sai kch thc truyn 1: Cho php yu cu ngt qung sai kch thc truyn 10 --0 R Khng dng Bit ny l bit ch c v khng th hiu chnh gi tr ca n. 9 ESIE 0 R/W Bit cho php ngt thot truyn. Bit ny cm/cho php yu cu ngt qung thot truyn. Khi bit ESIF bng 1 v bit ny cng c thit lp th mt thot truyn s c yu cu cho CPU. Yu cu thot truyn c xo bi vic xo bit ny hoc bit ESIF. 0: Cm ngt qung thot truyn 1: Cho php ngt qung thot truyn 8 DTIE 0 R/W Bit cho php ngt qung kt thc truyn d liu Bit ny cho php/cm yu cu ngt qung kt thc truyn d liu do m truyn. Khi bit DTIF v bit ny u bng 1, th mt ngt qung kt thc truyn s c yu cu cho CPU. Yu cu ngt qung kt thc truyn s c xo bi vic xo bit ny hay bit DTIF. 0: Cm ngt qung kt thc truyn 1: Cho php ngt qung kt thc truyn
274
7 6
DTF1 DTF0
0 0
R/W R/W
Bit nhn t truyn d liu Cc bit ny la chn ngun kch hot. Khi vic thit lp module ngoi vi trn chip c la chn, th ngun ngt qung phi c la chn bi thanh ghi DMRSR. Khi vic thit lp yu cu ngoi c la chn, th phng thc ly mu nn c chn bi bit DREQS 00: t ng yu cu (chu k stealing) 01: t ng yu cu (chu k burst) 10: module ngt qung trn chip 11: yu cu ngoi
DTA
R/W
Bit xc nhn truyn d liu Khi module ngt qung trn chip c la chn l ngun ngt qung cho DMAC, th bit ny phi c thit lp l 1.
4, 3 ---
Khng dng Cc bit ny l cc bit ch c v khng th hiu chnh gi tr ca n
2 1 0
DMAP 2 DMAP 1 DMAP 0
0 0 0
R/W R/W R/W
Cc bit ch u tin DMA Cc bit ny la chn mc u tin ca DTC v DMAC. Khi CPU c u tin hn DMAC, cc yu cu truyn ca DMAC s b hon li v ch cho n khi CPU c u tin thp hn DMAC. Mc u tin c th c thit lp theo tng knh ring r. Cc bit ny hp l khi bit CPUPCE trong thanh ghi CPUPCR bng 1 000: Mc 0 001: Mc 1 010: Mc 2 011: Mc 3 100: Mc 4 101: Mc 5 110: Mc 6 111: Mc 7 (cao)
9.2.7 Thanh ghi iu khin a ch ca DMA (DACR)
275
Thanh ghi DACR xc nh ch hot ng v phng thc truyn d liu
Bit
Tn bit
Gi tr khi ng 0
R/W
c t
31
AMS
R/W Bit la chn ch a ch La chn ch a ch n hay a ch i. Trong ch a ch n, th chn DACK c cho php thng qua bit DACKE 0: ch a ch i 1: ch a ch n
30
DIRS
R/W Bit la chn a ch n trc tip Ch nh d liu trc tip trong ch a ch n. Bit ny s b b qua trong ch a ch i 0: Ch nh thanh ghi DSAR l a ch ngun 1: Ch nh thanh ghi DDAR l a ch ch
29 n 27 26
----
Khng dng Cc bit ny ch l bit ch c v khng th hiu chnh gi tr ca n
RPTIE
R/W Bit cho php ngt kt thc kch thc lp Cm/cho php mt yu cu ngt qung kt thc kch thc lp. Trong ch lp, khi ln truyn k tip c yu cu sau khi hon tt vic truyn mt
276
d liu 1-repeat-size trong khi bit RPTIE bng 1, th bit DTE trong thanh ghi DMDR s b xo. V lc ny, bit ESIF trong thanh ghi DMDR c thit lp ch ra rng mt ngt qung kt thc kch thc truyn c pht sinh. Thm ch khi vng lp khng c ch nh bi (ARS1 = 1 v ARS0 = 0), mt ngt qung kt thc kch thc lp sau khi truyn mt d mt khi d liu cng c th c yu cu. Ngoi ra, trong ch truyn khi, khi ln truyn tip theo c yu cu sau khi truyn mt khi d liu trong khi bit RPTIE bng 1, th bit DTE trong thanh ghi DMDR cng b xo. Vo lc ny, bit ESIF trong thanh ghi DMDR c thit lp yu cu mt ngt qung kt thc kch thc lp. 0: Cm ngt qung kt thc kch thc lp 1: Cho php ngt qung kt thc kch thc lp. 25 24 ARS1 ARS0 0 0 R/W La chn khi R/W Xc nh vng d liu khi/lp trong ch truyn d liu khi/lp 00: Vng d liu khi hay vng lp c xc nh bi a ch ngun 01: Vng d liu khi hay vng lp c xc nh bi a ch ch 10: Khng xc nh vng d liu khi hay lp 11: Cm thit lp 23, 22 21 20 --0 R Khng dng Cc bit ny l nhng bit ch c v khng th hiu chnh gi tr ca n. SAT1 SAT0 0 0 R/W Cc bit Ch cp nht a ch ngun R/W Cc bit ny la chn phng thc cp nht cho a ch ngun (DSAR). Khi thanh ghi DSAR khng gi vai tr l a ch ngun cho b truyn d liu trong ch n a ch, th bit ny s b b qua. 00: a ch ngun khng thay i 01: a ch ngun c cp nht bng vic cng thm offset 10: a ch ngun c cp nht bi cng thm 1,
277
2, hay 4 tu vo kch thc d liu truy xut. 11: a ch ngun c cp nht bi vic tr 1, 2, hay 4 tu thuc vo kch thc d liu truy xut. 19, 18 17 16 --0 R Khng dng Cc bit ny l cc bit ch c v khng th thay i gi tr DAT1 DAT0 0 0 R/W Cc bit ch cp nht a ch ch R/W Cc bit ny la chn phng thc cp nht cho a ch ch (DDAR). Khi thanh ghi DDAR khng gi vai tr l a ch ch cho b truyn d liu trong ch n a ch, th bit ny s b b qua. 00: a ch ch khng thay i 01: a ch ch c cp nht bng vic cng thm offset 10: a ch ch c cp nht bi cng thm 1, 2, hay 4 tu vo kch thc d liu truy xut. 11: a ch ch c cp nht bi vic tr 1, 2, hay 4 tu thuc vo kch thc d liu truy xut. 15 SARIE 0 R/W Bit cho php ngt, ngt qung to ra bi vic trn vng a ch ngun m rng Khi c mt hot ng trn vng d liu lp m rng trn a ch ngun v bit ny bng 1, th bit DTE trong thanh ghi DMDR s b xo. Trong lc ny, bit ESIF trong thanh ghi DMDR c thit lp ch nh chi ra mt ngt qung to bi mt hot ng trn vng lp m rng trn a ch ngun c pht sinh. Khi ch truyn d liu khi c s dng vi chc nng vng lp m rng, th mt ngt qung s c yu cu sau khi hon tt mt hot ng chuyn mt khi d liu. Khi vic thit lp bit DTE trong thanh ghi DMDR ca knh b dng ln 1, b chuyn d liu s phc hi li trng thi khi m n b dng. Khi m vng lp m rng khng c ch nh, th bit ny s b b qua. 0: Cm ngt qung to ra cho vic trn vng nh m rng trn a ch ngun. 1: Cho php ngt qung to ra khi c hot ng
278
trn b nh m rng trn a ch ngun. 14, 13 12 11 10 9 8 --0 R Khng dng Cc bit ny l nhng bit ch c v khng th thay i gi tr SARA4 SARA3 SARA2 SARA1 SARA0 0 0 0 0 0 R/W Cc bit ch vng lp m rng a ch ngun R/W Ch nh vng lp m rng trn a ch ngun (DSAR). Vi vng lp m rng, th cc cc bit R/W thp ca a ch s c cp nht v cc bit cao R/W cn li s b c nh. Vng lp m rng c kch R/W thc t 4 byte n 128Mbyte Khi c hot ng trn vng lp m rng m bit SARIE c thit lp ln 1, th mt ngt qung s c yu cu. Bng 9.2 s trnh by vic thit lp v vng lp m rng. 7 DARIE 0 R/W Bit Cho php ngt qung trn vng lp m rng ca a ch ch. Cho php/cm yu cu ngt qung v mt hot ng trn vng lp m rng trn vng a ch ch Khi hot ng trn vng lp m rng trn vng a ch ch xy ra trong lc bit ny c bng 1, th bit DTE ca thanh ghi DMDR s b xo. V lc ny, bit ESIF trong thanh ghi DMDR s c thit lp ln 1 cho bit rng c mt yu cu ngt qung trn vng lp m rng trn vng a ch ch Khi ch truyn khi c s dng vi chc nng vng lp m rng, mt ngt qung s c yu cu sau khi hon tt truyn mt 1-block size. Nu vic thit lp bit DTE trong thanh ghi DMDR ca knh m b dng ln 1, th hot ng truyn s c phc hi li t trng thi m n b dng. Khi vng lp m rng khng c ch nh, th bit ny b b qua. 0: Cm yu cu ngt qung ca hot ng trn vng lp m rng trn a ch ch 1: Cho php yu cu ngt qung ca hot ng trn vng lp m rng trn a ch ch 6, 5 --0 R/W Khng dng Cc bit ny l nhng bit ch c v khng th thay
279
i gi tr 4 3 2 1 0 DARA4 0 DARA3 0 DARA2 0 DARA1 0 DARA0 0 R/W Cc bit Vng lp M rng trn vng a ch ch R/W Ch nh vng lp m rng trn vng a ch ch (DDAR). Vi vng lp m rng, th cc bit thp l R/W c cp nht v cc bit cao cn li l b c nh R/W (khng i). Kch thc ca vng lp m rng R/W c ch nh t 4 byte n 128 Mbyte theo n v byte v lu tha ca 2. Khi mt hot ng trn xy ra vi bit DARIE c thit lp ln 1, th mt ngt qung c th c yu cu. Bng 9.2 s trnh by vic thit lp cc vng ca vng lp m rng Bng 9.2 Thit lp v cc vng ca vng lp m rng SARA4 n SARA0 hay DARA4 n DARA0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 Khng xc nh Vng lp m rng l 2 byte Vng lp m rng l 4 byte Vng lp m rng l 8byte Vng lp m rng l 16byte Vng lp m rng l 32byte Vng lp m rng l 64byte Vng lp m rng l 128byte Vng lp m rng l 256byte Vng lp m rng l 512byte Vng lp m rng l 1Kbyte Vng lp m rng l 2Kbyte Vng lp m rng l 4Kbyte Vng lp m rng l 8Kbyte Vng lp m rng l 16Kbyte Vng lp m rng l 32Kbyte Vng lp m rng l 64Kbyte Vng lp m rng l 128Kbyte Vng lp m rng
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10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 111xx Ghi ch: X: Khng quan tm
Vng lp m rng l 256Kbyte Vng lp m rng l 512Kbyte Vng lp m rng l 1Mbyte Vng lp m rng l 2Mbyte Vng lp m rng l 4Mbyte Vng lp m rng l 8Mbyte Vng lp m rng l 16 Mbyte Vng lp m rng l 32Mbyte Vng lp m rng l 64Mbyte Vng lp m rng l 128Mbyte Cm thit lp
9.2.8 Thanh ghi la chn module yu cu ca DMA (DMRSR) Thanh ghi DMRSR l mt thanh ghi 8-bit c th c/ghi n xc nh cc ngun ngt ca cc module trn chip. Ch s vector ca ngun ngt c ch nh bi 8 bit. Tuy nhin, gi tr 0 c hiu nh l khng c ngun ngt qung. i vi cc ch s vector ca ngun ngt, tham kho bng 9.4
9.3 Cc ch chuyn d liu

Bng 9.3 Cho thy cc ch chuyn d liu ca DMAC. Cc ch chuyn d liu c th c ch nh cho tng knh ring r. Bng 9.3 Cc ch chuyn d liu Ch a ch a ch i Ch chuyn d liu - Ch bnh thng - Ch lp - Ch chuyn khi Kch thc ca Ngun kch hot - T ng yu cu (kch hot bi CPU) - Ngt qung module trn chip - Yu cu bn Chc nng thng thng a ch thanh ghi Ngun ch DDAR
- Tng kch DSAR thc truyn: 1 n 4 Gbyte hoc l khng ch nh - Cng thm Offset
281
khi hay lp = 1 n 65 536 byte, word hay longword a ch n
ngoi
- Chc nng vng lp m rng DSAR/

DACK DACK /
- Thay v ch nh thanh ghi a ch ngun hay ch, d liu c chuyn trc tip t/ti thit b ngoi s dng chn DACK - Cng cch thit lp nh trn l khng thch hp cho vic thit lp thanh ghi a ch (th d, cc ch chuyn d liu trn c th c ch nh). - Mt hot ng chuyn d liu c th c thc hin trong mt chu k bus
DDAR
Khi vic thit lp yu cu t ng c la chn nh l mt ngun kch hot, th chu k truy xut stealing hay burst c th c la chn. Khi m tng kch thc truyn khng c ch nh (DTCR = H0000 0000), th b m truyn s b dng v hot ng truyn c tip tc vi vic truyn d liu khng gii hn.
9.4 Cc hot ng
9.4.1 Ch a ch (1) Ch a ch i Trong ch a ch i, a ch ngun d liu cn truyn ti c ch nh bi thanh ghi DSAR v a ch ch cn truyn ti c ch nh trong thanh ghi DDAR. Mt ln truyn d liu s c thc thi trong 2 chu k (khi ln ca bus d liu nh hn kch thc d liu truy xut hay a ch truy xut khng tng thch vi d liu truy xut, khi s chu k bus cn phi c ch nh hn 2 v mi chu k trong n c chia thnh nhiu chu k bus). Trong chu k u tin, th d liu a ch ngun s c c v trong chu k k d liu c s c ghi vo a ch ch. Chu k c v ghi khng th b tch bit. Mt chu k bus khc khng th xy ra gia chu k c v chu k ghi. Tn hiu xut TEND c cho php hoc cm bi bit TENDE trong thanh ghi DMDR. Tn hiu TEND l tn hiu xut trong 2 chu k bus. Khi mt chu k idle c thm vo trc chu k bus, th tn hiu idle cng l tn hiu xut trong chu k idle . Tn hiu DACK khng phi l tn hiu xut. Hnh 9.2 trnh by mt v d v gin xung tn hiu trong ch a ch i v hnh 9.3 trnh by hot ng trong ch a ch i.
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Hnh 9.2 V d v gin xung tn hiu trong ch a ch i
Hnh 9.3 Hot ng trong ch a ch i (2) Ch a ch n Trong ch a ch n, d liu truyn gia mt thit b bn ngoi v mt b nh bn ngoi c truyn trc tip s dng chn DACK thay v s dng DSAR hay DDAR. Mt hot ng truyn ti mt thi im c thc hin trong mt chu k bus. Trong ch ny, rng ca bus d liu phi cng rng vi kch thc d liu truy xut. Chi tit tham kho rng ca bus d liu, phn 6, b iu khin bus (BSC) B iu khin DMAC truy xut mt thit b bn ngoi nh l mt a ch ngun hay ch bi vic xut mt tn hiu vo thit b bn ngoi ( DACK ) v truy xut a ch cn li (ngun hoc ch) bi thng qua a ch (c ch nh bi thanh ghi a ch ngun hoc ch). Do , hot ng chuyn ti DMA c thc hin trong mt chu k bus. Hnh 9.4 trnh by mt v d ca mt hot ng truyn d liu gia mt b nh bn ngoi v mt thit b bn ngoi vi chn DACK . Trong v d ny, thit b bn ngoi xut d liu trn bus d liu v d liu c ghi vo b nh ngoi trong cng mt chu k bus. Hot ng chuyn d liu trc tip c qut nh bi bit DIRS trong thanh ghi DACR, thanh ghi m ch nh mt thit b ngoi vi chn DACK ngun hay ch. Khi bit DIRS = 0, d liu c truyn t b nh ngoi (DSAR) vo thit b ngoi vi chn DACK . Khi bit DIRS = 1, d liu c truyn t thit b ngoi vi chn
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DACK vo b nh ngoi (DDAR). Vic thit lp cc thanh ghi m khng c s
dng vi vai tr l ngun hoc ch ca hot ng chuyn d liu s b b qua. Tn hiu xut DACK b cm trong ch a ch n bi bit DACKE trong thanh ghi DMDR. Tn hiu DACK tch cc mc cao. Tn hiu xut TEND c cho php hoc cm bi bit TENDE trong thanh ghi DMDR. Tn hiu TEND l tn hiu xut trong mt chu k bus. Khi mt chu k ngh (idle) c thm vo trc mt chu k bus, th tn hiu TEND cng c xut ra trong chu k ngh (idle) Hnh 9.5 trnh by mt v d v gin thi gian trong ch a ch n v Hnh 9.6 trnh by mt v d ca hot ng trong ch a ch n.
Hnh 9.4 Dng d liu trong ch a ch n
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Hnh 9.5 V d v gin tn hiu trong ch a ch n
Hnh 9.6 Cc hot ng trong ch a ch n 9.4.2 Cc ch chuyn d liu (1) Ch chuyn d liu bnh thng Trong ch bnh thng, d liu ca mt ln truy xut s c truyn i ch vi mt yu cu truyn. C th ch nh ti a l 4Gbyte kch thc cn truyn ti v kch thc ny c quyt nh bi thanh ghi DTCR. Thanh ghi DBSR s b b qua trong ch bnh thng.
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Tn hiu TEND l tn hiu xut ch trong ln truyn cui cng ca DMA. Tn hiu DACK l tn hiu xut khi nhn c yu cu truyn v khi bt u truyn ti. Hnh 9.7 Trnh by mt v d ca gin thi gian trong ch truyn bnh thng v hnh 9.8 trnh by hot ng trong ch bnh thng.
Hnh 9.7 V d v gin thi gian trong ch truyn bnh thng
Hnh 9.8 Cc hot ng trong ch bnh thng (2) Ch truyn lp Trong ch truyn lp, mt phn t d liu c truyn trong mt yu cu ngt truyn n. V kch thc truyn ti ti a l 4Gbyte v n c ch ra bi thanh ghi DTCR. Kch thc lp c th ch nh trong thanh ghi DBSR di 65536 x kch thc truy xut. Vng lp c th c ch nh cho a ch ngun hay a ch ch ph thuc vo cc bit ARS1 v ARS0 trong thanh ghi DACR. a ch c ch nh l vng lp s tr v the a ch bt u truyn khi m kch thc lp ca hot ng truyn c hon tt. Hot ng ny c lp li cho n khi m ton b kch thc c ch nh trong thanh ghi DTCR c hon thnh. Khi m gi tr H0000 0000 c ghi vo thanh ghi DTCR, th iu ny c xem nh l ch truyn t do v ch truyn lp c tip tc cho n khi m bit DTE trong thanh ghi DMDR b xo.
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Thm na, mt b truyn DMA c th dng v mt ngt qung kt thc truyn c th c yu cu cho CPU hay DTC khi kch thc lp ca hot ng truyn hon tt. Khi hot ng truyn tip theo c yu cu sau khi hon tt mt d liu 1-repeat size (1-repeat size data-mt khi d liu lp) trong khi bit RPTIE c bng 1, bit DTE trong thanh ghi DMDR s c xo v bit ESIF trong thanh ghi DMDR c thit lp ln 1 hon tt vic truyn. Vo lc ny, mt ngt qung s c pht sinh cho CPU hay DTC nu bit ESIE trong thanh ghi DMDR bng 1. Gin thi gian ca tn hiu TEND v DACK l ging nhau trong ch truyn bnh thng. Hnh 9.9 trnh by hot ng trong ch truyn lp v ch a ch i. Khi vng lp c ch nh l a ch ngun hoc a ch ch, th hot ng cng ging nh trong ch bnh thng c trnh by trong hnh 9.8. Trong trng hp ny, mt ngt qung kt thc 1 khi truyn lp cng c th c yu cu cho CPU nu vic truyn ti khi kt thc.
Hnh 9.9 Hot ng trong ch truyn lp (3) Ch truyn khi Trong ch truyn khi, mt khi d liu c th c truyn trong mt yu cu truyn. Kch thc khi cn truyn ti a l 4Gbyte c ch nh bi thanh ghi DTCR. Kch thc truy xut khi c th c ch nh bi thanh ghi DBSR, nh hn 65535 x kch thc truy xut. Trong khi mt khi d liu ang c truyn ti, th cc yu cu truyn ti ca cc knh khc u b hon li. Khi hot ng truyn ti hon thnh, th bus s c gii phng cho cc thnh phn s dng bus khc. Vng khi c th c ch nh l a ch ngun hay ch bi cc bit ARSI v ARS0 trong thanh ghi DACR. a ch c ch nh l vng khi s tr v a ch bt u ca hot ng truyn ti khi m kch thc khi ca d liu hon thnh. Khi vng khi c ch nh hoc l a ch ngun hoc l a ch ch,
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hot ng s tip tc m khng tr v a ch bt u truyn. Mt ngt qung kt thc truyn d liu c th c yu cu. Tn hiu TEND l tn hiu xut trong chu k DMA cui cng ca tt c cc khi d liu truyn (xem hnh 9.10). Khi c mt ngt ngoi c chn lm ngun kch, tn hiu in p thp trn chn DREQ nn c la chn. Nu mt yu cu ngt qung bi hot ng trn vng lp m rng c s dng trong ch truyn khi, th vic thit lp nn c la chn mt cch k lng. Chi tit, tham kho phn 9.4.5, chc nng vng lp m rng. Hnh 9.10 trnh by mt v d v gin thi gian lun chuyn DMA trong ch truyn khi d liu. Cc iu kin truyn nh sau: Ch nh a ch: Ch a ch n Kch thc truy xut d liu: byte Kch thc ca mt khi d liu: 3 byte
Ch truyn d liu khi hot ng trong ch a ch n v trong ch a ch i c trnh by trong hnh 9.11 v 9.12.
Hnh 9.10 Cc hot ng trong ch truyn khi
Hnh 9.11 Hot ng trong ch a ch n trong ch truyn khi (vng khi c ch nh)
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Hnh 9.12 Hot ng trong ch a ch i trong ch truyn khi (Vng khi khng c ch nh) 9.4.3 Cc ngun kch hot DMAC c kch hot bi mt yu cu t ng, mt module ngt qung trn chip, v mt ngt ngoi. Ngun ngt c ch nh bi cc bit DTF1 v DTF0 trong thanh ghi DMDR. (1) S kch hot bi yu cu t ng S kch hot bi yu cu t ng c s dng khi c mt yu cu truyn t mt thit b ngoi (external device) hay mt module ngoi vi m khng c pht sinh, v nh hot ng truyn ti gia b nh v b nh hay gia b nh v module thit b ngoi vi trn chip m khng c yu cu truyn. Mt yu cu truyn c t ng pht sinh bn trong DMAC. Trong yu cu kch hot t ng, vic thit lp bit DTE trong thanh ghi DMDR l khi ng hot ng truyn. Ch bus c th c la chn l cycle stealing hay burst modes. (2) S kch hot bi mt module ngt qung trn chip Mt yu cu ngt qung t mt module thit b ngoi vi trn chip(ngt qung module thit b ngoi vi trn chip) c s dng nh l mt yu cu truyn ti. Khi hot ng truyn DMA c cho php (DTE = 1), th hot ng truyn DMA c bt u bi mt ngt qung t mt module trn chip.
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Ngun kch hot ca module ngt qung trn chip c la chn bi thanh ghi la chn module yu cu ngt qung DMA (DMRSR). Cc ngun ngt c ch nh cho tng knh c th. Bng 9.4 l mt danh sch cc ngt qung ca module trn chip cho DMAC. DMAC nhn cc yu cu ngt qung bi cc module ngoi vi c lp trn chip ca b iu khin ngt qung. V vy, m DMAC khng b nh hng bi u tin c a ra bi b iu khin ngt qung. Nu DMAC c kch hot bi ngun ngt c la chn trong khi DTE = 1, c ngt qung s c t ng xo bi b truyn d liu DMA. Nu nhiu knh c s dng yu cu ngt qung n nh l ngun ngt, th knh c u tin hn c kch hot, c ngt qung s c xo. Trong trng hp ny, cc knh khc s khng c kch hot bi v yu cu truyn s khng c gi li trong b truyn DMAC. Khi mt ngun ngt c la chn trong khi DTE = 0, th ngun ngt s khng truyn cho DMAC. N s yu cu mt ngt qung cho CPU hoc DTC. Ngoi ra, phi chc chn rng c ngt qung ca mt module ngun ngt trn chip c xo trc khi ghi 1 vo bit DTE. Bng 9.4 Danh sch cc ngt qung ca module trn chip cho DMAC Ngun ngt ca module trn chip Module DMRSR trn (Ch s chip vector) A/D_0 A/D_1 TPU_0 TPU_1 TPU_2 TPU_3 SCI_3 SCI_3 SCI_4 SCI_4 TPU_6 TPU_7 TPU_8 86 87 88 93 97 101 157 158 161 162 164 169 173
ADI0 (Ngt qung kt thc vic chuyn i A/D) ADI1 (Ngt qung kt thc vic chuyn i A/D) TGI0A (TGI0A input capture/compare match) TGI1A (TGI1A input capture/compare match) TGI2A (TGI2A input capture/compare match) TGI3A (TGI3A input capture/compare match) RXI3 (Ngt qung nhn y d liu ca knh SCI 3) TXI3 (Ngt qung khng c d liu truyn ca knh SCI 3) RXI4 (Ngt qung nhn y d liu ca knh SCI 4) TXI4 (Ngt qung khng c d liu truyn ca knh SCI 4) TGI6A (TGI6A input capture/compare match) TGI7A (TGI7A input capture/compare match) TGI8A (TGI8A input capture/compare match)
290
TGI9A (TGI9A input capture/compare match) TGI10A (TGI10A input capture/compare match) TGI11A (TGI11A input capture/compare match) SSRXI0 (ngt qung nhn y d liu ca knh SSU 0) SSTXI0 (ngt qung khng c d liu truyn hay kt thc truyn ca knh SSU 0) SSRXI1 (ngt qung nhn y d liu ca knh SSU 1) SSTXI1 (ngt qung khng c d liu truyn hay kt thc truyn ca knh SSU 1) SSRXI2 (ngt qung nhn y d liu ca knh SSU 2) SSTXI2 (ngt qung khng c d liu truyn hay kt thc truyn ca knh SSU 2) (3) Kch hot bi ngt ngoi
TPU_9
177
TPU_10 182 TPU_11 188 SSU_0 SSU_0 SSU_1 SSU_1 SSU_2 SSU_2 228 229 232 233 236 237
Mt b truyn d liu c khi ng bi mt tn hiu ngt ngoi ( DREQ ) t mt thit b ngoi. Khi mt b truyn DMA c cho php (DTE = 1), th b truyn DMA c khi ng bi mt tn hiu DREQ Mt tn hiu yu cu truyn c a vo chn DREQ . Tn hiu DREQ c kim tra khi c cnh xung hay mc thp. Cnh xung hay mc thp s c s dng l c quyt nh bi bit DREQS trong thanh ghi DMDR. thc hin truyn d liu khi, th tn hiu mc thp nn c la chn. Khi mt yu cu ngoi c la chn vi vai tr l mt ngun ngt, th xo bit DDR v thit lp bit ICR ln 1 cho chn tng ng. Chi tit, tham kho phn 9 cng xut nhp. Khi mt hot ng truyn d liu gia cc module thit b ngoi vi trn chip c thc hin, thi nn la chn mt ngun ngt t yu cu t ng v module ngt trn chip (yu cu ngt ngoi khng th c s dng). 9.4.4 Cc ch truy xut bus C 2 loi ch truy xut bus l: chu k stealing v burst. Khi mt ngun kch hot l yu cu t ng, ch cycle stealing hay burst s c la chn bi bit DTF0 trong thanh ghi DMDR. Nu ngun kch hot l ngt qung ca module trn chip hoc l cc yu cu bn ngoi, th ch chu k stealing c la chn. (1) Ch cycle stealing
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Trong ch cycle stealing, th DMAC s gii phng bus khi mt hot ng truyn d liu kt thc (truyn 1 byte, 1 word, 1 longword, hay khi). Sau , khi mt hot ng truyn khc c yu cu, DMAC s nhn c bus truyn mt n v d liu no v sau li tip tc gii phng bus khi m hot ng truyn ny kt thc. Qu trnh ny c tip tc cho n khi m iu kin kt thc vic truyn d liu tho mn. Khi mt hot ng truyn c yu cu cho mt knh khc trong qu trnh hot ng ca mt DMA, b DMAC s gii phng bus v sau truyn d liu cho knh c yu cu. Chi tit tham kho phn 10.4.8, u tin ca cc knh. Hnh 9.13 Trnh by mt v d ca gin thi gian trong ch cycle stealing. Cc iu kin truyn c cho bn di y: Ch a ch: ch a ch n Phng thc ly mu ca tn hiu DREQ : kim tra mc thp
Hnh 9.13 V d gin thi gian ca ch Cycle stealing (2) Ch truy xut burst (burst access) Trong ch burst th DMAC chim bus mt ln duy nht t u n cui. B DMAC c tip tc truyn m khng gii phng bus cho n khi iu kin truyn c tho mn. Thm ch c khi mt hot ng truyn c yu cu bi mt knh khc c u tin cao hn, th hot ng truyn cng s khng dng li mt khi khi ng. DMAC ch gii phng bus chu k k tip sau khi hot ng truyn ca knh ny trong ch burst hon tt. iu ny cng tng t nh trong ch stealing. Tuy nhin vic thit lp bit IBCCS trong thanh ghi IBCR ca b iu khin bus s lm cho DMAC gii phng bus v chuyn cho thnh phn khc mun s dng bus. Trong ch truyn khi, th vic thit lp ch burst s b b qua. B DMAC lun c hot ng trong ch cycle stealing. Vic xo bit DTE trong thanh ghi DMDR s dng hot ng truyn DMA. Mt yu cu truyn trc khi bit DTE trong thanh ghi DMDR b xo s c thc thi. Khi mt ngt qung bi mt li kch thc truyn, kt thc kch thc lp, hay mt hot ng trn vng lp m rng, th bit DTE s b xo v qu trnh truyn s kt thc. Hnh 10.14 trnh by mt v d v gin thi gian trong ch burst.
Hnh 9.14 V d ca gin thi gian trong ch burst

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9.4.5 Chc nng vng lp m rng a ch ngun v a ch ch (side) c th c ch nh l vng lp m rng. Ni dung ca thanh ghi a ch lp li cc a ch trong vng c ch nh l vng lp m rng. V d, s dng mt vng m nh l mt ch hoc ngun ca hot ng truyn (transfer target), th ni dung ca thanh ghi a ch nn tr v a ch bt u ca buffer khi m ni dung t ti a ch kt thc ca buffer (trn trn a ch buffer vng). Hot ng ny c th t ng thc hin s dng chc nng vng lp m rng ca DMAC (xem hnh 9.15). Cc vng lp m rng c th c ch nh mt cch c lp cho thanh ghi a ch ngun (DSAR) v thanh ghi a ch ch (DDAR) Vng lp m rng trn a ch ngun c ch nh bi cc bit SARA4 n SARA0 trong thanh ghi DACR. Vng lp m rng trn a ch ch c ch nh bi cc bit DARA4 n DARA0 trong thanh ghi DACR. Cc kch thc ca vng lp m rng cho mi loi a ch (ngun hot ch) c th c ch nh mt cch c lp. Hot ng truyn DMA s b dng v mt ngt qung bi mt tn hiu trn vng lp m rng c th c yu cu cho CPU khi ni dung ca thanh ghi a ch t ti a ch kt thc ca vng lp m rng. Khi mt hot ng trn vng lp m rng DSAR (a ch ch) xy ra trong khi bit SARIE trong thanh ghi DACR c thit lp l 1, th bit ESIF trong thanh ghi DMDR c thit lp l 1 v bit DTE trong thanh ghi DMDR c xo dng hot ng truyn d liu. Trong lc ny, nu bit ESIE trong thanh ghi DMDR c thit lp l 1, th mt ngt qung bi hot ng trn vng lp m rng s c gi n CPU. Khi m bit DARIE trong thanh ghi DACR c thit lp l 1, cho php ngt qung mt hot ng trn trn vng lp m rng (c ch n bi DDAR) xy ra, v iu ny c ngha l vng a ch ch l mt target (ch ca hot ng truyn). Trong qu trnh p ng ngt qung th vic thit lp bit DTE trong thanh ghi DMDR s phc hi li hot ng truyn. Hnh 9.15 trnh by mt v d ca hot ng vng lp m rng
Hnh 9.15 V d ca hot ng vng lp m rng
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Khi mt hot ng truyn b dng bi mt ngt qung trn vng lp m rng, th thanh ghi a ch mi rng phi c thit lp kch thc khi l mt lu tha ca 2 hay kch thc khi tng thch vi vng lp m rng. Khi mt hot ng trn trn vng lp m rng xy ra trong qu trnh truyn mt khi d liu, th ngt qung do trn c b hon li v hot ng truyn trn (transfer overrun). Hnh 9.16 trnh by cc v d khi chc nng vng lp m rng c s dng trong ch truyn khi
Hnh 9.16 V d v chc nng vng lp m rng trong ch truyn khi 9.4.6 Chc nng cp nht a ch s dng Offset a ch ngun v ch c cp nht bng cch c nh, tng/gim 1, 2, hay 4 hay cng offset. Khi m offset addition c la chn, th offset c ch nh bi thanh ghi offset (DOFR) c cng vo a ch mi khi DMAC truyn kch thc truy xut d liu. Chc nng ny gip nhn dng c d liu khi a ch ca nhng d liu ny nm nhng ni ring r (hay cch xa nhau). Hnh 9.17 Trnh by phng thc cp nht a ch
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Hnh 9.17 Phng thc cp nht a ch Trong mu (a), a ch c c nh, a ch ngun v ch ca hot ng truyn khng c cp nht. Trong mu (b), Tng hoc gim 1, 2, hay 4, a ch ngun v ch c tng hay gim ng bng kch thc d liu truy xut mt ln truyn. Byte, word, hay longword c th c ch nh l kch thc truy xut. Gi tr 1 cho byte, 2 cho word v 4 cho longword c s dng cho vic cp nht a ch. Hot ng ny th hin r d liu truyn trong vng lin tip nhau Trong mu (c), cng offset, a ch cp nht khng ph thuc vo kch thc d liu truy xut. Offset c ch nh bi DOFR, offset c cng vo a ch mi khi DMAC truyn d liu ca kch thc d liu truy xut. a ch c tnh bi offset c thit lp trong DOFR v ni dung ca thanh ghi DSAR v DDAR. Mc d DMAC ch tnh ton phn cng thm, hot ng tr offset thay v cng offset cng c th c thit lp bng cch thit lp gi tr ph nh ca offset vo trong thanh ghi DOFR. Trong trng hp ny, th gi tr trong thanh ghi DOFR s l gi tr b 2 ca offset cn tr. (1) Truyn s dng offset Hnh 9.18 Trnh by mt hot ng cn bn ca hot ng truyn s dng cng offset.
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Hnh 9.18 Hot ng cng offset Trong hnh 9.18, th vic cng thm offset c la chn cp nht a ch ngun v a ch ch c th c la chn l tng hay gim 1, 2, hay 4. Cch cp nht a ch ny ngha l d liu ti a ch m cch a ch ngun ln trc offset. D liu m c c t a ch cch a ch ln trc s c ghi trong mt vng lin tc trong di a ch ngun. (2) i chiu XY s dng offset (chuyn d liu dng ct sang dng hng sau khi truyn) Hnh 9.19 Trnh by hot ng i ch XY s dng vic cng thm offset trong cht truyn lp.
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Hnh 9.19 i chiu XY s dng vic cng offset trong ch truyn lp Trong hnh 9.19, a ch ngun (side) c ch nh cho vng lp bi thanh ghi DACR v hot ng cng offset c la chn. Gi tr offset c thit lp l 4 x kch thc d liu truy xut (v d, khi kch thc d liu truy xut l longword, H0000 0010 s c thit lp trong thanh ghi DOFR). Kch thc lp c thit lp l 4 x kch thc d liu truy xut (v d, khi kch thc d liu truy xut l longword, th kch thc lp s c thit lp l 4 x 4 = 16byte). Khi mt hot ng truyn bt u, th a ch ngun c cng thm offset mi khi d liu c truyn. D liu truyn c ghi vo a ch ch mt cch lin tc. Khi d liu 4 (xem hnh v) c truyn th c ngha rng kch thc lp ca hot ng truyn hon thnh, a ch ngun tr v a ch bt u truyn (a ch ca d liu 1 trn ngun) v mt ngt qung kt thc kch thc lp c yu cu. Trong khi ngt qung ny dng tm thi hot ng truyn, th ni dung ca DSAR c ghi vo a ch ca d liu 5 (data 5) bi CPU (khi m kch thc d liu truy xut l longword, th ghi data 1 address + 4). Khi m bit DTE trong thanh ghi DMDR c thit lp l 1, th hot ng truyn c phc hi t trng thi m hot ng truyn b dng. Do , cc hot ng c lp v d liu ngun c truyn n vng ch (i chiu XY)
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Hnh 9.20 Lc i chiu XY s dng cng offset trong ch truyn lp (3) Tr offset Khi thit lp gi tr ph nh vo thanh ghi DOFR, th phi thit lp gi tr b 2. Gi tr b 2 c tnh thng qua cng thc sau: Gi tr b 2 ca offset = 1 + ~offset V d: B 2 ca H0001 FFFF = HFFFE 0000 + H0000 0001 = HFFFE 0001 Gi tr b 2 c th c tnh bi cu lnh NEG.L 9.4.7 Cc thanh ghi trong qu trnh truyn DMA. Cc thanh ghi DMAC c cp nht bi hot ng truyn DMA. Gi tr c cp nht theo cc thit lp khc v trng thi truyn. Cc thanh ghi c cp nht l DSAR, DDAR, DTCR, cc bit BKSZH v BKSZ trong thanh ghi DBSR, v cc bit DTE, ACT, ERRF, ESIF, v DTIF trong thanh ghi DMDR. (1) thanh ghi a ch ngun DMA (~: o bit)
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Khi a ch ngun m c thit lp trong thang ghi DSAR c truy xut, ni dung ca thanh ghi DSAR l tn hiu xut v sau c cp nht a ch mi. Tng hay gim c th thit lp bi cc bit SAT1 v SAT0 trong thanh ghi DACR. Khi m SAT1 v SAT0 u c gi tr l 0, th a ch l c c nh. Khi m SAT1 = 0 v SAT0 = 1, th a ch s c cng vi gi tr offset. Khi SAT1 = 1 v SAT0 = 0, th a ch s c tng. Khi SAT1 = 1 v SAT0 = 1, th a ch s c gim. Kch thc tng hay gim ph thuc vo kch thc truyn d liu. Kch thc d liu c ch nh bi cc bit DTSZ1 v DTSZ0 trong thanh ghi DMDR. Khi m DTSZ1 = 0 v DTSZ0 = 0, th kch thc d liu truy xut l byte v a ch s tng hoc gim 1 n v. Khi m DTSZ1 = 0 v DTSZ0 = 1, th kch thc d liu truy xut s l word v a ch tng hay gim 2 n v. Khi m DTSZ1 = 1 v DTSZ0 = 0, th kch thc d liu l longword v a ch s tng hay gim 4 n v. Thm ch nu kch thc d liu truy xut ca a ch ngun l word hay longword, khi m a ch ngun khng tng thch vi kch thc word hay longword, th chu k bus s b chia thnh chu k byte hay word. Trong khi d liu ca mt word hay mt longword ang c c, th kch thc tng hay gim thay i thng qua kch thc d liu truy xut tht, v d +1 cho d liu byte v +2 cho d liu word. Sau khi mt word hay mt longword c c th, a ch ban u s c tng hay gim l tu thuc vo 2 bit SAT1 v SAT0 Trong ch truyn lp hoc truyn khi, khi m khi lng truyn ca truyn lp hay truyn khi hon tt trong v vng lp hay khi c ch nh l vng a ch ngun, th a ch ngun s tr v a ch bt u truyn v khng b nh hng bi a ch cp nht. Trong khi d liu ang c truyn, thanh ghi DSAR phi c truy xut theo longword. Nu word cao v word thp c c mt cch ring r, th c th s b c sai d liu v ni dung ca thanh ghi DSAR trong sut qu trnh truyn c th c cp nht bt chp s truy xut ca CPU. Hn na, DSAR ca knh ang truyn th khng th ghi vo n. (2) Thanh ghi a ch ch DMA Khi a ch ch c thit lp trong DDAR c truy xut, th ni dung ca DDAR l tn hiu xut v sau c cp nht gi tr a ch k tip. C th thit lp l tng hoc gim bng cch thit lp cc bit DAT1 v DAT0 trong thanh ghi DACR. Khi m DAT1 = 0 v DAT0 = 0 th a ch s c nh. Khi m DAT1 = 0 v DAT0 = 1 th a ch s c cng vo offset. Khi m DAT1 = 1 v DAT0 = 0 th a ch tng. Khi m DAT1 = 1 v DAT0 = 1 th a ch gim. Tng gim bao nhiu l tu thuc vo kch thc d liu truy xut. Kch thc d liu c ch nh bi cc bit DTSZ1 v DTSZ0 trong thanh ghi DMDR. Khi m DTSZ1 = 0 v DTSZ0 = 0 th kch thc d liu truy xut l byte v a ch c tng hay gim 1 n v. Khi m DTSZ1 = 0 v DTSZ0 = 1 th kch thc d liu truy xut l word v a ch c tng hay gim 2 n v. Khi m DTSZ1 = 1 v DTSZ0 = 0 th kch thc d liu truy xut l longword v a ch c tng hay gim 4 n v. Thm ch nu kch thc d liu truy xut ca
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a ch ngun l word hay longword, v a ch ngun khng tng thch vi word hay longword, th chu k ghi bus s b chia thnh chu k byte hay word. Trong khi mt word hay mt longword ca d liu ang c ghi vo, th s tng hay gim kch thc ph thuc vo kch thc d liu truy xut, v d, + 1 cho d liu byte hay +2 cho d liu word. Sau khi mt word hay mt longword c ghi, th a ch ban u s c tng hay gim l tu thuc vo 2 bit SAT1 v SAT0 Trong ch truyn lp v khi, khi kch thc d liu cn truyn c truyn xong trong khi m vng lp v vng khi c ch nh l vng a ch ch, th a ch ch s tr v a ch lc u truyn v n s khng b nh hng bi gi tr cp nht. Trong khi d liu ang c truyn, DDAR phi c truy xut longword. Nu word cao v word thp c truy xut mt cch ring r th, th d liu c th c c khng chnh xc v ni dung ca thanh ghi DDAR trong sut qu trnh truyn c th b cp nht bt chp s truy xut ca CPU. Hn na, DDAR ca knh ang truyn th khng th ghi. (3) Thanh ghi m truyn DMA (DTCR) m truyn ca DMA s gim i 1 sau mi ln truyn nu truyn d liu byte. Khi m byte d liu c truyn i, th DTCR s b gim i 1 n v. Khi m d liu word c truyn, th DTCR s b gim i 2 n v. Khi m d liu longword c truyn, th DTCR s b gim i 4 n v. Tuy nhin, khi m DTCR = 0, th ni dung ca DTCR s khng b thay i na v vy m s ln truyn s khng c m na Trong khi d liu ang c truyn, tt c cc bit c th b thay i. Thanh ghi DTCR phi c truy xut theo longword. Nu word cao v word thp c truy xut mt cch ring r th, th d liu c th c c khng chnh xc v ni dung ca thanh ghi DTCR trong sut qu trnh truyn c th b cp nht bt chp s truy xut ca CPU. Hn na, DTCR ca knh ang truyn th khng th ghi. Khi c mt s xung t xy ra gia vic cp nht a ch do hot ng truyn ca DMA v hot ng truy xut ca CPU, th CPU c u tin hn. Khi c s xung t xy ra gia vic c mt s thay i t 1, 2, hay 4 n 0 trong DTCR v hot ng ghi bi CPU (khc 0), th CPU s c u tin hn. Tuy nhin lc hot ng truyn s b dng. (4) Thanh ghi kch thc khi ca DMA (DBSR) Thanh ghi DBSR l c cho php trong ch truyn lp hoc khi. Cc bit t 31 n 16 ca thanh ghi DBSR c xem l BKSZH v cc bit t bt 15 n 0 trong thanh ghi DBSR c xem l BKSZ. BKAZH lu kch thc khi v lp v gi tr ca n s khng thay i. BKSZ c chc nng l mt b m cho kch thc khi v lp gi tr ca ni s b gim sau mi ln truyn. Khi m gi tr ca BKSZ thay i t 1 sang 0 bi mt ln truyn ca DMA, th gi tr 0 s khng c lu m gi tr BKSZH s c a vo BKSZ. Chnh v vy m 16 bit cao ca DBSR s khng c cp nht, DBSR c th c truy xut theo word.
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Thanh ghi DBSR ca knh ang truyn d liu th khng th ghi vo thanh ghi ny. (5) Bit DTE trong thanh ghi DMDR Mc d Vi vic ghi vo bit DTE trong thanh ghi DMDR ca CPU s cho php hoc cm d liu truyn, n s t ng b xo thng qua trng thi truyn ca DMA bi DMAC. Cc iu kin xo bit DTE bi DMAC l: Khi tng kch thc truyn c truyn xong Khi mt hot ng truyn c hon thnh bi mt ngt qung sai kch thc truyn Khi mt hot ng truyn c hon thnh bi mt ngt qung kt thc kch thc truyn Khi mt hot ng truyn c hon thnh bi mt ngt qung trn vng lp m rng Khi mt hot ng truyn b dng bi mt ngt qung NMI (khng th che) Khi mt hot ng truyn b dng bi mt li a ch Trng thi Reset Ch standby phn cng Khi mt hot ng truyn b dng bi hot ng ghi gi tr 0 vo bi DTE
Vic ghi vo cc thanh ca cc knh khi cc bit DTE tng ng c thit lp ln 1 l b cm (ngoi tr bit DTE). Khi vic thay i thit lp thanh ghi sau khi ghi 0 vo bit DTE, th phi chc chn rng bit DTE c xo.
Hnh 9.21 Tin trnh thay i thit lp thanh ghi cho knh ang truyn. (6) Bit ACT trong thanh ghi DMDR
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Bit ACT trong thanh ghi DMDR ch nh liu DMAC c ang trong trng thi idle hay ang trong trng thi kch hot. Khi DTE = 0 hoc l DTE = 1 v DMAC ang ch yu cu truyn, th bit ACT l 0. Ngc li (DMAC ang trong ch kch hot), th bit ACT l 1. Khi m cc knh ring r u b dng bi vic thit lp gi tr 0 vo bit DTE trong khi b truyn cha hon tt, th bt ACT vn cn mang gi tr 1. Trong ch truyn khi, th thm ch khi cc knh ring r u dng bi vic ghi gi tr 0 vo bit DTE, th vic truyn 1 khi s khng dng. Bit ACT vn l 1 cho n khi m hot ng truyn 1 khi kt thc. (7) Bit ERRF trong thanh ghi DMDR Khi c mt li a ch hay mt ngt qung NMI xy ra, th DMAC s xo cc bit DTE ca tt c cc knh dng truyn. Thm na, n s thit lp bit ERRF trong thanh ghi DMDR_0 ln 1 chi ra rng c mt li a ch hay mt ngt qung NMI xy ra bt chp liu DMAC ang hot ng hay khng (8) Bit ESIF trong thanh ghi DMDR Khi mt ngt qung do li a ch truyn, mt kt thc kch thc lp, hay mt trn vng lp m rng c yu cu, th bit ESIF trong thanh ghi DMDR c thit lp ln 1. Khi m c 2 bit ESIF v ESIE u c thit lp ln 1, th mt ngt qung thot khi truyn s c yu cu cho CPU hay DTC Bit ESIF c thit lp ln 1 khi m bit ACT trong thanh ghi DMDR b xo dng hot ng truyn sau khi chu k bus ca ngun ngt qung hon thnh. Bit ESIF s t ng b xo v mt yu cu truyn s b xo nu hot ng truyn c khi phc bi vic thit lp bit DTE ln 1 trong sut qu trnh p ng ngt qung. Chi tit tham kho, phn 9.7, Ngun ngt (9) Bit DTIF trong thanh ghi DMDR Bit DTIF trong thanh ghi DMDR c thit lp ln 1 sau khi tt c vng d liu u c truyn xong. Khi m c 2 bit DTIF v DTIE trong thanh ghi DMDR c thit lp ln 1, th mt ngt qung kt thc truyn bi m truyn s c yu cu cho CPU hay DTC Bit DTIF c thit lp ln 1 khi bit ACT trong thanh ghi DMDR c xo dng truyn sau khi chu k bus hon thnh. Bit DTIF t ng b xo v yu cu truyn s b xo nu hot ng truyn c phc hi bi vic thit lp bit DTE ln 1 trong sut qu trnh p ng ngt qung. Chi tit v cc ngt qung, tham kho phn 9.7, Cc ngun ngt. 9.4.8 u tin ca cc knh Cc knh ca DMAC c gn mc u tin nh sau: knh 0> knh 1> knh 2 > knh 3. Bng 9.5 trnh by mc u tin ca cc knh DMAC Bng 9.5 u tin ca cc knh DMAC
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Knh Knh 0 Knh 1 Knh 2 Knh 3
u tin Cao
Thp
Knh m c u tin cao nht s c la chn khi c mt yu cu t knh khc. Knh c la chn bt u truyn sau khi knh ang truyn gii phng bus. Vo lc ny, khi mt thnh phn s dng bus khc DMAC yu cu bus, th chu k cho thnh phn s dng bus c chn vo Trong ch truyn burst hoc khi th cc knh khng c chuyn Hnh 9.22 Trnh by mt v d truyn d liu khi c yu cu truyn ca 2 knh 0 v 2.
Hnh 9.22 V d v s iu ho u tin ca knh 9.4.9 Chu k bus cn bn ca DMA Hnh 9.23 trnh by mt v d v tn hiu thi gian ca mt chu k bus cn bn. Trong hnh 9.23, th d liu c truyn theo word t khng gian truy xut 2-trng thi 16-bit n khng gian truy xut 3-trng thi 8 bit. Khi m bus master c chuyn t DMAC n CPU, th d liu c c t a ch ngun v n c ghi vo a ch ch. Bus s khng c gii phng gia chu k c v ghi.
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Hnh 9.23 V d v gin thi gian bus ca b truyn DMA 9.4.10 Chu k bus trong ch a ch kp (1) Ch truyn bnh thng (ch Chu k stealing) Trong ch chu k stealing, th bus s c gii phng mi khi hon tt vic truyn mt n v d liu (mt byte, word, hay longword). CPU hay DTC mt mt hay nhiu chu k bus gii phng bus. Trong hnh 9.24, th tn hiu xut TEND c cho php v d liu c truyn theo word t khng gian truy xut ngoi 2-trng thi 16-bit n vng khng gian truy xut ngoi 2-trng thi 16-bit (external 16-bit 2-state access space) trong ch truyn bnh thng vi chu k stealing.
Hnh 9.24 V d v truyn d liu trong ch truyn bnh thng bi chu k stealing Trong hnh 9.25 v 9.26, tn hiu xut TEND c cho php v d liu c truyn theo longword t khng gian truy xut ngoi 2-trng thi 16-bit n khng
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gian truy xut ngoi 2-trng thi 16-bit trong ch truyn bnh thng bi chu k stealing Trong hnh 9.25, ngun truyn (DSAR) th khng tng thch vi d liu longword cn ch truyn (DDAR) th tng thch vi d liu longword. Hnh 9.26, ngun truyn (DSAR) th tng thch vi d liu longword cn ch truyn (DDAR) th khng tng thch vi d liu longword.
Hnh 9.25 V d ca truyn d liu trong ch bnh thng bi chu k stealing (ngun truyn DSAR = a ch l v a ch ngun tng)
Hnh 9.26 V d ca truyn d liu trong ch bnh thng bi chu k stealing (ngun truyn DDAR = a ch l v a ch ch gim) (2) Ch truyn bnh thng (ch burst) Trong ch burst, mt byte, mt word, hay longword d liu tip tc c truyn cho n khi m iu kin dng c tho mn. Khi m hot ng truyn burst bt u, th mt yu cu t mt knh m c u tin hn s b hon cho n khi m truyn burst hon tt.
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Trong hnh 9.27 th tn hiu xut TEND l c cho php v d liu c truyn theo word t khng gian truy xut ngoi 2-trng thi 16-bit n khng gian truy xut ngoi 2-trng thi 16-bit trong ch truyn bnh thng bi cch truy xut burst.
Hnh 9.27 V d truyn d liu trong ch truyn bnh thng bi cch truy xut burst (3) Ch truyn khi Trong ch truyn khi, th bus s c gii phng mi khi 1-block d liu (trong 1 ln truyn) c truyn xong Hnh 9.28, tn hiu xut TEND c cho php v d liu c truyn theo word t khng gian truy xut ngoi 2-trng thi 16-bit n khng gian truy xut ngoi 2-trng thi 16-bit trong ch truyn khi.
Hnh 9.28 v d v truyn d liu trong ch truyn khi (4) iu chnh kch hot bi cnh xung ca DREQ
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Hnh 9.29 trnh by mt v d ca ch truyn bnh thng c kch hot bi cnh xung ca tn hiu DREQ . Tn hiu DREQ c ly mu mi chu k t cnh ln k tip ca tn hiu B ngay lp tc sau khi chu k ghi vo bit DTE. Khi mt mc thp ca tn hiu DREQ xut hin trong khi mt yu cu truyn bi tn hiu DREQ l cho php, th yu cu truyn s c gi trong DMAC. Khi DMAC c kch hot, th yu cu truyn s b xo v bt u kim tra mc cao ca tn hiu DREQ cho s kim tra cnh xung. Nu mt mc cao ca tn hiu DREQ duy tr cho n khi ht chu k ghi DMA, th vic nhn yu cu truyn tip theo c phc hi v sau mc thp ca tn hiu DREQ s c kim tra. Hot ng ny lp li cho n khi hot ng truyn kt thc. (xem hnh bn di)
Hnh 9.29 V d v truyn d liu trong ch truyn bnh thng c kch hot bi cnh xung ca DREQ (5) iu chnh kch hot bi mc thp ca DREQ Hnh 9.30 trnh by 1 v d v ch truyn bnh thng c kch hot bi mc thp ca tn hiu DREQ . Tn hiu DREQ c ly mu mi chu k t cnh ln tip theo ca tn hiu B ngay lp tc sau khi m bit chu k ghi DTE. Khi m mc thp ca tn hiu DREQ xut hin trong khi mt yu cu truyn bi tn hiu DREQ c cho php, th yu cu truyn s c gi trong thanh ghi DMAC. Khi m DMAC c kch hot, th yu cu truyn s b xo. Vic nhn yu cu truyn tip theo s c phc hi sau khi hon thnh chu k ghi v sau
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mt mc thp ca tn hiu DREQ s c kim tra. Hot ng ny s lp li cho n khi hot ng truyn hon tt.
Hnh 9.30 V d truyn d liu trong ch truyn bnh thng c kch hot bi mc thp ca tn hiu DREQ Hnh 9.31 trnh by mt v d v ch truyn khi m c kch hot bi mc thp ca tn hiu DREQ . Tn hiu DREQ c ly mu mi chu k t cnh ln tip theo ca tn hiu B ngay lp tc sau khi m bit chu k ghi DTE. Khi mc thp ca tn hiu DREQ xy ra trong khi yu cu truyn bi tn hiu
DREQ c cho php, th yu cu truyn s c gi trong b iu khin truyn
DMAC. Khi DMAC c kch hot, th yu cu truyn s b xo. Vic nhn yu cu truyn tip theo c phc hi sau khi m chu k ghi c hon tt v sau mc thp ca tn hiu DREQ c kim tra. Hot ng ny s lp li cho n khi b truyn hon tt
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Hnh 9.31 v d ca truyn d liu trong ch truyn khi c kch hot bi mc thp ca tn hiu DREQ (6) iu chnh kch hot bi mc thp ca DREQ vi NRD = 1 Khi bit NRD trong thanh ghi DMDR c thit lp ln 1, th vic iu chnh nhn yu cu truyn tip theo s b tr hon li mt chu k. Hnh 9.32 trnh by mt v d ca ch truyn bnh thng c kch hot bi tn hiu mc thp ca DREQ vi NRD =1. Tn hiu DREQ c ly mu mi chu k t cnh ln tip theo ca tn hiu B ngay lp tc sau khi m bit chu k ghi DTE. Khi mt mc thp ca tn hiu DREQ c duy tr trong khi mt yu cu truyn bi tn hiu DREQ c cho php, th mt yu cu truyn s c gi trong b iu khin truyn DMAC. Khi m DMAC c kch hot, th yu cu truyn s b xo. Vic nhn yu cu truyn tip theo c phc hi sau khi hon tt chu k ghi v sau mt mc thp ca tn hiu DREQ s c kim tra. Hot ng ny s c lp cho n khi hot ng truyn hon tt.
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Hnh 9.32 V d truyn d liu trong ch truyn d liu bnh thng c kch hot bi mc thp tn hiu DREQ vi NRD = 1 9.4.11 Cc chu k bus trong ch a ch n (1) Ch a ch n (c v chu k stealing) Trong ch a ch n d liu 1 byte, 1 word hay 1 longword c truyn vi mt yu cu truyn n v sau khi truyn mt n v d liu th bus tm thi c gii phng. Trong thi gian gii phng b ny, th mt hay nhiu chu k ca CPU hay DTC s c thc thi. Trong hnh 9.33, th tn hiu xut TEND c cho php v d liu truyn theo byte t khng gian truy xut ngoi 2-trng thi 8-bit n thit b ngoi trong ch a ch n (c)
Hnh 9.33 V d v truyn d liu trong ch a ch n (c byte) (2) Ch a ch n (Ghi v chu k Stealing)
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Trong ch a ch n, d liu 1 byte, word, hay longword c truyn vi mt yu cu n v sau khi hot ng truyn th bus s tm thi c gii phng. Trong thi gian gii phng bus ny, CPU s thc hin mt hay nhiu chu k bus. Hnh 9.34, tn hiu xut TEND c cho php v d liu c truyn theo byte t khng gian truy xut 2-trng thi 8-bit n thit b ngoi trong ch a ch n (ghi).
Hnh 9.34 V d v truyn d liu trong ch a ch n (ghi byte) (3) iu chnh kch hot bi cnh xung DREQ Hnh 9.35 trnh by mt v d ca ch a ch n c kch hot bi tn hiu cnh xung ca DREQ . Tn hiu DREQ c ly mu c mi chu k t cnh ln tip theo ca B ngay lp tc sau khi m bit chu k ghi DTE. Khi mt mc thp ca tn hiu DREQ c kim tra trong khi yu cu truyn bi tn hiu DREQ c cho php, th mt yu cu truyn s c gi trong b iu khin truyn DMAC. Khi m DMAC c kch hot, th yu cu truyn s b xo v bt u kim tra mc cao ca tn hiu DREQ cho s kim tra cnh xung ca tn hiu ny. Nu mc cao ca tn hiu DREQ c duy tr cho n khi hon tt mt chu k n, th vic nhn yu cu truyn k tip yu cu c phc hi v sau mt mc thp ca tn hiu DREQ s c kim tra. Hot ng ny c lp li cho n khi m hot ng truyn c hon thnh.
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Hnh 9.35 V d v truyn d liu trong ch a ch n c kch hot bi cnh xung ca DREQ (4) iu chnh hot ng bi mc thp ca DREQ Hnh 9.36 Trnh by mt v d ca hot ng truyn bnh thng c kch hot bi tn hiu mc thp ca DREQ . Tn hiu DREQ c ly mu mi chu k t cnh ln tip theo ca B ngay lp tc sau khi m bit chu k ghi DTE. Khi mt cnh xung ca tn hiu DREQ c pht hin trong khi yu cu truyn bi tn hiu DREQ c cho php, th yu cu truyn s c gi trong DMAC. Khi m DMAC c kch hot, th yu cu truyn s b xo. Vic nhn yu cu truyn tip theo s c phc hi sau hot ng ca chu k n v sau mt mc thp ca tn hiu DREQ s c kim tra. Hot ng ny c lp li cho n khi hot ng truyn hon tt.
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Hnh 9.36 V d v truyn d liu trong ch a ch n c kch hot bi mc thp ca DREQ (5) iu chnh kch hot bi tn hiu mc thp ca DREQ vi NRD = 1 Khi bit NRD trong thanh ghi DMDR c thit lp l 1, th vic nhn yu cu truyn s b tr hon mt chu k. Hnh 9.37 Trnh by mt v d v ch truyn a ch n c kch hot bi tn hiu mc thp ca DREQ vi NRD = 1 Tn hiu DREQ c ly mu mi chu k t cnh ln tip theo ca B ngay lp tc sau khi m bit chu k ghi DTE. Khi m mc thp ca tn hiu DREQ c duy tr trong khi mt yu cu truyn bi tn hiu DREQ c cho php, th mt yu cu truyn s c gi trong DMAC. Trong khi DMAC c kch hot, th yu cu truyn s b xo. Vic nhn yu cu truyn tip theo c phc hi sau khi mt chu k ca yu cu truyn trong khong thi gian m NRD = 1 trong mt chu k n v sau mc thp ca tn hiu DREQ s c kim tra. Hot ng ny s c lp cho n khi hot ng truyn hon tt.
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Hnh 9.37 V d v truyn d liu trong ch a ch n c kch hot bi mc thp ca tn hiu DREQ vi NRD = 1
9.5 Kt thc truyn DMA

Cc hot ng kt thc truyn khc nhau thng qua iu kin kt thc truyn. S hon tt truyn DMA ch ra rng cc bit DTE v ACT trong thanh ghi DMDR b chuyn t 1. (1) Kt thc truyn bi vic thay i thanh ghi DTCR t 1, 2, hay 4 Khi thanh ghi DTCR chuyn t 1, 2, hay 4, th mt b truyn DMA ca mt knh hon tt. Bit DTE trong thanh ghi DMDR b xo v bit DTIF trong thanh ghi DMDR c thit lp ln 1. Vo lc ny, khi m bit DTIE trong thanh ghi DMDR c thit lp l 1, th mt ngt qung kt thc truyn do m truyn. Khi m gi tr trong DTCR l 0 trc khi truyn, th qu trnh truyn s khng b dng li. (2) Kt thc truyn bi ngt qung kch thc truyn Khi cc iu kin sau c tho mn trong khi bi TSEIE trong thanh ghi DMDR c thit lp l 1, mt li kch thc truyn s xy ra v hot ng truyn DMA s dng li. Vo lc ny, khi bit DTE trong thanh ghi DMR c xo v bit ESIF trong thanh ghi DMDR c thit lp l 1 Trong ch truyn bnh thng v ch truyn lp, khi hot ng truyn tip theo c yu cu trong khi hot ng truyn b cm v gi tr ca DTCR nh hn kch thc truy xut.
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Trong ch truyn khi, khi hot ng truyn tip theo c yu cu trong khi b truyn b cm v gi tr DTCR nh hn kch thc ca khi Khi bit TSEIE trong thanh ghi DMDR b xo, d liu c truyn cho n khi gi tr DTCR t ti 0. Li kch thc truyn s khng pht sinh. Hot ng mi ch truyn c trnh by bn di. Trong ch truyn bnh thng v ch lp, khi gi tr DTCR nh hn kch thc d liu truy xut, th d liu c truyn theo byte Trong ch truyn khi, khi gi tr DTCR nh hn kch thc khi, th kch thc c ch nh bi d liu trong thanh DTCR s c truyn thay v hot ng truyn kch thc khi ca d liu. Hot ng truyn c truyn theo byte (3) Kt thc truyn bi ngt qung kt thc kch thc lp Trong ch truyn lp, khi hot ng truyn tip theo c yu cu sau khi hon tt mt hot ng truyn 1 khi trong khi bit RPTIE trong thanh ghi DACR c thit lp ln 1, th mt ngt qung kt thc truyn c yu cu. Khi ngt qung c yu cu hon tt truyn DMA, th bit DTE trong thanh ghi DMDR s c xo v bit ESIF trong thanh ghi DMDR c thit lp ln 1. Theo iu kin ny, vic thit lp bit DTE ln 1 phc hi hot ng truyn. Trong ch truyn khi, khi hot ng truyn tip theo c yu cu sau khi hon thnh mt hot ng truyn 1 khi, th ngt qung kt thc kch thc truyn c th c yu cu. (4) Kt thc truyn bi ngt qung trn vng lp m rng Khi mt trn vng lp m rng xy ra trong khi vng lp m rng c ch nh v bit SARIE hay DARIE trong thanh ghi DACR c thit lp ln 1, th mt ngt qung do vng lp m rng s c yu cu. Khi ngt qung c yu cu, b truyn DMA s b dng, bit DTE trong thanh ghi DMDR s b xo, v bit ESIF trong thanh ghi DMDR c thit lp ln 1. Trong ch truyn khi, thm ch nu mt ngt qung vng lp m rng xy ra trong sut 1 hot ng truyn 1 khi n v, th d liu vn cn c truyn. Hot ng truyn s khng b dng bi ngt qung trn vng lp m rng tr khi hot ng truyn hin ti hon tt. (5) Kt thc truyn bi vic xo bit DTE trong thanh ghi DMDR Khi bit DTE trong thanh ghi DMDR b xo bi CPU, th hot ng truyn hon tt sau khi chu k DMA hin ti. Trong ch truyn khi, mt hot ng truyn DMA s c hon thnh sau khi d liu mt khi c truyn. (6) Kt thc truyn bi ngt qung NMI Khi mt ngt qung NMI c yu cu, cc bit DTE cho tt c cc knh u b xo v bit ERRF trong thanh ghi DMDR_0 s b thit lp ln 1. Khi mt ngt qung NMI c yu cu trong khi hot ng truyn DMA ang hot ng, th
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hot ng truyn s b p phi dng li. phc hi hot ng truyn DMA sau khi mt ngt qung c yu cu, th xo bit ERRF v sau thit lp bit DTE cho cc knh ln 1. (a) Ch truyn bnh thng v ch truyn lp Trong ch a ch i, mt hot ng truyn DMA c hon tt sau khi hon thnh chu k ghi 1 n v truyn. Trong ch truyn n, th hot ng truyn DMA c hon tt sau khi hon thnh chu k cho mt n v truyn. (b) Ch truyn khi Mt hot ng truyn s b p phi ng. V kch thc 1 khi cha c truyn xong, nn hot ng khng c m bo. Trong ch a ch i, chu k ghi tng ng vi chu k c c thc hin. iu ny tng t trong ch truyn bnh thng (a). (7) Kt thc truyn bi li a ch Khi mt li a ch xy ra, cc bit DTE ca tt c cc knh u b xo v bit ERRF trong thanh ghi DMDR_0 c thit lp ln 1. Khi mt li a ch xy ra trong khi DMA ang truyn d liu, th hot ng truyn s b dng. thc hin hot ng truyn DMA sau mt li a ch, th xo bit ERRF v sau thit lp cc bit DTE ca cc knh. (8) Kt thc truyn bi ch standby phn cng hay v mt hot ng reset. DMAC c khi ng bi mt hot ng reset v mt s chuyn i sang ch standby phn cng. Hot ng truyn s khng c m bo.
9.6 Mi quan h gia DMAC v cc thnh phn s dng bus khc

9.6.1 Chc nng iu khin u tin ca CPU so vi DMAC Chc nng iu khin ch u tin ca CPU so vi DMAC c th c s dng thng qua vic thit lp thanh ghi iu khin u tin CPUPCR. Chi tit, tham kho phn 5.7, Chc nng iu khin u tin ca CPU so vi DTC v DMAC. Mc u tin ca DMAC c ch nh bi cc bit CPUP0 n CPUP2. Gi tr ca cc bit CPUP0 n CPUP2 c cp nht thng qua u tin p ng ngoi l (exception handling priority). Nu iu khin u tin ca CPU c cho php bi bit CPUPCE trong thanh ghi CPUPCR, khi CPU c u tin cao hn DMAC, th mt yu cu truyn cho knh tng ng s b che v hot ng truyn s khng c kch hot. Khi mt knh khc c u tin cao hn hay bng CPU, th yu cu truyn s c nhn bt chp u tin gia cc knh v hot ng truyn c kch hot. Nu mc u tin ca yu cu ngt qung b che bi chc nng iu khin u tin ca CPU b thay i hoc u tin ca CPU b thay i, th yu cu truyn c th c nhn v hot ng truyn c khi ng.
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Khi bit CPUPCE b xo, th n c xem nh l mc u tin thp nht. Cc yu cu truyn b che u b hon. Nu mt hot ng truyn b hon, n s b xo xung bi vic xo bit DTE. 9.6.2 Gii quyt tranh chp gia DMAC v cc thnh phn s dng bus khc Khi cc chu k truyn DMA c thc hin mt cch lin tc, th cc chu k bus ca cc bus master khc c th c thm vo gia cc chu k truyn. DMAC c th gii phng tm thi bus chuyn bus cho mt master bus khc Cc chu k truyn DMA lin tip cc th khng b chia ra tu vo vic thit lp ch truyn t c tc truy xut cao. Cc chu k c v ghi ca b truyn DMA khng th b chia s. Vic lm ti, gii phng bus bn ngoi, v cc chu k ca bus master trn chip (CPU v DTC) khng c thm vo gia cc chu k c v ghi ca hot ng truyn DMA. Trong ch truyn khi v mt yu cu t ng truyn bi truy xut burst, th cc chu k ca truyn DMA s c thc hin mt cch lin tc. Trong thi khon ny, v DMAC c u tin cao hn CPU v DTC, nn truy xut n vng khng gian ngoi s b hon (bit IBCCS trong thanh ghi iu khin bus 2 (BCR2) b xo). Khi bus c chuyn sang cho 1 knh khc hay mt yu cu t ng bi chu k stealing, th cc chu k bus ca DMAC v bus master trn chip s c thc hin. Khi chc nng gii quyt tranh chp gia DMAC v bus master khc c cho php bi vic thit lp bit IBCCS trong thanh ghi BCR2, th bus s c chp nhn cc chu k bus m khng b lm ri ra. Chi tit tham kho phn 6 iu khin Bus (BSC) Mt xung t c th xy ra gia vic truy xut khng gian ngoi ca DMAC v mt chu k lm ti hay mt chu k gii phng bus ngoi. Thm ch nu mt burst hay mt hot ng truyn khi c thc hin bi DMAC, th hot ng truyn s tm thi b dng v mt chu k lm ti hay vic gii phng bus ngoi c thm vo BSC (Khi truy xut ngoi ca DTC v CPU khng c u tin hn DMAC, th hot ng truyn s khng hot ng cho n khi DMAC gii phng bus). Trong ch a ch i, th DMAC gii phng bus ngoi sau khi chu k c vng khng gian ngoi. V cc chu k c v ghi l khng c lm ri ra, nn bus s khng c gii phng. Mt truy xut khng gian bn trong (b nh trn chip v cc thanh ghi xut nhp) ca DMAC v mt chu k gii phng bus ngoi c th c thc hin trong cng mt lc.
9.7 Cc ngun ngt

Cc ngun ngt l mt ngt qung kt thc truyn bi m truyn v mt ngt qung chm dt truyn m c pht sinh khi mt hot ng truyn kt thc trc khi m truyn t n 0. Bng 9.6 Cc ngun ngt v u tin.
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Vit tt
Cc ngun ngt
u tin Cao
DMTEND0 Ngt qung kt thc truyn bi m truyn ca knh 0 DMTEND1 Ngt qung kt thc truyn bi m truyn ca knh 1 DMTEND2 Ngt qung kt thc truyn bi m truyn ca knh 2 DMTEND3 Ngt qung kt thc truyn bi m truyn ca knh 3 DMEEND0 Ngt qung do li kch thc truyn knh 0 Ngt qung do kt thc kch thc lp knh 0 Ngt qung do trn vng lp m rng trn a ch ngun ca knh 0 Ngt qung do trn vng lp m rng trn a ch ch ca knh 0 DMEEND1 Ngt qung do li kch thc truyn knh 1 Ngt qung do kt thc kch thc lp knh 1 Ngt qung do trn vng lp m rng trn a ch ngun ca knh 1 Ngt qung do trn vng lp m rng trn a ch ch ca knh 1 DMEEND2 Ngt qung do li kch thc truyn knh 2 Ngt qung do kt thc kch thc lp knh 2 Ngt qung do trn vng lp m rng trn a ch ngun ca knh 2 Ngt qung do trn vng lp m rng trn a ch ch ca knh 2 DMEEND3 Ngt qung do li kch thc truyn knh 3 Ngt qung do kt thc kch thc lp knh 3 Ngt qung do trn vng lp m rng trn a ch ngun ca knh 3 Ngt qung do trn vng lp m rng trn a ch ch ca knh 3
Thp Mi ngt qung c cho php hay cm bi cc bit DTIE v ESIE trong thanh ghi DMDR cho tng knh tng ng. Mt ngt qung DMTEND c pht sinh bi s kt hp ca cc bit DTIF v DTIE trong DMDR. Mt ngt qung DMEEND c
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pht sinh bi s kt hp ca cc bit ESIF v ESIE trong thanh ghi DMDR. Cc ngun ngt DMEEND l khng c phn bit. u tin gia cc knh l c qut nh bi b iu khin ngt qung v c trnh by trong bng 9.6. Chi tit, tham kho phn 5, B iu khin ngt qung. Mi ngun ngt qung c ch nh bi bit cho php ngt qung trong thanh ghi tng ng vi tng knh. Mt ngt qung kt thc truyn bi m truyn, mt ngt qung li kch thc truyn, mt ngt qung kt thc kch thc truyn, mt ngt qung trn vng lp m rng trn a ch ngun v mt ngt qung trn vng lp m rng trn a ch ch l c cho php hot cm bi bit DTIE trong thanh ghi DMDR, bit TSEIE trong thanh ghi DMDR, bit RPTIE trong thanh ghi DACR, bit SARIE trong thanh ghi DACR, v bit DARIE trong thanh ghi DACR. Mt ngt qung kt thc truyn bi m truyn c pht sinh khi m bit DTIF trong thanh ghi DMDR c thit lp ln 1. bit DTIF c thit lp ln 1 khi DTCR tr thnh f0 bi mt hot ng truyn trong khi bit DTIE trong thanh ghi DMDR c thit lp ln 1. Mt ngt qung khc ngt qung kt thc truyn bi m truyn sinh ra khi bit ESIF trong thanh ghi DMDR c thit lp ln 1. bit ESIF c thit lp ln 1 khi cc iu kin c tho mn bi hot ng truyn trong khi bit cho php ngt c thit lp ln 1. Mt ngt qung li kch thc truyn c pht sinh khi mt hot ng truyn tip theo khng th c thc thi bi v gi tr trong DTCR nh hn kch thc truyn, iu ny c ngha l kch thc d liu truy xut ca hot ng truyn khng th c thc hin. Trong ch truyn khi, th kch thc khi c so snh vi gi tr DTCR quyt nh li truyn. Mt ngt qung kt thc kch thc lp khi yu cu truyn c yu cu sau khi hon tt vic truyn d liu trong ch truyn lp. Thm ch khi vng lp khng c ch nh trong thanh ghi a ch, hot ng truyn c th b dng mt cch nh k thng qua kch thc lp. Vo lc ny, khi mt ngt qung kt thc truyn bi m truyn c pht sinh, th bit ESIF c thit lp ln 1. Mt ngt qung bi mt trn vng lp m rng trn a ch ngun v a ch ch c pht sinh khi a ch vt qu vng lp m rng (trn). Vo lc ny, Khi mt ngt qung kt thc truyn bi m truyn, th bit ESIF c thit lp ln 1. Hnh 9.38 l mt s khi ca cc ngt qung v c ngt qung. xo mt ngt qung, xo bit DTIF hay ESIF trong thanh ghi DMDR trong hm p ng ngoi l hay tip tc truyn bi vic thit lp bit DTE trong thanh ghi DMDR sau khi thit lp thanh ghi. Hnh 9.39 Trnh by tin trnh phc hi hot ng truyn bi vic xo mt ngt qung.
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Hnh 9.38 Ngt qung v cc ngun ngt qung
Hnh 9.39 V d tin trnh ca vic phc hi truyn bi vic xo ngun ngt qung
9.8 Ch s dng
1. Truy xut thanh ghi DMAC trong sut qu trnh hot ng Tr vic xo bit DTE trong thanh ghi DMDR ra th vic thit lp cho knh trong lc n ang hot ng phi khng c thay i (k c trng thi ch). Vic thit lp cc thanh ghi phi c thay i trong trng thi cm truyn(transfer prohibited state).
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2. Vic thit lp chc nng dng module Hot ng DMAC c th c cho php hay cm bi thanh ghi iu khin dng module. DMAC c cho php bi gi tr khi ng. Vic thit lp bit MSTPA13 trong thanh ghi MSTPCRA s dng xung clock c cung cp cho DMAC v DMAC s vo trng thi dng module. Tuy nhin, khi mt hot ng truyn ca mt knh c cho php hay khi mt ngt qung ang c yu cu, th bit MSTPA13 khng th b thit lp ln 1. Xo bit DTE, xo bit DTIF hay DTIE trong thanh ghi DMDR, v sau thit lp bit MSTPA13. Khi xung clock b dng, th cc thanh ghi DMAC khng th b truy xut. Tuy nhin, vic thit lp cc thanh ghi sau l hp l trong trng thi dng module. Phi cm chng trc khi vo trng thi dng, nu cn thit. Bit TENDE trong DMDR l 1 (tn hiu xut TEND c cho php) Bit DACK trong thanh ghi DMDR l 1 (tn hiu xut DACK c cho php) 3. Kch hot bi cnh xung ca DREQ S kim tra cnh xung ca DREQ l ng b vi hot ng bn trong ca DMAC. A. Trng thi ch yu cu kch hot: ch kim tra mc thp ca tn hiu DREQ . Mt s chuyn i sang 2. c thc hin B. Trng thi ch truyn: ch mt hot ng truyn DMAC. Mt s chuyn i sang 3. c thc hin. C. Trng thi truyn cm: ch kim tra mc cao ca tn hiu DREQ . Mt s chuyn i sang 1. s c thc hin Sau khi mt b truyn c cho php, th mt s chuyn i sang 1. c thc hin. Bi vy tn hiu DREQ c ly mu bi s kim tra mc thp khi m s kch hot u tin sau khi b truyn DMAC c cho php. 4. S cho php ngun kch hot Vo lc mi nhn c ngun kch hot, th mt mc thp s c kim tra bt chp vic thit lp ca cnh xung ca DREQ hay s kim tra mc thp. Chnh v vy, nu tn hiu DREQ c a xung mc cao trc khi thit lp DMDR, th mc thp s c nhn nh l mt yu cu truyn. Khi DMAC c kch thot, th xa tn hiu DREQ cho trng thi truyn k tip.
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Chng 10 B iu khin truyn d liu DTC

Thit b ny bao gm mt b iu khin truyn d liu DTC. B iu khin truyn d liu DTC c th c kch hot truyn d liu bi mt yu cu ngt qung.
10.1 Cc tnh nng

C th truyn vi s lng knh bt k: C 69 ngun kch hot cho b truyn d liu Cho php chuyn nhiu d liu cho mt ngun ngt (chuyn d liu dy chuyn) Chuyn d liu dy chuyn c th c ch nh sau hot ng chuyn d liu (khi m counter c gi tr l 0) C 3 ch truyn d liu: Bnh thng/Lp/Khi a ch ngun v ch ca vic chuyn d liu c th c chn la theo cch thc tng/gim/c nh C th chn la ch a ch ngn hay y a ch ngn Thng tin truyn c cp pht trn gii hn 3 longword a ch ngun v ch ca chuyn d liu c th c xc nh bi 24 bit c th la chn trc tip vng khng gian 256Mbyte a ch y Thng tin truyn c cp pht trn gii hn 4 longword a ch ngun v ch ca chuyn d liu c th c xc nh bi 32 bit cho php la chn trc tip vng khng gian 4Gbyte. Kch thc ca d liu c truyn c th c thit lp theo byte, word hay longword Chu k bus s b chia ra nu nh mt a ch l c dng xc nh v tr ca mt word hay mt longword cn c truyn Chu k bus cng c chia nh ra nu mt a ch c dng 4n+2 c dng xc nh v tr mt d liu longword cn c truyn Mt ngt qung CPU c th c yu cu l mt ngt qung m kch hot DTC Mt ngt qung CPU c th c yu cu sau khi hon tt chuyn mt n v d liu Mt ngt qung CPU c th c yu cu sau khi hon tt chuyn mt khi d liu xc nh. C th kch hot DTC bng phn mm
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C th ch nh hot ng b qua vic c thng tin truyn Hot ng b qua vic ghi tr li thng tin truyn c nh a ch ngun v ch truyn. C th xc nh ch dng module Hnh 10.1 Trnh by mt s khi ca b iu khin truyn d liu DTC. Thng tin truyn ca DTC c th c cp pht cho vng d liu *. Khi thng tin truyn d liu c cp pht RAM trn chip, th DTC kt ni vi RAM trn chip thng qua bus 32-bit, cho php vic c v ghi 1 trng thi 32-bit ca thng tin truyn d liu DTC Ch : * khi m thng tin truyn c lu trn RAM trn chip, th bit RAME trong thanh ghi SYSCR phi c thit lp l 1.
Hnh 10.1 S khi ca DTC
10.2 c t thanh ghi

B iu khin truyn d liu c cc thanh ghi sau: Thanh ghi ch A (MRA) Thanh ghi ch B (MRB) Thanh ghi a ch ngun (SAR)
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Thanh ghi a ch ch (DAR) Thanh ghi counter A (CRA) (thanh ghi m truyn) Thanh ghi counter B (CRB) CPU khng th truy xut trc tip 6 Thanh ghi MRA, MRB, SAR, DAR, CRA, CRB. Ni dung ca nhng thanh ghi ny c lu trn vng d liu nh l nhng thng tin truyn. Khi c mt tn hiu yu cu kch hot DTC, th DTC c mt a ch bt u ca thng tin truyn m c lu trong vng d liu thng qua a ch vector, c thng tin truyn, v chuyn d liu. Sau khi truyn d liu, n cp nht thng tin truyn li vo vng d liu. Thanh ghi cho php A n H (DTCERA n DTCERH) Thanh ghi iu khin (DTCCR) Thanh ghi nn vector (DTCVBR) CPU c th truy xut trc tip cc thanh ghi DTCERA n DTCERH, DTCCR, v DTCVBR. 10.2.1 Thanh ghi ch A (MRA) Thanh ghi MRA la chn ch hot ng ca DTC. CPU khng th truy xut trc tip n thanh ghi MRA.
Bit
Tn Bit
Gi tr khi ng Khng xc nh
R/W
c t
7 6
MD1 MD0
---
Cc bit la chn ch DTC 00: Ch bnh thng 01: Ch lp 10: Ch chuyn khi 11: Cm thit lp
Sz1
Khng xc nh Khng xc nh Khng xc
---
Cc bit la chn kch thc d liu ca DTC 00: chuyn theo kch thc l byte 01: chuyn theo kch thc l word 10: chuyn theo kch thc l longword 11: cm thit lp Cc bit la chn ch a ch ngun
Sz0
---
SM1
---
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nh 2 SM0 Khng xc nh ---
N ch nh thao tc s thc hin sau mt hot ng chuyn d liu 0X: gi tr trong thanh ghi SAR khng thay i (hot ng ghi tr li vo thanh ghi ny s b b qua) 10: gi tr trong thanh ghi SAR s tng sau mi ln chuyn d liu (tng 1 nu kch thc d liu truy xut l byte, 2: word, 4: longword) 11: gi tr trong thanh ghi SAR s gim sau mi ln chuyn d liu (gim1 nu kch thc d liu truy xut l byte, 2: word, 4: longword)
1,0
---
---
Khng dng Gi tr ban u khng th thay i
Ghi ch: X: khng quan tm 10.2.2 Thanh ghi ch B (MRB) Thanh ghi MRB l thanh ghi la chn ch ca b iu khin truyn d liu DTC. CPU khng th truy xut trc tip MRB.
Bit
Tn Bit
Gi tr khi ng Khng xc nh
R/W
c t
CHNE
---
Cho php chuyn d liu dy chuyn Bit ny cho php truyn d liu dy chuyn. Chi tit, tham kho 10.5.7, Truyn d liu dy chuyn. iu kin truyn d liu dy chuyn c la chn bi bit CHNS 0: Cm truyn d liu dy chuyn 1: Cho php truyn d liu dy chuyn
CHNS
Khng xc nh
---
iu kin truyn d liu dy chuyn Xc nh iu kin truyn d liu dy chuyn. Nu truyn d liu theo kiu dy chuyn, th
325
s kim tra counter s khng c thc hin v c ngun kch hot hay DTCER s khng b xo. 0: Truyn dy chuyn mi lc 1: Truyn dy chuyn ch khi m m truyn bng 0 (transfer counter =0) 5 DISEL Khng xc nh --La chn ngt DTC Khi bit ny c thit lp l 1, th mt ngt qung s c pht sinh ngay sau khi truyn xong 1 n v d liu. Khi bit ny c xo, mt yu cu ngt qung CPU ch xy ra khi m ton b vic truyn d liu hon tt. --La chn ch truyn ca DTC Ch nh vng lp hay vng khi l ngun hay ch trong sut qu trnh chuyn d liu trong ch lp hay khi 0: Ch nh vng lp/khi l ch 1: Ch nh vng lp/khi l ngun 3 DM1 Khng xc nh Khng xc nh --Bit Ch a ch ngun Ch nh thao tc s thc hin sau mt hot ng truyn d liu --0X: DAR s b c nh (hot ng ghi tr li vo thanh ghi ny s b b qua) 10: DAR s tng sau mt hot ng truyn d liu (tng 1 nu d liu truy xut l byte, 2 nu l word, 4 nu l longword) 11: DAR s gim sau mt hot ng truyn d liu (gim 1 nu d liu truy xut l byte, 2 nu l word, 4 nu l longword) 1, 0 --0 --Khng dng Gi tr ban u s khng b thay i Ghi ch: X: khng quan tm 10.2.3 Thanh ghi a ch ngun (SAR) Thanh ghi SAR l mt thanh ghi 32-bit m ch r a ch ngun ca d liu s c truyn bi b iu khin truyn d liu DTC.
DTS
Khng xc nh
DM0
326
Trong ch a ch full, th 32-bit ca thanh ghi SAR l hp l. Trong ch a ch ngn, th ch c 24-bit thp l hp l v cc bit t 31 n 24 s b b qua. Nu mt truy xut d liu dng word hay longword c thc hin trong khi thanh ghi SAR ang cha mt a ch l hay nu truy xut longword trong khi thanh ghi SAR cha mt a ch c dng 4n+2, th chu k bus s b chia nh thnh nhiu chu k truyn d liu. Chi tit tham kho phn 10.5.1, Chia nh chu k bus. CPU khng th truy xut trc tip thanh ghi SAR. 10.2.4 Thanh ghi ch DTC (DAR) Thanh ghi DAR l mt thanh ghi 32-bit n xc nh a ch ch ca d liu c truyn n bi b iu khin truyn d liu DTC Trong ch a ch di (y ), th c 32 bit ca thanh ghi DAR u hp l. Trong ch ngn th ch c 24 bit thp ca DAR l hp l cc bit cn li b b qua. Nu mt hot ng truy xut mt word hay mt longword c thc hin trong khi thanh ghi DAR ang cha mt a ch l, hay mt hot ng truy xut b nh longword m thanh ghi DAR li cha mt a ch 4n+2 th chu k bus s c chia thnh nhiu chu k truyn d liu nh hn. Chi tit, tham kho phn 10.5.1, Chia chu k Bus CPU khng th truy xut trc tip thanh ghi DAR. 10.2.5 Thanh ghi counter A (CRA) Thanh ghi DRA l mt thanh ghi 16-bit n xc nh s ln d liu c truyn bi b iu khin truyn d liu DTC. Trong ch truyn bnh thng th thanh ghi CRA thc hin chc nng nh l b m 16-bit (t 1 n 65 536). N c gim mt n v sau mi hot ng chuyn d liu, v nu bit DTCEn (n t 0 n 15) tng ng vi ngun kch hot (activation source) b xo th sau mt ngt qung c yu cu n CPU khi m thanh ghi m truyn c gi tr l H0000. Gi tr m truyn l 1 nu thanh ghi CRA = H0001, v 65 535 nu CRA = HFFFF, v 65 536 nu CRA = H0000. Trong ch lp th thanh ghi CRA c chia thnh hai phn: 8 bit cao (CRAH) v 8 bit thp (CRAL). CRAH gi s ln cn chuyn trong khi CRAL c chc nng nh mt b m truyn 8-bit (t 1 n 256). CRAL s b gim 1 n v c sau mi ln d liu c truyn, v ni dung ca CRAH s c a vo CRAL khi m CRAL c gi tr l 0. B m truyn l 1 nu CRAH=CRAL=H01, v 255 khi m CRAH=CRAL=HFF, v 256 khi m CRAH=CRAL=H00. Trong ch chuyn theo khi, th CRA c chia thnh 2 phn: 8 bit cao (CRAH) v 8 bit thp (CRAL). CRAH gi kch thc ca khi trong khi CRAL c chc nng nh mt m truyn cho khi d liu c kch thc l 8-bit (1 n 256 byte, word hay longword). CRAL s b gim 1 n v sau mi ln chuyn d liu (chuyn 1 byte, word, hay longword), v ni dung ca CRAH s c chuyn co CRAL khi m gi tr trong CRAL bng 0. Kch thc ca khi l 1 byte (hoc word hay longword) nu CRAH = CRAL = H01, v 255 byte (hoc word hay longword)
327
khi m CRAH = CRAL = HFF, v 256 byte (hoc word hay longword) nu CRAH=CRAL=H00. CPU khng th truy xut trc tip thanh ghi CRA. 10.2.6 Thanh ghi m truyn B (CRB) Thanh ghi CRB l mt thanh ghi 16-bit, xc nh s ln d liu c chuyn bi DTC trong ch truyn khi. N thc hin chc nng nh mt b m truyn 16-bit (t 1 n 65 536), n s gim 1 mi ln d liu c chuyn v cc bit DTCEn (n=15 n 0) tng ng vi ngun kch hot (activation source) s b xo,sau mt ngt qung s c gi n CPU khi m m ny t n gi tr bng H0000. m truyn c gi tr l 1 khi CRB = H0001, v 65 535 khi CRB = HFFFF, v 65 536 khi CRB = H0000. Thanh ghi CRB khng cho php trong ch bnh thng v ch lp v CPU khng th truy xut trc tip thanh ghi ny. 10.2.7 Thanh ghi cho php DTC t A n H (DTCERA n DTCERH) DTCER bao gm 8 thanh ghi 16 bit, DTCERA n DTCERH, n l thanh ghi m xc nh ngun ngt qung ca DTC. S tng ng gia ngun ngt qung v cc bit DTCE c trnh by trong bng 10.1. S dng cc cu lnh thao tc trn bit nh BSET v BCLR c hay ghi vo mt bit DTCE. Nu tt c cc ngt qung u b che, th nhiu ngun kch hot (multiple activation sources) c th c thit lp mt ln (ch vo lc khi ng) bng vic ghi d liu sau khi thc thi mt thc thi mt hot ng c gi trn thanh ghi lin quan.
Bit
Tn bit
Gi tr khi ng 0 0 0 0 0 0 0
R/W
c t
15 14 13 12 11 10 9
DTCE15 DTCE14 DTCE13 DTCE12 DTCE11 DTCE10 DTCE9
R/W Cho php kch hot DTC R/W Vic thit lp cc bit ny xc nh mt ngt qung lin quan ti mt ngun kch hot DTC R/W [iu kin xo] R/W - Khi ghi gi tr 0 vo bit ny sau khi n c R/W c vi gi tr l 1 R/W - Khi m bit DISEL l 1 v 1 vic chuyn d R/W liu hon tt.
328
8 7 6 5 4 3 2 1 0
DTCE8 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0
0 0 0 0 0 0 0 0 0
R/W -
Khi mt s ln truyn xc nh kt thc
R/W Cc bit ny s khng xo c khi m bit DISEL c gi tr l 0 v vic lun chuyn d R/W liu cha kt thc R/W R/W R/W R/W R/W R/W
10.2.8 Thanh ghi iu khin DTC (DTCCR) Thanh ghi DTCCR ch nh hot ng kch hot DTC bi phn mm v b qua vic c thng tin chuyn d liu
Ch : * ch gi tr 0 mi c ghi vo cc bit ny xo c. Bit Tn bit Gi tr khi ng 0 R/W c t
7, --6, 5 4 RRS
Khng dng Cc bit ny lun c gi tr l 0. Ch nn ghi vo cc bit ny gi tr l 0
R/W
Cho php b qua vic c thng tin truyn d liu iu khin vector a ch v vic c thng tin truyn. Ch s vector DTC l lun lun c so snh vi ch s vector kch hot trc . Nu cc ch s vector l trng khp v bit ny bng 1, th hot ng truyn d liu DTC s c bt u m khng cn c mt a ch vector v thng tin truyn. Nu s kch thot DTC trc l mt hot ng truyn chui, th vic c a ch vector v c thng tin truyn l lun lun c thc hin. 0: B qua vic c thng tin truyn khng
329
c cho php. 1: B qua c thng tin truyn c cho php khi m cc ch s vector l trng khp. 3 RCHNE 0 R/W Cho php truyn d liu dy chuyn sau khi truyn d liu lp. Cho php/cm chuyn d liu dy chuyn trong khi bin m truyn (CRAL) l 0 trong ch chuyn d liu lp. Trong ch truyn d liu lp, th gi tr CRAH c chuyn vo CRAL khi m gi tr ca CRAL l 0. Do , m hot ng truyn d liu theo dy chuyn c th khng xy ra khi m CRAL c gi tr l 0. Nu bit ny bng 1, th hot ng truyn d liu dy chuyn c cho php khi CRAH c chuyn vo CRAL. 0: Cm hot ng truyn d liu dy chuyn sau khi truyn d liu lp 1: Cho php ng truyn d liu dy chuyn sau khi truyn d liu lp 2, 1 --0 R Khng dng Cc bit ny lun lun c gi tr l 0 v khng th hiu chnh cc gi tr ca n. 0 ERR 0 R/(W)* C dng chuyn d liu N ch ra rng nu mt li a ch hay mt ngt NMI xy ra th DTC s b dng 0: Khng c ngt 1: C ngt xy ra [iu kin xa] Khi ghi gi tr 0 vo n sau khi c c 1 Ch : * Ch c th ghi gi tr 0 vo bit ny xa c. 10.2.9 Thanh ghi vector nn ca DTC (DTCVBR) Thanh ghi DTCVBR l mt thanh ghi 32-bit, xc nh a ch nn h tr cho vic tnh a ch bng vector. Cc bit 31-28 v cc bit 11 n 0 c c nh l 0 v khng th ghi vo cc bit ny. Gi tr khi to cho DTCVBR l H0000 0000
330
10.3 Cc ngun kch hot

DTC c kch hot bi mt yu cu ngt qung. Ngun ngt qung c la chn bi DTCER. Mt ngun ngt qung c th c chn la bi vic thit lp cc bit tng ng trong DTCER; ngun ngt CPU c th c la chn bng vic xa cc bit tng ng trong DTCER. Khi kt thc mt hot ng chuyn d liu (hay kt thc mt hot ng chuyn lin tc trong trng hp truyn d liu dy chuyn), c ngt ngun kch hot hay cc bit tng ng trong DTCER s b xa.
10.4 V tr ca thng tin truyn ti v bng vector DTC

t thng tin truyn ti trong vng d liu, a ch bt u ca thng tin truyn ti nn c t ti a ch m l bi s ca 4 (4n). Nu khng, 2 bit thp s b b qua trong qu trnh truy xut ([1:0] = B00). Thng tin truyn ti c th c t trong ch a ch ngn (3 longword) hoc trong ch a ch y (4 longword), c ch nh bi bit DTCMD trong thanh ghi SYSCR. Chi tit, tham kho phn 3.2.2, thanh ghi iu khin h thng (SYSCR). Thng tin truyn ti nm trong vng d liu c m t nh hnh 10.2. DTC (b iu khin truyn ti) c a ch bt u ca thng tin truyn ti t bng vector thng qua ngun kch hot, v sau c thng tin truyn ti t a ch bt u. Hnh 10.3 s trnh s tng ng ca a ch bng vector v thng tin truyn ti.
Hnh 10.2 Thng tin truyn ti trong vng d liu
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Hnh 10.3 S tng ng gia a ch bng vector DTC v thng tin truyn ti Bng 10.1 Ngun ngt, a ch vector DTC, v cc DTCE tng ng Ngun kch hot gc Chn ngoi Ngun kch hot Ch s vector a ch offset vector DTC H500 H504 H508 H50C H510 H514 H518 H51C H520 H524 H528 H52C H530 H534 H538 H53C H558 DTCE*1 u tin
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 86
DTCEA15 DTCEA14 DTCEA13 DTCEA12 DTCEA11 DTCEA10 DTCEA9 DTCEA8 DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB15
Cao
A/D_0
ADI0
332
A/D_1 TPU_0
ADI1 TGI0A TGI0B TGI0C TGI0D
87 88 89 90 91 93 94 97 98 101 102 103 104 106 107 110 111 116 117 119 120 122 123 125 126
H55C H560 H564 H568 H56C H574 H578 H584 H588 H594 H598 H59C H5A0 H5A8 H5AC H5B8 H5BC H5D0 H5D4 H5DC H5E0 H5E8 H5EC H5F4 H5F8 H600 H604 H608 H60C H620 H624
DTCEB14 DTCEB13 DTCEB12 DTCEB11 DTCEB10 DTCEB9 DTCEB8 DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC15 DTCEC14 DTCEC13 DTCEC12 DTCEC11 DTCEC10 DTCEC9 DTCEC8 DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCED13 DTCED12
TPU_1 TPU_2 TPU_3
TGI1A TGI1B TGI2A TGI2B TGI3A TGI3B TGI3C TGI3D
TPU_4 TPU_5 TMR_0 TMR_1 TMR_2 TMR_3 DMAC
TGI4A TGI4B TGI5A TGI5B CMIA0 CMIB0 CMIA1 CMIB1 CMIA2 CMIB2 CMIA3 CMIB3
DMTEND0 128 DMTEND1 129 DMTEND2 130 DMTEND3 131 DMEEND0 136 DMEEND1 137
333
DMEEND2 138 DMEEND3 139 SCI_3 SCI_4 TPU_6 RXI3 TXI3 RXI4 TXI4 TGI6A TGI6B TGI6C TGI6D TPU_7 TPU_8 TPU_9 TGI7A TGI7B TGI8A TGI8B TGI9A TGI9B TGI9C TGI9D TPU_10 TGI10A TGI10B Khng dng Khng dng TCI10V*2 TPU_11 TGI11A hoc khng dng TGI11B hoc khng dng SCI_5 Ch : RXI5 TXI5 157 158 161 162 164 165 166 167 169 170 173 174 177 178 179 180 182 183 184 185 186 188
H628 H62C H674 H678 H684 H688 H690 H694 H698 H69C H6A4 H6A8 H6B4 H6B8 H6C4 H6C8 H6CC H6D0 H6D8 H6DC H6E0 H6E4 H6E8 H6F0
DTCED11 DTCED10 DTCEE15 DTCEE14 DTCEE13 DTCEE12 DTCEE11 DTCEE10 DTCEE9 DTCEE8 DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEE3 DTCEE2 DTCEE1 DTCEE0 DTCEF15 DTCEF14 DTCEF13 DTCEF12 DTCEF11 DTCEF10
189
H6F4
DTCEF9
193 194
H704 H708
DTCEF7 DTCEF6 Thp
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1. Cc bit DTCE khng c cc ngt qung tng ng c xem nh l Khng dng (khng dng), v cc gi tr ghi vo cc bit ny lun nn l 0. ri khi ch standby phn mm hay ch all-module-clock-stop vi mt ngt qung, th ghi gi tr 0 vo bit DTCE tng ng. 2. TCI10V khng kch hot DTC
10.5 Hot ng
B iu khin truyn ti lu thng tin truyn ti trong vng d liu. Khi c kch hot, DTC s c thng tin truyn ti c lu trong vng d liu v truyn d liu i da trn thng tin truyn . Sau mi ln truyn d liu, b iu khin s t ng cp nht li thng tin truyn ti vo vng d liu. V thng tin truyn ti lun vng d liu, nn n c th truyn d liu trn bt k bao nhiu knh, C 3 ch truyn: Bnh thng (normal), lp (repeat) v khi (block). B iu khin DTC ch nh a ch ngun v a ch ch ln lt trong thanh ghi SAR v DAR. Sau mi ln truyn d liu, th cc thanh ghi SAR v DAR c tng, gim, hay c nh (khng thay i) Bng 10.2 Cc ch truyn ca DTC Ch truyn Bnh thng (Normal) Lp (Repeat)*1 Khi (Block)*2 Kch thc d liu truyn mi ln truyn byte/word/longword byte/word/longword Kch thc khi c ch nh bi thang ghi CRAH (1 n 256 byte/ word/ longword) a ch b nh c tng hay gim Tng/gim 1, 2 hay 4 hoc khng thay i Tng/gim 1, 2 hay 4 hoc khng thay i Tng/gim 1, 2 hay 4 hoc khng thay i m truyn
1 n 65536 1 n 256*3 1 n 65536
Ch : 1. Hoc l ngun hoc l ch uc ch nh l vng lp. 2. Hoc l ngun hoc l ch uc ch nh l vng khi. 3. Sau hot ng truyn ca b m truyn, th trng thi ban u c phc hi tip tc hot ng. Thit lp bit CHNE trong thanh ghi MRB ln 1 c th truyn nhiu ln truyn ti ch vi mt hot ng kch hot n (truyn d liu dy chuyn). Vic thit lp bit CHNS trong thanh ghi MRB ln 1 cng c th lm thc hin hot ng truyn dy chuyn ch khi bin m truyn c gi tr l 0. Hnh 10.4 cho thy lu hot ng DTC, v bng 10.3 tng kt cc iu kin ca chui truyn ti
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Hnh 10.4 Lu ca hot ng DTC Bng 10.3 Cc iu kin ca truyn ti chui B chuyn th nht B chuyn th hai CHNE CHNS DISEL m CHNE CHNS DISEL m Truyn truyn*1 truyn*1 DTC 0 --0 Not 0 --------Kt thc ln truyn u tin Kt thc
---
0*2
---
---
---
---
336
---
---
---
---
---
ln truyn u tin Yu cu ngt qung n CPU
---
---
---
Not 0
Kt thc ln truyn th 2 Kt thc ln truyn th 2 Yu cu ngt qung n CPU
0 0
-----
0 1
0*2 ---
Not 0
---
---
---
Kt thc ln truyn u tin Kt thc ln truyn th 2 Kt thc ln truyn th 2 Yu cu ngt qung n CPU
---
0*2
---
Not 0
0 0
-----
0 1
0*2
Not 0
---
---
---
---
Kt thc ln truyn
337
u tin Yu cu ngt qung n CPU Ch : 1. CRA trong ch truyn d liu bnh thng, CRAL trong ch truyn d liu lp, hoc CRB trong ch truyn khi 2. Khi m ni dung ca thanh ghi CRAH c ghi vo CRAL trong ch lp. 10.5.1 Chia chu k bus Khi gi tr thit lp trong thanh ghi SAR v DAR ng iu kin bin ca kch thc d liu th chu k bus s b chia nh ra. Bng 10.4 s trnh by mi quan h gia SAR, DAR, kch thc d liu truyn, chia chu k bus, v kch thc d liu truy xut. Hnh 10.5 s trnh by v d v chia chu k bus. Bng 10.4 S chia nh s chu k bus v kch thc truy xut Gi tr trong SAR v DAR a ch l 4n a ch l 2n + 1 a ch l 4n + 2 Kch thc d liu Byte (B) 1 (B) 1 (B) 1 (B) Word (W) 1 (W) 2 (B-B) 1 (W) LongWord (LW) 1 (LW) 3 (B-W-B) 2 (W-W)
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Hnh 10.5 V d v chu k bus 10.5.2 Chc nng b qua vic c thng tin truyn Bng vic thit lp bit PRS ca thanh ghi DTCCR, hot ng c vector a ch v c thng tin truyn ti c th c b qua, ch s vector hin ti ca DTC lun lun c so snh vi ch s vector ca hot ng trc . Nu cc ch s ny trng khp khi bit RRS bng 1, th mt hot ng truyn d liu s c thc hin m khng cn c a ch vector v thng tin truyn ti. Nu hot ng trc l mt chui truyn, th hot ng c a ch vector v c thng tin truyn ti phi lun c thc hin. Hnh 10.6 trnh by gin thi gian v hot ng b qua vic c thng tin truyn ti. chnh sa bng vector v thng tin truyn ti, xa tm thi bit RRS, chnh sa bng vector v thng tin truyn ti, v sau thit lp bit RRS ln 1 tr li. Khi m bit RRS b xa, th ch s vector c lu tr trc s b xa, v gi tr cp nht v thng tin truyn ti s c c hot ng k tip
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Hnh 10.6 Gin thi gian hot ng b c thng tin truyn 10.5.3 Chc nng b qua vic ghi tr li thng tin truyn Bng cch ch nh bit SM1 trong thanh ghi MRA v bit DM1 trong thanh ghi MRB cho ch a ch c nh, mt phn ca thng tin truyn ti s khng c ghi li (writeback). Chc nng ny c thc thi bt chp ch a ch l ngn hay . Bng 10.5 trnh by iu kin b qua vic ghi li thng tin truyn v cc thanh ghi c b qua vic ghi li ny. Ch rng thanh ghi CRA v CRB l lun lun c ghi li cho d ch a ch l ngn hay . Trong ch a di () th vic ghi li (writeback) vo cc thanh ghi MRA v MRB lun lun c b qua. Bng 10.5 iu kin b qua vic ghi li thng tin truyn v cc thanh ghi b b qua vic ghi li thng tin truyn. SM1 0 0 1 1 0 1 0 1 DM1 SAR B qua B qua Ghi li Ghi li Ghi li B qua Ghi li DAR B qua
10.5.4 Ch truyn bnh thng Trong ch bnh thng, mt ln truyn 1 byte, 1 word, hay 1 longword d liu. T 1 n 65536 ln truyn c th c ch nh. a ch ngun v ch c th c ch nh l tng, gim hay c nh. Khi m s ln truyn c ch nh kt thc, th mt ngt qung s c pht sinh cho CPU. Bng 10.6 Danh sch chc nng thanh ghi trong ch truyn bnh thng. Thanh ghi SAR DAR CRA Chc nng a ch ngun a ch ch m truyn A Gi tr writeback Tng/gim/c nh Tng/gim/c nh CRA - 1
340
CRB
m truyn B
Khng cp nht
Hnh 10.7 trnh by bn a ch trong ch truyn bnh thng.
Hnh 10.7 Bn a ch trong ch truyn bnh thng. 10.5.5 Ch truyn lp Trong ch truyn lp, mt ln truyn 1 byte, 1 word, hay 1 longword ca d liu. a ch ngun hoc a ch ch c th c ch nh nh l mt vng lp bi bit DTS trong thanh ghi MRB. T 1 n 256 ln truyn c th c ch nh. Khi m s ln truyn c ch nh kt thc, thanh ghi m truyn (transfer counter) v thanh ghi a ch c ch nh vi vai tr l vng lp c phc hi li trng thi ban u, v hot ng truyn c lp li. Thanh ghi a ch khc sau c tng, gim hoc c nh. Trong ch truyn lp, m truyn (CRAL) c cp nht gi tr c ch nh trong thanh ghi CRAH khi CRAL c gi tr l H00. Chnh v vy m m truyn khng c gi tr l 0, v do khng c ngt qung cho CPU khi bit DISEL = 0. Bng 10.7 Lit k chc nng thanh ghi trong ch truyn lp. Gi tr ghi vo Thanh ghi SAR Chc nng a ch ngun CRAL khng phi l 1 Tng/gim/c nh* CRAL l 1 DTS = 0: Tng/gim/c nh* DTS = 1: Gi tr khi ng SAR DAR a ch ch Tng/gim/c nh* DTS = 0: Gi tr khi ng DAR DTS = 1: Tng/gim/c nh* CRAH Lu m truyn CRAH CRAH
341
CRAL CRB
m truyn A m truyn B
CRAL 1 Khng cp nht
CRAH Khng cp nht
Ch : * Thng tin truyn ghi li c b qua Hnh 10.8 Trnh by bn b nh trong ch truyn lp
Hnh 10.8 B nh trong ch truyn lp (khi ngun c ch nh l vng lp) 10.5.6 Ch truyn khi Trong ch truyn khi, mt ln truyn mt khi (block) d liu. Hoc l a ch ngun hoc l a ch ch l c ch nh l vng khi bi bit DTS trong thanh ghi MRB. Kch thc khi t 1 n 256 byte (1 n 256 word, hay longword). Khi truyn xong 1 khi d liu, th thanh ghi m kch thc khi (CRAL) v thanh ghi a ch (SAR khi bit DTS = 1 hay DRA khi DTS = 0) m c ch nh l vng khi c s c phc hi li trng thi ban u. Thanh khi a ch khc sau s c tng, gim hay khng i. T 1 n 65536 ln truyn c th c thit lp. Khi s ln truyn c ch nh kt thc, mt ngt qung s c pht sinh cho CPU. Bng 10.8 Lit k chc nng thanh ghi trong ch truyn khi. Thanh ghi SAR DAR CRAH CRAL CRB Chc nng a ch ngun a ch ch Lu tr kch thc m kch thc khi m truyn khi Gi tr ghi vo DTS = 0: Tng/gim/c nh* DTS = 1: Gi tr khi ng SAR DTS = 0: Gi tr khi ng DAR DTS = 1: Tng/gim/c nh* CRAH CRAH CRB - 1
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Ch : * Thng tin truyn ghi li c skip Hnh 10.9 Trnh by bn b nh trong ch truyn khi
Hnh 10.9 Bn b nh trong ch truyn khi 10.5.7 Truyn d liu dy chuyn (chain) Vic thit lp bit CHNE trong thanh ghi MRB ln 1 cho php mt s hot ng truyn c thc hin mt cch lin tip nh mt ln truyn duy nht. Vic thit lp cc bit CHNE v CHNS trong thanh ghi MRB ln 1 cho php truyn d liu dy chuyn ch khi m truyn t ti gi tr 0. Cc thanh ghi SAR, DAR, CRA, CRB, MRA v MRB (dng xc nh d liu truyn) c th c thit lp mt cch c lp. Hnh 10.10 trnh by hot ng truyn chui Trong trng hp hot ng truyn vi bit CHNE bng 1, s khng c ngt qung c yu cu cho CPU khi kt thc truyn hay vicsetbit DISEL ln 1, v c ngun ngt cho ngun kch hot v DTCER khng b nh hng. Trong ch truyn lp, vic set cc bit RCHNE trong thanh ghi DTCCR v cc bit CHNE v CHNS trong thanh ghi MRB ln 1 s cho php hot ng truyn d liu dy chuyn sau mt hot ng truyn m m truyn bng 1 (transfer counter =1) hon tt.
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Hnh 10.10 Hot ng ca truyn chui 10.5.8 iu chnh thi gian cc hot ng (Operation Timing) Hnh 10.11 n 10.14 trnh by vic iu chnh thi gian cc hot ng ca DTC
Hnh 10.11 iu chnh hot ng ca DTC (V d v ch a ch ngn trong ch truyn bnh thng hay trong ch truyn lp)
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Hnh 10.12 iu chnh hot ng ca DTC (V d v ch a ch ngn trong ch truyn khi vi kch thc khi ca 2)
Hnh 10.13 iu chnh hot ng ca DTC (V d v ch a ch ngn trong truyn chui)
Hnh 10.14 iu chnh hot ng DTC (v d v ch a ch di trong ch truyn bnh thng hay ch truyn lp) 10.5.9 S chu k thc thi DTC Bng 10.9 trnh by cc trng thi thc thi cho mt hot ng truyn d liu DTC n gin, v bng 10.10 trnh by s yu cu chu k cho mi s thc thi. Bng 10.9 Cc trng thi thc thi ca DTC
345
c Vector
c thng tin truyn
Ghi thng tin truyn
c d liu
Ghi d liu
Hot ng bn trong N
Ch Bnh thng Lp Truyn khi
I 1 1 1 0*
1
J 4*
2
L 3*
3
L
23
0*
1
3*
2*
1*
3*
3
0*
1
4*
2
3*
3
0*
1
3*23 3*23
2*4 1*
5
0*
1
4*
2
3*
3
0*
1
2*4 1*
5
Ghi ch: P: Kch thc khi (gi tr ca CRAH v CRAL) Ch : 1. Khi vic c thng tin truyn ti b b qua. 2. Trong ch hot ng a ch y . 3. Trong ch hot ng a ch ngn. 4. Khi thanh ghi SAR hoc DAR trong ch c nh. 5. Khi thanh ghi SAR v DAR trong ch c nh. 6. Khi mt longword c truyn i trong khi mt a ch l c ch nh trong thanh ghi a ch. 7. Khi mt word c truyn i trong khi mt a ch l c ch nh trong thanh ghi a ch hay mt longword c truyn i trong khi mt a ch 4n+2 c ch nh trong thanh ghi a ch. P: Kch thc khi (khi ng gi tr ban u ca CRAH v CRAL) Bng 10.10 S chu k cn thit cho mi trng thi thc thi. i tng RAM trn chip 32 1 1 1 RO Thanh ghi M xut/nhp trn trn chip chip 32 1 1 1 8 16 2 _ _ 2 _ _ 32 2 _ _ 2 8 8 Thit b bn ngoi
rng bus Chu k truy xut Trng c vector thi SI thc c thng
8 3 12+4 m 12+4 2
16 3 2 4 6+2m 2 4 6+2m 2
32 3 3+ m 3+
346
thi
tin truyn SJ Ghi thng tin truyn SJ c d liu byte SL c d liu word SL c d liu longword SL Ghi d liu byte SM Ghi d liu word SM Ghi d liu longword SM Hot ng trong SN 1 1 _ _ _ 8
m 12+4 m 3+m 4+2 m 12+4 m 3+m 4+2 m 12+4 m 4 6+2m 2
m 3+ m 3+ m 3+ m 3+ m 3+ m 3+ m 3+ m
1 1 1
1 1 1
2 4 8
2 2 4
2 2 2
2 4 8
2 2
3+m 3+m
2 2
4 6+2m 2
1 1 1
1 1 1
2 4 8
2 2 4
2 2 2
2 4 8
2 2
3+m 3+m
2 2
4 6+2m 2
Ghi ch: m: S chu k i (t 0 n 7, chi tit tham kho phn 6, B iu khin Bus BSC). S chu k thc thi c tnh t cng thc bn di. Ch rng S c ngha l tng s ca tt c cc hot ng truyn c kch hot bi mt s kin (s hot ng cho ti khi bit CHNE c set ln 1, cng 1) S chu k thc thi = I SI + (J SJ + K SK + L SL + M SM) + N SN 10.5.10 iu chnh gii phng bus ca b DTC Khi c 1 yu cu kch hot xy ra th b DTC s gi yu cu s dng bus n b qun l bus (bus arbiter, ngi phn gii). B DTC s gii phng bus sau mt hot ng c vector, c thng tin, mt hot ng truyn n, hay mt hot ng ghi li thng tin truyn. B DTC s khng gii phng bus trong sut qu trnh c thng tin truyn, trong qu trnh truyn 1 n v d liu, hay trong qu trnh ghi li thng tin truyn. 10.5.11 iu khin mc u tin ca b DTC cho CPU Mc u tin ca cc ngun kch hot DTC so vi CPU c th c iu khin bi mc u tin ca CPU c ch nh bi cc bi CPUP2 n CPUP0 trong thanh ghi CPUPCR v mc u tin ca DTC c ch nh bi cc bit DTCP0 n DTCP2. Chi tit tham kho, phn 5, b iu khin bus.
347
10.6 Quy trnh s dng DTC

10.6.1 Kch hot bi ngt qung Tin trnh s dng DTC vi ngun kch hot l ngt qung c trnh by bn di.
1. Thit lp bit RRS trong thanh ghi DTCCR reset c cho hot ng b c thng tin truyn. Sau hot ng ny, hot ng b c thng tin truyn s khng c thc thi trong hot ng ca DTC. Khi thng tin truyn c cp nht, ta nn thit lp bit ny. 2. t thng tin truyn (MRA, MRB, SAR, DAR, CRA v CRB) trong vng d liu. Vic thit lp thng tin truyn, tham kho phn 10.2 c t thanh ghi. Vic cp pht cc thanh ghi tham kho phn 10.4 cp pht thng tin truyn v bng vector DTC. 3. Thit lp a ch bt u ca thng tin truyn cho bng vector DTC. V tin trnh thit lp thng tin truyn cho bng a ch vector DTC, tham kho phn 10.4 Cp pht thng tin truyn v bng vector DTC.
348
4. Bng cch thit lp bit RRS trong thanh ghi DTCCR, ln th 2 v cc ln c thng tin truyn tip sau c th b skip (b qua) khi m vic kch hot DTC mt cch lin tc bi cc ngt qung nh nhau. Vic ghi 1 vo bit RRS lun lun c cho php. Ch rng nu vic ghi c thc hin trong sut qu trnh truyn DTC, th vic thit lp bit RRS s l c tc dng cho ln truyn k tip 5. Thit lp bit trong thanh ghi DTCER, l thanh ghi c lin quan n mt ngt qung kch hot cho DTC. Xem bng 10.1 tham kho cc ngun ngt v cc bit DTCE. Trong cc ln truyn th 2 v cc ln sau, bit tng ng trong DTCER c th c set ln 1. Vic thit lp li cc bit tng ng ny l khng cn thit. 6. Thit lp bit cho php mt ngun ngt qung kch hot DTC. Khi mt ngt qung l ngun ngt c pht sinh th DTC s c kch hot. thit lp bit cho php cho cc ngun ngt, tham kho tin trnh thit lp cc module ngun cho ngun kch hot. 7. Sau khi d liu c truyn i 1 ln, th DTC s xa c ngun ngt v cc bit tng ng trong thanh ghi DTCER, v pht sinh mt ngt qung cho CPU. Hot ng truyn sau khi truyn c quyt nh thng qua vic thit lp thng tin truyn. Chi tit tham kho phn 10.2, c t thanh ghi v hnh 10.4.
10.7 V d s dng DTC

10.7.1 Ch truyn bnh thng Mt v d c trnh by, trong DTC c s dng nhn 128 byte d liu thng qua SCI. 1. Thit lp MRA c nh a ch ngun (SM1 = SM0 = 0), tng a ch ch (DM1 = 1, DM0 = 0), ch truyn bnh thng (MD1 = MD0 = 0), v kch thc byte (Sz1 = Sz0 = 0). Bit DTS c th cha bt k gi tr no. Thit lp MRB cho mt ln truyn d liu bi mt ngt qung (CHNE = 0, DISEL = 0). Thit lp a ch RDR ca SCI trong thanh ghi SAR, a ch bt u ca vng RAM ni m d liu s c nhn trong thanh ghi DAR, v thit lp gi tr 128 (H0080) trong thanh ghi CRA. Thanh ghi CRB c th cha mt gi tr no bt k. 2. Thit lp a ch bt u ca thng tin truyn ngt qung RXI l ngun kch hot theo bng vector a ch ca DTC. 3. Set cc bit tng ng trong DTCER ln 1. 4. Thit lp SCI ln ch nhn thch hp. Set bit RIE trong SCR ln 1 cho php ngt qung kt thc nhn RXI. V vic pht sinh li trong sut qu trnh nhn d liu SCI s cm vic nhn nhng ln tip theo, nn CPU s c cho php d chp nhn cc ngt qung li nhn. 5. Mi khi nhn c 1 byte d liu kt thc trn SCI, th c RDRF trong SSR c set ln 1, mt ngt qung RXI c pht sinh, v DTC c kch hot. D liu nhn c truyn t RDR n RAM thng qua DTC. DAR c tng v DRA c gim xung. C RDRF t ng c xa.
349
6. Khi CRA tr thnh 0 sau khi truyn 128 ln truyn d liu, c RDRF c gi mc 1, bit DTCE c xa, v mt ngt qung RXI c gi n CPU. Hm p ng ngt qung s kt thc qu trnh. 10.7.2 Truyn chui Mt v d ca truyn chui DTC, trong xung xut c thc hin s dng PPG. Truyn chui c th c s dng truyn d liu xut xung v cp nht chu k trigger xut PPG. Ch lp truyn vo NDR ca PPG c thc thi trong na u ca chui truyn, v ch bnh thng truyn vo TGR ca TPU na cn li. iu ny bi v vic xa ngun kch hot v pht sinh ngt qung khi kt thc mt s ln truyn nht nh l b hn ch cho phn th 2 (na cn li) ca chui truyn (truyn khi CHNE = 0). 1. Thc hin vic thit lp cho NDR ca PPG. Thit lp MRA tng a ch ngun (SM1 = 1, SM0 = 0), c nh a ch ngun (DM1 = DM0 = 0), ch lp (MD1 = 0, MD0 = 1), v kch thc word (Sz1 = 0, Sz0 = 1). Thit lp ngun l mt vng lp (DTS = 1). Thit lp MRB ch truyn chui (CHNE = 1, CHNS = 0, DISEL = 0). Thit lp a ch bt u bng d liu trong SAR, a ch NDRH trong thanh ghi DAR, v kch thc bng d liu trong CRAH v CRAL. CRB c th thit lp mt gi tr bt k. 2. Thc hin vic thit lp cho hot ng truyn cho TGR ca TPU. Thit lp MRA gim a ch ngun (SM1 = 1, SM0 = 0), c nh a ch ch (DM1 = DM 0 = 0), ch bnh thng (MD1 = MD0 = 0), v kch thc word (Sz1 = 0, Sz0 = 1). Thit lp a ch bt u bng d liu trong thanh ghi SAR, a ch TGRA trong DAR, v kch thc bng d liu trong thanh ghi CRA. CRB c th thit lp 1 gi tr bt k. 3. Cp pht thng tin truyn TPU mt cch lin tip sau thng tin truyn NDR. 4. Thit lp a ch bt u ca thng tin truyn NDR cho a ch vector ca DTC 5. Set bit tng ng cho ngt TGIA trong thanh ghi DTCER ln 1 6. Thit lp TGRA l thanh ghi output compare vi TIOR, v cho php ngt qung TGIA vi TIER. 7. Thit lp gi tr xut ban u trong PODR, v gi tr xut tip theo trong NDR. Thit lp cc bit trong DDR v NDER m tn hiu xut l 1. S dng PCR, la chn compare match ca TPU l output trigger. 8. Thit lp bit CST trong TSTR ln 1, v bt u hot ng m TCNT. 9. Mi khi c s compare match thanh ghi TGRA xy ra, th gi tr xut tip theo s c truyn vo NDR v gi tr thit lp ca k output trigger tip theo c chuyn vo thanh ghi TGRA. C ngun kch hot TGFA c xa. 10. Khi hot ng truyn hon tt (gi tr CRA l 0), c TGFA c gi mc 1, bit DTCE c xa, v mt yu cu ngt qung TGIA c gi cho CPU. V vic kt thc tin trnh s c thc thi trong hm p ng ngt qung. 10.7.3 Truyn chui khi Counter = 0
350
Bng vic thc thi truyn d liu ln th 2 v thc hin vic thit lp li vic truyn d liu ln u ch khi gi tr counter l 0, ta c th thc hin 256 ln truyn lp hoc nhiu hn. Mt v d c trnh by di y l c cu hnh buffer nhp l 128 Kbyte. Buffer nhp l c thit lp ban u vi a ch thp H0000. Hnh 10.16 trnh by hot ng truyn chui khi m counter c gi tr l 0. 1. Vi ln truyn u tin, thit lp ch truyn bnh thng cho d liu nhp. Thit lp a ch ngun c nh (v d G/A), CRA = H0000 (64K ln), CHNE = 1, CHNS = 1, v DISEL = 0. 2. Chun b 8-bit a ch cao ca a ch bt u cho hot ng truyn khi 64K ln truyn d liu u tin trong vng ring bit (v d ROM). V d, nu buffer nhp c cu hnh ti a ch H20 0000 n H21 FFFF, chun b H21 v H20. 3. Vi ln truyn th 2, thit lp ch truyn lp (vi vng ngun l vng lp) thit lp li a ch ch truyn cho ln truyn u tin. S dng 8 bit cao ca DAR trong vng thng tin d liu truyn u tin. S dng 8 bit cao ca DAR trong vng thng tin truyn u tin nh l ch truyn. Thit lp CHNE = DISEL =0. Nu buffer nhp trn c ch nh l H20 0000 n H21 FFFF, thit lp m truyn l 2. 4. Thc thi nhng ln truyn ca 64k u tin thng qua cc ngt qung. Khi m truyn cho ln truyn d liu u tin t n 0, ln truyn d liu th 2 s c bt u. Thit lp 8 bit cao ca a ch ngun cho ln truyn u tin l H21. 16 bit thp ca a ch ch ca ln truyn u tin v m truyn c thit lp l H0000. 5. Tip theo, thc thi nhng ln truyn ca 64K u tin bi cc ngt qung. Khi m truyn cho ln truyn d liu u tin t n 0, th ln truyn th 2 s c bt u. Thit lp 8-bit cao ca a ch ngun cho ln truyn u l H20. 16 bit thp ca a ch ch ca ln truyn u tin v m truyn c thit lp l H0000 6. Cc bc 4 v 5 c lp li v tn. Khi ch lp c ch nh cho ln truyn th 2, th khng c yu cu ngt qung no c gi cho CPU.
Hnh 10.16 Truyn chui khi Counter = 0
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10.8 Ngun ngt

Mt yu cu ngt qung c gi n cho CPU khi DTC hon tt mt s ln truyn nht nh hay ch mt ln truyn n v (truyn mt n v d liu) m set bit DISEL ln 1. Trong trng hp ngun kch hot ngt qung, th ngt qung c thit lp l ngun ngt c pht ra. Nhng ngt qung n CPU l ph thuc vo cp mask ca CPU v mc u tin trong b iu khin ngt qung.
10.9 Ch s dng
10.9.1 Thit lp ch dng module Hot ng ca DTC c th b cm hay cho php s dng thanh ghi iu khin dng module. Vic thit lp gi tr ban u l cho hot ng ca DTC m c cho php. Truy xut thanh ghi b cm bi vic thit lp ch dng module. Ch dng module khng th c thit lp trong khi DTC c kch hot. Chi tit, tham kho phn 19, Ch Power-Down. 10.9.2 RAM trn chip Thng tin truyn c th c cp pht trong vng RAM trn chip. Trong trng hp ny th bit RAME trong thanh ghi SYSCR khng c xa. 10.9.3 Ngt qung kt thc truyn DMAC Khi DTC c kch hot bi ngt qung kt thc truyn DMAC, gi tr trong bit DTE trong thanh ghi DMDR c u tin hn iu khin DTC bt chp m truyn hay gi tr bit DISEL. V vy m mt ngt qung n CPU c th khng c pht sinh, ngay c khi m truyn ca DTC t ti 0. 10.9.4 Thit lp bit DTCE thit lp bit DTCE, s dng cc cu lnh thao tc trn bit v d nh BSET v BCLR. Nu tt c cc ngt qung u b cm, th nhiu ngun kch hot c th c thit lp cng mt lc(ch thit lp 1 ln lc khi ng) bng vic ghi d liu sau khi thc thi mt hot ng c gi (dummy read) trn thanh ghi lin quan 10.9.5 Truyn d liu dy chuyn Khi hot ng truyn d liu dy chuyn c s dng, vic xa ngun ngt hay DTCER c thc hin vo ln truyn d liu cui cng. Mt khc, cc ngun ngt/kch hot ca SCI v b chuyn i A/D tc cao u c xa khi DTC c hay ghi vo cc thanh ghi lin quan. V vy, khi DTC c kch hot bi mt ngt qung hay mt ngun kch hot, nu mt hot ng c/ghi ca cc thanh ghi lin quan khng c trong ln truyn d liu chui cui cng, th ngt qung hay ngun kch hot s vn c. 10.9.6 a ch bt u, ngun v ch ca thng tin truyn a ch bt u ca thng tin truyn c ch nh trong bng vector nn c a ch c dng l 4n. Nu mt a ch khc a ch 4n c ch nh, th 2 bit thp ca a ch s c xem nh l cc bit 0. a ch ngun v ch ca thng thin truyn
352
c ch nh trong thanh ghi SAR v DAR, s c truyn, trong mt vi chu k bus ty thuc vo a ch v kch thc d liu 10.9.7 Endian DTC h tr c nh dng big-endian v little-endian. nh dng endian ca thng tin truyn phi ging nhau khi thng tin c ghi vo v khi thng tin c c ra bi DTC.
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Chng 11 B pht sinh xung clock kh lp trnh (PPG)

B pht sinh xung clock (PPG) cung cp xung nhp xut bng cch s dng b m xung 16-bit (TPU) vi vai tr lm chun thi gian. Tn hiu xut ca PPG c chia thnh cc nhm 4-bit (cc nhm 3 v 2) m c th pht sinh c ng thi v c lp. Hnh 11.1 trnh by s khi ca PPG.
11.1 Cc tnh cht

D liu xut 8-bit 2 nhm xut C th la chn tn hiu trigger xut Ch Non-overlapping C th hot ng vi b iu khin truyn d liu (DTC) v b iu khin DMA (DMAC) C th thit lp o ng xut C th thit lp ch dng module.
Hnh 11.1 S khi ca PPG
11.2 Cc chn xut/nhp

Bng 11.1 Cu hnh chn Tn chn Xut/nhp Chc nng
354
PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8
Xut Xut Xut Xut Xut Xut Xut Xut
Xung xut nhm 3
Xung xut nhm 2
11.3 Cc c t thanh ghi

PPG c cc thanh ghi sau: Thanh ghi cho php d liu k tip H (NDERH) Thanh ghi cho php d liu k tip L (NDERL) Thanh ghi d liu xut H (PODRH) Thanh ghi d liu xut L (PODRL) Thanh ghi d liu k tip H (NDRH) Thanh ghi d liu k tip L (NDRL) Thanh ghi iu khin xut PPG (PCR) Thanh ghi ch xut PPG (PMR) 11.3.1 Cc thanh ghi cho php d liu k tip H, L (NDERH, NDERL) Thanh ghi NDERH v NDERL cho php/cm xung xut theo tng bit. NDERH
NDERL
NDERH Bit Tn bit Gi tr khi ng R/W c t
355
7 6 5 4 3 2 1 0 Bit
NDER15 0 NDER14 0 NDER13 0 NDER12 0 NDER11 0 NDER10 0 NDER9 NDER8 Tn bit 0 0 Gi tr khi ng 0 0 0 0 0 0 0 0
R/W Cc bit cho php d liu k tip (15 n R/W 8). Khi mt bit bng 1, th gi tr bit tng ng trong thanh ghi NDRH s c truyn R/W n bit PODRH bi trigger xut c la R/W chn. Ngc li (bit NDRH bng 0) th d liu s khng c truyn. R/W R/W R/W R/W R/W c t
NDERL
7 6 5 4 3 2 1 0
NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0
R/W Cc bit cho php d liu k tip (7 n 0). R/W Khi mt bit trong thanh ghi ny bng 1, bit tng ng vi n trong thanh ghi R/W NDRL s c truyn sang bit trong thanh R/W ghi PODRL bi mt trigger c chn. R/W Cc bit s khng c truyn nu cc bit trong thanh ghi ny b xa. R/W R/W R/W
11.3.2 Cc thanh ghi d liu xut H, L (PODRH, PODRL) Thanh ghi PODRH v PODRL lu tr d liu xut dng trong tn hiu xut. Mt bit c thit lp l xung xut bi NDER ch c php c v khng th hiu chnh gi tr. PODRH
PODRL
PODRH
356
Bit
Tn bit POD15 0 POD14 0 POD13 0 POD12 0 POD11 0 POD10 0 POD9 POD8 Tn bit POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 0 0 0 0 0 0 0 0 0 0
Gi tr khi ng
R/W
c t
7 6 5 4 3 2 1 0 Bit
R/W Cc bit d liu xut (15 8) R/W Vi cc bit m c thit lp l xung xut bi thanh ghi NDERH, gi tr trong R/W NDRH s c truyn sang thanh ghi R/W ny trong qu trnh hot ng PPG. Khi R/W NDERH c set ln 1, CPU khng th ghi vo thanh ghi ny. Khi thanh ghi R/W NDERH b xa, th gi tr khi ng ca R/W xung s c thit lp. R/W Gi tr khi ng R/W c t
PODRL
7 6 5 4 3 2 1 0
R/W Cc bit d liu xut (7 0) R/W Vi cc bit m c thit lp l xung xut bi thanh ghi NDERL, gi tr trong R/W NDRL s c truyn sang thanh ghi ny R/W trong qu trnh hot ng PPG. Khi R/W NDERL c set ln 1, CPU khng th ghi vo thanh ghi ny. Khi thanh ghi R/W NDERL b xa, th gi tr khi ng ca R/W xung s c thit lp. R/W
11.3.3 Cc thanh ghi d liu k tip H, L (NDRH, NDRL) Thanh ghi NDRH v NDRL lu tr d liu k tip cho tn hiu xut. a ch ca NDR khc nhau ph thuc vo nhm tn hiu xut c cng trigger xut hay c cc trigger xut khc nhau. NDRH
NDRL
357
NDRH Nu cc nhm xung xut 2 v 3 c cng trigger xut, th c 8 bit s c nh x vo cng mt a ch v c th c truy xut cng mt lc, nh di y. Bit 7 6 5 4 3 2 1 0 Tn bit NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Gi tr R/W khi ng 0 0 0 0 0 0 0 0 c t
R/W Cc bit d liu k tip (15 8) R/W Ni dung ca cc thanh ghi s c truyn vo cc bit tng ng trong R/W PODRH bi cc tn hiu trigger R/W c ch nh bi PCR. R/W R/W R/W R/W
Nu cc nhm tn hiu xut 2 v 3 c tn hiu trigger xut l khc nhau, th 4 bit cao v 4 bit thp ca cc bit s c nh x vo cc a ch khc nhau nh di y Bit Tn bit Gi tr khi ng 0 0 0 0 1 R/W c t
7 6 5 4 3-0
NDR15 NDR14 NDR13 NDR12 ---
R/W Cc bit d liu k tip (15 12) R/W Cc ni dung thanh ghi s c truyn vo cc bit tng ng trong R/W thanh ghi PODRH bi tn hiu R/W trigger c ch nh bi PCR. R Khng dng. y l nhng bit ch c v khng th thay i gi tr ca n.
Bit 7-4
Tn bit ---
Gi tr R/W khi ng 1 R Khng dng
c t
y l nhng bit ch c v khng th hiu chnh gi tr ca n.
358
3 2 1 0
NDR11 NDR10 NDR9 NDR8
0 0 0 0
R/W Cc bit d liu tip theo (11 8) R/W Cc ni dung ca thanh ghi c truyn vo cc bit tng ng trong R/W thanh ghi PODRH bi tn hiu R/W trigger xut c ch nh
NDRL Nu tn hiu xut thuc nhm 0 v 1 c cng tn hiu trigger xut, tt c 8 bit s c nh x vo cng mt a ch v khi c th truy xut, nh v d di y. Bit 7 6 5 4 3 2 1 0 Tn bit NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Gi tr R/W khi ng 0 0 0 0 0 0 0 0 R/W c t
R/W Cc bit d liu k tip (7-0) Ni dung ca cc bit ny s c truyn vo cc bit tng ng trong R/W thanh ghi PODRL bi trigger xut R/W c ch nh vi PCR. R/W R/W R/W R/W
Nu cc nhm tn hiu xut 0 v 1 c tn hiu trigger xut l khc nhau, th 4 bit cao v 4 bit thp ca cc bit s c nh x vo cc a ch khc nhau nh di y Bit Tn bit Gi tr khi ng 0 0 0 0 1 R/W c t
7 6 5 4 3-0
NDR7 NDR6 NDR5 NDR4 ---
R/W Cc bit d liu k tip 7-4 R/W Ni dung ca cc bit s c truyn vo cc bit tng ng trong thanh R/W ghi PODRL bi tn hiu trigger xut R/W c ch nh vi PCR. R Khng dng. Cc bit ny ch c khng th thay hiu chnh n.
Bit
Tn bit
Gi tr khi ng
R/W
c t
359
7-4
---
Khng dng. L cc bit ch c v khng th hiu chnh n.
3 2 1 0
NDR3 NDR2 NDR1 NDR0
0 0 0 0
R/W Cc bit d liu k tip (3 0) R/W Ni dung cc bit ny c truyn t cc bit tng ng trong thanh ghi R/W PODRL bi trigger xut c ch R/W nh vi PCR.
11.3.4 Thanh ghi iu khin xut PPG (PCR) Thanh ghi PCR la chn cc tn hiu trigger xut theo tng nhm. Chi tit v vic la chn trigger xut, tham kho phn 11.3.5, Thanh ghi ch xut PPG (PMR)
Bit
Tn bit
Gi tr khi ng 1 1
R/W
c t
7 6
G3CMS1 G3CMS0
R/W Bit la chn compare match cho nhm 3 R/W Cc bit ny la chn trigger xut cho xung xut nhm 3. 00: compare match trn knh 0 ca TPU 01: compare match trn knh 1 ca TPU 10: compare match trn knh 2 ca TPU 11: compare match trn knh 3 ca TPU
5 4
G2CMS1 G2CMS0
1 1
R/W Bit la chn compare match cho nhm 2 R/W Cc bit ny la chn trigger xut cho xung xut nhm 2. 00: compare match trn knh 0 ca TPU 01: compare match trn knh 1 ca
360
TPU 10: compare match trn knh 2 ca TPU 11: compare match trn knh 3 ca TPU 3-0 --1 R/W Khng dng. Cc bit ny lun lun c gi tr l 1, v khng th ghi vo cc bit ny. 11.3.5 Thanh ghi ch xut PPG (PMR) Thanh ghi PMR la chn ch xung xut ca PPG cho tng nhm. Nu la chn o tn hiu xut, th mc thp ca xung s c xut ra khi gi tr trong PODRH l 1 v mt mc cao ca xung s c xut ra khi gi tr ca PODRH l 0. Nu hot ng non-overlapping c la chn, th PPG s cp nht gi tr xut ca n khi c hot ng compare match trn thanh ghi A hay B ca TPU. Chi tit tham kho phn 11.4.4, Xung xut Non-overlapping.
Bit
Tn bit
Gi tr khi ng 1
R/W
c t
G3INV
R/W o nhm 3 Bit ny s cho php la chn l tn hiu xut s l trc tip hay l tn hiu xut s b o (trn nhm 3) 0: o tn hiu xut 1: Tn hiu xut trc tip
G2INV
R/W o nhm 2 Bit ny s cho php la chn l tn hiu xut s l trc tip hay l tn hiu xut s b o (trn nhm 2) 0: o tn hiu xut 1: Tn hiu xut trc tip
5, 4
---
R/W Khng dng Cc bit ny lun c gi tr l 1.
361
G3NOV 0
R/W Bit Non-Overlap nhm 3 La chn ch hot ng l bnh thng hay non-overlapping cho xung xut nhm 3. 0: Ch bnh thng (cc gi tr xut c cp nht khi c hot ng compare match A trong knh TPU c chn) 1: Ch hot ng non-overlapping (gi tr xut s c cp nht khi c hot ng compare match A hay B trn knh TPU c chn)
G2NOV 0
R/W Bit Non-Overlap nhm 2 La chn ch hot ng l bnh thng hay non-overlapping cho xung xut nhm 2. 0: Ch bnh thng (cc gi tr xut c cp nht khi c hot ng compare match A trong knh TPU c chn) 1: Ch hot ng non-overlapping (gi tr xut s c cp nht khi c hot ng compare match A hay B trn knh TPU c chn)
1, 0
---
R/W Khng dng Cc bit ny lun c gi tr l 0. Vic ghi gi tr vo cc bit ny thi nn ghi vo cc gi tr 0.
11.4 Hot ng
Hnh 11.2 Trnh by mt gin khi ca PPG. Xung xut ca PPG c cho php khi cc bit tng ng ca n trong thanh ghi NDER c thit lp l 1. Gi tr ban u c ch nh bi vic thit lp cc bit tng ng trong thanh ghi PODR. Khi c hot ng compare match xy ra, th ni dung ca bit tng ng trong thanh ghi NDR s c chuyn vo PODR cp nht li gi tr xut. D liu xut tun t khng ln hn 8 bit l c kh nng thc hin bi hot ng ghi gi tr xut mi vo thanh ghi NDR trc khi hot ng compare match k tip xy ra.
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Hnh 11.2 Gin khi ca PPG 11.4.1 Gin thi gian tn hiu xut Nu xung xut c cho php, th ni dung ca thanh ghi NDR s c truyn vo thanh ghi PODR v tn hiu xut khi hot ng compare match xy ra. Hnh 11.3 trnh by gin thi gian ca hot ng ny trong trng hp tn hiu xut trong ch bnh thng nhm 2 v 3, c trigger bi compare match A.
Hnh 11.3 Gin thi gian ca truyn v xut ni dung ca NDR (v d) 11.4.2 Qu trnh thit lp cho xung xut trong ch bnh thng Hnh 11.4 trnh by mt v d v tin trnh thit lp cho mt xung xut trong ch thng.
363
Hnh 11.4 Tin trnh thit lp cho xung xut ch bnh thng 11.4.3 V d ca xung xut bnh thng (v d ca xung xut 5-phase) Hnh 11.5 trnh by mt v d m trong xung xut c s dng cho xung xut 5-phase
Hnh 11.5 V d v xung xut bnh thng (xung xut 5-phase)
364
1. Thit lp thanh ghi TGRA trong TPU m c s dng vi vai tr l trigger xut l mt thanh ghi output compare. Thit lp mt chu k trong thanh ghi TGRA cho b m s c xa bi hot ng compare match A. Set bit TGIEA trong thanh ghi TIER ln 1 cho php hot ng ngt qung compare match/input capture A (TGIA) 2. Ghi gi tr HF8 vo thanh ghi NDERH, v thit lp cc bit G3CMS1, G3CMS0, G2CMS1 v G2CMS0 trong thanh ghi PCR la chn hot ng compare match trong knh TPU (c thit lp bc trn) l hot ng trigger output. Ghi gi tr xut l H80 vo thanh ghi NDRH. 3. Khi ng bin m counter trong knh TPU. Khi hot ng compare match A xy ra, th ni dung ca thanh ghi NDRH s c truyn sang thanh ghi PODRH v tn hiu xut. Hm p ng ngt qung TGIA s ghi gi tr xut k tip (HC0) vo thanh ghi NDRH. 4. Xung xut 5-phase (1 hay 2 phase hot ng cng mt lc) c th c thu c mt cch lin tip bng cch ghi cc gi tr H40, H60, H18, H08, H88, trong hm ngt qung TGIA. 11.4.4 Xung xut trong ch Non-Overlapping Trong hot ng non-overlapping, th hot ng truyn t thanh ghi NDR sang PODR c thc hin nh sau: Khi hot ng compare match A xy ra, cc bit trong thanh ghi NDR lun c truyn sang PODR. Khi hot ng compare match B xy ra, cc bit trong thanh ghi NDR ch c truyn khi gi tr ca n l 0, cc bit c gi tr 1 trong thanh ghi NDR s khng c truyn.
Hnh 11.6 Minh ha hot ng xut xung trong ch non-overlapping
Hnh 11.6 Xut xung trong ch non-overlapping Chnh v vy, d liu 0 s c truyn trc d liu 1 bng cch thit lp hot ng compare match B xy ra trc hot ng compare match A. Cc bit trong thanh ghi NDR s khng c thay i trong khong thi gian t khi hot ng compare match B xy ra cho n khi hot ng compare match A xy ra (non-overlapping margin)
365
iu ny c th c hon tt bi hm p ng ngt qung TGIA ghi d liu k tip ln thanh ghi NDR, hay bi ngt qung TGIA kch hot b DTC hay DMAC. Ch d liu k tip phi c ghi trc khi hot ng compare match B k tip xy ra. Hnh 11.7 Trnh by gin thi gian ca hot ng ny
Hnh 11.7 Hot ng non-overlapping v gin ghi NDR 11.4.5 Qu trnh thit lp cho xung xut trong ch non-overlapping Hnh 11.8 trnh by mt tin trnh cho vic thit lp xung xut trong ch nonoverlapping.
Hnh 11.8 Qu trnh thit lp xung xut non-overlapping

366
11.4.6 V d v xung xut trong ch non-overlapping (v d xung xut nonoverlapping b 4-phase) Hnh 11.9 trnh by mt v d m trong xung xut c s dng cho xung xut non-overlapping b 4-phase.
Hnh 11.9 V d xung xut non-overlapping (b 4-phase) 1. Thit lp knh TPU c s dng vi vai tr l knh xut trigger m thanh ghi TGRA v TGRB l cc thanh ghi output compare. Thit lp chu k trong thanh ghi TGRB v non-overlapping margin (ngha l gi tr NDR khng c thay i) trong thanh ghi TGRA, v thit lp bin m counter s c xa bi hot ng compare match B. Set bit TGIEA trong thanh ghi TIER ln 1 cho php ngt qung TGIA. 2. Ghi gi tr HFF vo thanh ghi NDERH, v thit lp cc bit G3CMS1, G3CMS0, G2CMS1, v G2CMS0 trong thanh ghi PCR la chn hot ng compare match trong knh TPU (knh m c la chn trong bc 1) s ng vai tr l output trigger. Set cc bit G3NOV v G2NOV trong thanh ghi PMR ln 1 la chn xung xut trong ch non-overlapping. Ghi d liu xut H95 vo thanh ghi NDRH. 3. Khi ng bin m counter ca TPU (start). Khi mt hot ng compare match trong TGRB xy ra, tn hiu xut s chuyn t 1 sang 0. Khi hot ng compare
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match trong TGRA xy ra, tn hiu xut s chuyn t 0 ln 1 (s thay i t 0 ln 1 s b tr hon bi gi tr c thit lp trong thanh ghi TGRA). Hm p ng ngt qung TGIA ghi gi tr d liu k tip (H65) vo thanh ghi NDRH. 4. Xung xut non-overlapping b 4-phase c th thu c mt cch lin tip bng cch ghi cc gi tr H59, H56, H95 trong hm p ng ngt qung TGIA. 11.4.7 o tn hiu xut Nu cc bit G3INV v G2INV trong thanh ghi PMR u b xa, gi tr xut s l gi tr o cc gi tr trong thanh ghi PODR. Hnh 11.10 trnh by cc tn hiu xut khi cc bit G3INV v G2INV b xa, thm vo vic thit lp ca hnh 11.9
Hnh 11.10 o xung xut 11.4.8 Xung xut c trigger bi tn hiu input capture Xung xut cng c th c trigger bi tn hiu input capture ca TPU nh l bi hot ng compare match. Nu TGRA c chc nng nh l mt thanh ghi input capture trong knh TPU c la chn bi PCR, th xung xut s c trigger bi tn hiu input capture. Hnh 11.11 trnh by gin thi gian ca tn hiu xut ny.
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Hnh 11.11 Xung xut c trigger bi tn hiu input capture
11.5 Ch s dng
11.5.1 Thit lp ch dng module Hot ng PPG c th b cm hay cho php s dng thanh ghi iu khin dng module. Gi tr khi ng s c gn cho PPG b dng ny. Truy xut thanh ghi c cho php bi vic xa ch dng module. Chi tit tham kho phn 19, Ch Power-Down 11.5.2 Hot ng ca cc chn xut xung Cc chn PO0 n PO8 cng c s dng cho cc chc nng ngoi vi khc v d nh TPU. Khi tn hiu xut bi mt chc nng ngoi vi khc c cho php, cc chn tng ng s khng c dng cho xung xut. Mc d vy, d liu truyn t NDR sang PODR vn s xy ra, bt chp chn ang s dng cho chc nng ngoi vi no.
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Chng 12 Giao din giao tip tun t (SCI)

Vi iu khin ny c hai knh giao tip tun t (SCI) c lp. SCI c th x l c giao tip ng b clock v bt ng b. Giao tip d liu tun t bt ng b c th c thc hin bng cc chip giao tip bt ng b chun nh UART (Universal Asynchronous Receiver/Transmitter) hoc ACIA (Asynchronous Communication Interface Adapter. Mt chc nng khc cng c cung cp cho vic giao tip tun t gia cc vi x l (chc nng giao tip a x l). SCI cng ng thi h tr giao din smart card (IC card) theo chun ISO/IEC 7816-3 nh mt ch giao tip bt ng b ngoi. Hnh 12.1 cho thy s khi ca SCI.
12.1 c im
C th la chn gia 2 ch giao tip tun t: bt ng b v ng b clock. C kh nng giao tip theo c ch full-duplex. B truyn v b nhn c lp hon ton vi nhau, cho php qu trnh truyn v nhn c th xy ra ng thi. B m kp trong b truyn v b nhn gip cho qu trnh truyn nhn c din ra lin tc trn d liu tun t. B to xung ni gip to ra bt k tc truyn nhn no mong mun. Clock ngoi c th c chn lm ngun cp clock cho qu trnh chuyn d liu (tr trng hp s dng giao din smart card). C th chn phng php truyn bit thp trc hoc bit cao trc (tr trng hp ch bt ng b 7-bit d liu). Bn ngun ngt qung pht sinh Cc ngun ngt qung l Kt thc truyn, Ht d liu truyn, y d liu nhn, v Li qu trnh nhn. Cc ngt qung Ht d liu truyn v y d liu nhn c th kch hot DTC hoc DMAC. Ch dng module c th c thit lp. Ch bt ng b: di d liu: 7 hoc 8 bit di bit kt thc: 1 hoc 2 bit Parity: Chn, l hoc khng c Pht hin li nhn: Li parity, li overrun, v li frame Pht hin Break: Break c th c pht hin bi c chn RxD trc tip trong trng hp b li frame. Ch ng b clock: di d liu: 8 bits Pht hin li nhn: Li overrun
370
Giao din smart card: Mt tn hiu li s c t ng truyn i khi nhn thy c li parity trong qu trnh giao tip. D liu c th c t ng truyn li khi c mt tn hiu li trong qu trnh truyn. C quy c trc tip v quy c o u c h tr.
Hnh 12.1 S khi ca SCI
12.2 Cc chn xut/nhp

Bng 12.1 Cu hnh chn Knh 3 Tn chn* SCK3 RxD3 TxD3 4 SCK4 RxD4 TxD4 Nhp/Xut Nhp/Xut Nhp Xut Nhp/Xut Nhp Xut Chc nng Clock nhp/xut knh 3 Ng nhp d liu nhn knh 3 Ng xut d liu truyn knh 3 Clock nhp/xut knh 4 Ng nhp d liu nhn knh 4 Ng xut d liu truyn knh 4
Ch : * Cc tn SCK, RxD v TxD s c s dng chung cho c hai knh.
12.3 M t thanh ghi

371
SCI c cc thanh ghi sau. Mt vi bit trong thanh ghi ch tun t (SMR), thanh ghi trng thi tun t (SSR) v thanh ghi iu khin tun t (SCR) s c cc chc nng khc trong cc ch khc: Ch giao tip tun t bnh thng v ch giao din smart card. Cc bit s c m t ring r cho tng ch tng ng vi v tr trong thanh ghi. Knh 3: Thanh ghi dch nhn_3 (RSR_3) Thanh ghi dch truyn_3 (TSR_3) Thanh ghi d liu nhn_3 (RDR_3) Thanh ghi d liu truyn_3 (TDR_3) Thanh ghi ch tun t _3 (SMR_3) Thanh ghi iu khin tun t _3 (SCR_3) Thanh ghi trng thi tun t _3 (SSR_3) Thanh ghi ch smart card_3 (SCMR_3) Thanh ghi tc bit_3 (BRR_3) Knh 4: Thanh ghi dch nhn_4 (RSR_4) Thanh ghi dch truyn_4 (TSR_4) Thanh ghi d liu nhn_4 (RDR_4) Thanh ghi d liu truyn_4 (TDR_4) Thanh ghi ch tun t _4 (SMR_4) Thanh ghi iu khin tun t _4 (SCR_4) Thanh ghi trng thi tun t _4 (SSR_4) Thanh ghi ch smart card_4 (SCMR_4) Thanh ghi tc bit_4 (BRR_4) 12.3.1 Thanh ghi dch nhn (RSR) RSR l mt thanh ghi dch c s dng nhn d liu nhp tun t t chn RxD v chuyn n thnh d liu song song. Khi mt frame d liu c nhn, n s c t ng chuyn ti RDR. RSR khng th giao tip trc tip vi CPU. 12.3.2 Thanh ghi d liu nhn (RDR) RDR l mt thanh ghi 8 bit lu tr d liu nhn. Khi SCI nhn mt frame d liu tun t, n truyn d liu tun t nhn c t thanh ghi RSR ti lu tr trong thanh ghi RDR, gip RSR c th nhn tip d liu sau. Bi v RSR v RDR hot ng nh mt b m kp trong trng hp ny, nn hot ng nhn lin tc c th c
372
tin hnh. Sau khi xc nhn rng bit RDRF trong thanh ghi SSR bng 1, ta c RDR mt ln. RDR khng th c ghi bi CPU.
12.3.3 Thanh ghi d liu truyn (TDR) TDR l mt thanh ghi 8 bit lu d liu truyn. Khi SCI pht hin rng TSR rng, n truyn d liu t TDR sang TSR v bt u qu trnh truyn. Cu trc b m kp ca TDR v TSR cho php truyn tun t lin tc. Nu d liu truyn tip theo c ghi trong TDR khi mt frame c truyn, SCI li tip tc ly d liu em vo TSR v tip tc qu trnh truyn. Mc d TDR c th c c hoc ghi bi CPU trong cng mt lc, c c d liu truyn tin cy, ta ch nn ghi d liu truyn vo TDR mt ln sau khi xc nhn rng bit TDRE trong SSR bng 1.
12.3.4 Thanh ghi dch truyn (TSR) TSR l mt thanh ghi dch truyn d liu tun t. thc hin vic truyn d liu tun t, SCI trc ht s t ng chuyn d liu truyn t TDR vo TSR, sau gi d liu ny ti chn TxD. TSR khng c truy xut trc tip t CPU. 12.3.5 Thanh ghi ch tun t (SMR) SMR c s dng thit lp nh dng truyn tun t ca SCI v chn ngun clock cung cp tc Baud. Mt vi bit trong thanh ghi SMR c chc nng khc nhau trong ch bnh thng hoc ch giao din smart card. Khi SMIF trong SCMR = 0
Khi SMIF trong SCMR = 1
Chc nng bit trong Ch giao tip tun t bnh thng (khi SMIF = 0): Bit Tn bit Gi tr khi R/W c t
373
ng 7 C/A 0 R/W Ch giao tip 0: ch bt ng b 1: ch ng b clock 6 CHR 0 R/W Chiu di k t (ch s dng trong ch bt ng b) 0: chn 8 bit lm chiu di d liu. 1: chn 7 bit lm chiu di d liu. Ch truyn bit thp trc c chn c nh, v bit MSB (bit 7) trong TDR s khng c truyn trong qu trnh truyn. Trong ch ng b clock, th chiu di d liu c chn c nh l 8 bit. 5 PE 0 R/W Cho php parity (ch s dng trong ch bt ng b) Khi bit ny bng 1, bit parity c thm vo d liu truyn trc khi truyn, v bit parity s c kim tra trong qu trnh nhn. Vi nh dng a x l, vic thm v kim tra bit parity s khng c thc hin. 4 O/E 0 R/W Ch parity (ch s dng khi bit PE l 1 trong ch bt ng b) 0: chn parity chn. 1: chn parity l. 3 STOP 0 R/W Chiu di bit kt thc (ch s dng trong ch bt ng b) Chn chiu di bit kt thc trong qu trnh truyn. 0: 1 bit kt thc. 1: 2 bit kt thc. Trong qu trnh nhn, ch c bit kt thc u tin c kim tra. Nu bit kt thc th hai bng 0, n s c xem nh l bit bt u ca frame truyn k tip. 2 MP 0 R/W Ch a x l (ch s dng trong ch bt ng b) Khi bit ny bng 1, chc nng a x l c cho php. Bit PE v thit lp bit O/E s khng c gi
374
tr trong ch a x l. 1 0 CKS1 CKS0 0 0 R/W Chn clock R/W Nhng bit ny chn ngun clock cho b pht tc baud. 00: clock P (n = 0) 01: clock P/4 (n = 1) 10: clock P/16 (n = 2) 11: clock P/64 (n = 3) bit thm mi quan h gia thit lp cc bit ny v tc baud, xem phn 12.3.9, Thanh ghi tc bit (BRR). N l s thp phn cho thy gi tr ca n trong BRR) Chc nng bit trong ch giao din smart card (khi bit SMIF trong SCMR = 1): Bit Tn bit Gi tr khi ng 0 R/W c t
GM
R/W Ch GSM Bit ny bng 1 cho php hot ng theo ch GSM. Trong ch GSM, thi gian thit lp TEND c t trc 11.0 etu k t lc khi ng v chc nng iu khin xut clock c thm vo. bit thm chi tit, xem phn 12.7.6, Truyn d liu (Tr khi trong ch truyn khi_ v 12.7.8, iu khin xut clock. Ch GSM Bit ny bng 1 cho php hot ng theo ch GSM. Trong ch GSM,
BLK
R/W Bit ny bng 1 cho php hot ng theo ch truyn khi. bit thm chi tit, xem phn 12.7.3, Ch truyn khi
PE
R/W Cho php parity (ch s dng trong ch bt ng b) Khi bit ny bng 1, bit parity c thm vo d liu truyn trc khi truyn, v bit parity s c kim tra trong qu trnh nhn.
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O/E
R/W Ch parity (ch s dng khi bit PE l 1 trong ch bt ng b) 0: chn parity chn. 1: chn parity l.
3 2
BCP1 BCP0
0 0
R/W Xung clock c bn 1,0 R/W Nhng bit ny s la chn s chu k clock c bn cho vic truyn 1 bit trong ch giao din smart card. 00: 32 chu k clock (S = 32) 01: 64 chu k clock (S = 64) 10: 372 chu k clock (S = 372) 11: 256 chu k clock (S = 256) bit thm chi tit, xem phn 12.7.4. S c miu t trong phn 12.3.9
1 0
CKS1 CKS0
0 0
R/W Chn clock R/W Nhng bit ny chn ngun clock cho b pht tc baud. 00: clock P (n = 0) 01: clock P/4 (n = 1) 10: clock P/16 (n = 2) 11: clock P/64 (n = 3) bit thm mi quan h gia thit lp cc bit ny v tc baud, xem phn 12.3.9, Thanh ghi tc bit (BRR). N l s thp phn cho thy gi tr ca n trong BRR)
Ch : etu (Elementary Time Unit): thi gian truyn 1 bit. 12.3.6 Thanh ghi iu khin tun t (SCR) SCR l thanh ghi cho php / cm mt s tc v truyn SCI v yu cu ngt qung, v la chn ngun clock cho vic truyn d liu. bit thm chi tit v yu cu ngt qung, xem phn 12.8, Ngun Ngt qung. Khi SMIF trong SCMR = 0
Khi SMIF trong SCMR = 0
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Cc chc nng bit trong ch giao din giao tip tun t bnh thng (Khi SMIF trong SCMR = 0): Bit Tn bit Gi tr khi ng 0 R/W c t
TIE
R/W Cho php ngt qung truyn Khi bit ny bng 1, mt yu cu ngt qung TXI c cho php. Mt yu cu ngt qung TXI c th b xa bi vic c 1 t c TDRE v xa c, hoc bi vic xa bit TIE
RIE
R/W Cho php ngt qung nhn Khi bit ny bng 1, yu cu ngt qung RXI v ERI c cho php. Yu cu ngt qung RXI v ERI c th c xa bng cch c 1 t c RDRF, FER, PER, ORER v xa c, hoc bi vic xa bit RIE.
TE
R/W Cho php truyn Khi bit ny bng 1, vic truyn c cho php. Di iu kin ny, vic truyn tun t c khi ng bi vic ghi d liu truyn ln TDR, v xa c TDRE trong SSR. Ch rng SMR cn c set u tin lp bit TE ln 1 c th quyt nh nh dng truyn. Nu vic truyn b dng bi vic xa bit ny, c TDRE trong SSR s c c nh l 1.
RE
R/W Cho php nhn Khi bit ny bng 1, vic nhn c cho php. Di iu kin ny, vic nhn tun t c khi ng bi vic xc nh bit bt u trong ch bt ng b, hoc xung clock nhp ng b trong ch ng b. Ch rng SMR nn c thit lp u tin set bit RE ln 1 trong trng hp mun quyt nh nh dng nhn. Ngay c khi vic nhn b dng bi vic xa bit
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ny, c RDRF, FER, PER, v ORER vn khng b nh hng bi gi tr trc c gi li. 3 MPIE 0 R/W Cho php ngt a x l (ch c gi tr khi bit MP trong SMR l 1 trong ch bt ng b) Khi bit ny bng 1, d liu nhn trong lc bit a x l bng 0 s b b qua, v thit lp ca cc bit trng thi RDRF, FER, v ORER trong SSR s b cm. Khi nhn d liu trong lc bit a x l l 1, bit ny s c t ng xa v ch nhn bnh thng s khi phc. Khi d liu nhn bao gm MPB = 0 trong SSR ang c nhn, vic truyn d liu nhn t RSR ti RDR, pht hin li nhn, v thit lp cc c RDRF, FER, ORER trong SSR s khng c thc thi. Khi d liu nhn bao gm MPB = 1 c nhn, bit MPB trong SSR c set ln 1, bit MPIE s c t ng xa, cc yu cu ngt qung RXI, ERI v thit lp ca cc c ORER, FER s c cho php. 2 TEIE 0 R/W Cho php ngt qung kt thc truyn Khi bit ny bng 1, mt yu cu ngt qung TEI c cho php. Yu cu ngt qung TEI c th b hy bi vic c gi tr 1 t c TDRE v xa c ny xa c TEND, hoc bi xa bit TEIE. 1 0 CKE1 CKE0 0 0 R/W Cho php clock 1, 0 R/W Nhng bit ny la chn ngun clock v chc nng chn SCK. Ch bt ng b 00: B pht tc Baud ni (Chn SCK hot ng nh cng I/O.) 01: B pht tc Baud ni (Xut ra 1 clock vi tn s bng vi tc bit t chn SCK.) 1X: Clock ngoi (Nhp 1 clock vi tn s gp 16 ln tc bit t chn SCK.)
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Ch ng b clock 0X: Clock ni (Chn SCK hot ng nh ng ra clock.) 1X: External clock (Chn SCK hot ng nh ng vo clock.) Ch : X: Khng quan tm 12.3.7 Thanh ghi trng thi tun t (SSR) SSR l thanh ghi cha cc c trng thi ca SCI v cc bit a x l cho vic truyn d liu. TDRE, RDRF, ORER, PER, v FER ch c th c xa. Mt vi bit trong SSR c cc chc nng khc nhau trong ch bnh thng v ch giao din smart card. Khi SMIF trong thanh ghi SCMR = 0
Khi SMIF trong thanh ghi SCMR = 1
Chc nng cc bit trong Ch giao tip tun t bnh thng (Khi bit SMIF trong SCMR = 0): Bit Tn bit Gi tr khi ng 1 R/W c t
TDRE
R/(W)* C rng thanh ghi d liu truyn Ch r thanh ghi TDR c cha d liu truyn hay khng. [iu kin set] Khi bit TE trong SCR bng 0 Khi d liu c truyn t TDR ti TSR [iu kin xa] Khi 0 c ghi vo TDRE sau khi c TDRE =1 Khi 1 yu cu ngt qung TXI c pht ra
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cho php DTC hoc DMAC ghi d liu vo TDR 6 RDRF 0 R/(W)* C y thanh ghi d liu nhn Ch r thanh ghi RDR c cha d liu nhn hay khng. [iu kin set] Khi vic nhn tun t kt thc bnh thng v d liu c truyn t RSR sang RDR [iu kin xa] Khi 0 c ghi vo RDRF sau khi c RDRF =1 Khi mt yu cu ngt qung RXI c pht ra cho php DTC hoc DMAC c d liu t RDR C RDRF vn gi nguyn gi tr trc khi bit RE trong SCR b xa. Ch rng khi vic truyn tip theo c hon thnh khi c RDRF bng 1, mt li overrun s xy ra v d liu nhn b mt. 5 ORER 0 R/(W)* Li overrun Cho bit c mt li overrun xy ra trong qu trnh nhn v qu trnh nhn kt thc bt thng. [iu kin set] Khi vic truyn tip theo hon thnh trong khi RDRF = 1 Trong thanh ghi RDR, d liu nhn gy ra mt li overrun s c lu tr, nhng d liu nhn sau li overrun s b mt. Khi c ORER c set ln 1, vic truyn tun t tip sau s khng xy ra. Ch rng, trong ch ng b clock, vic truyn tun t cng khng th tip tc. [iu kin xa] Khi 0 c ghi vo ORER sau khi c ORER =1 Ngay c khi bit RE trong SCR b xa, c ORER vn khng b nh hng v gi nguyn gi tr trc . 4 FER 0 R/(W)* Li frame
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Ch ra c mt li frame xy ra trong qu trnh nhn trong ch bt ng b v vic nhn kt thc bt thng. [iu kin set] Khi bit dng l 0 Trong ch 2 bit dng, ch c bit dng u tin c kim tra. Ch rng d liu nhn khi li frame xy ra s c chuyn vo RDR, tuy nhin, c RDRF s khng c lp. Thm vo , khi c FER ang c lp ln 1, qu trnh nhn tun t tip sau s khng c thc thi. Trong ch ng b clock, vic truyn tun t cng khng th tip tc. [iu kin xa] Khi gi tr 0 c ghi vo FER sau khi c FER = 1 Ngay khi bit RE trong SCR c xa, c FER vn khng b nh hng v gi nguyn gi tr trc . 3 PER 0 R/(W)* Li parity Cho bit c mt li parity xy ra trong qu trnh nhn ch bt ng b v qu trnh nhn kt thc bt thng. [iu kin set] Khi c mt li parity c nhn ra trong qu trnh nhn D liu nhn khi c li parity xy ra s c chuyn vo RDR, tuy nhin, c RDRF s khng c lp. Ch rng khi c PER l 1, qu trnh nhn tun t tip theo s khng th c thc thi. Trong ch ng b clock, vic truyn tun t cng khng th tip tc. [iu kin xa] Khi 0 c ghi vo PER sau khi c PER = 1 Ngay c khi bit RE trong SCR b xa, bit PER vn khng b nh hng v vn gi nguyn gi tr. 2 TEND 1 R Kt thc truyn
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[iu kin set] Khi bit TE trong SCR = 0 Khi TDRE = 1 ti qu trnh truyn bit cui ca mt k t truyn [iu kin xa] Khi 0 c ghi vo TDRE sau khi c TDRE =1 Khi mt yu cu ngt qung TXI c pht ra cho php DMAC ghi d liu vo TDR 1 MPB 0 R Bit a x l Cha gi tr bit a x l trong frame nhn. Khi bit RE trong SCR c xa, trng thi trc ca n s c gi nguyn. 0 MPBT 0 R/W Truyn bit a x l Thit lp gi tr bit a x l thm vo frame truyn Ch : * Ch c ghi 0, xa c. Chc nng cc bit trong Ch giao din smart card (Khi bit SMIF trong SCMR=1): Bit Tn bit Gi tr khi ng 1 R/W c t
TDRE
R/(W)* C rng thanh ghi d liu truyn Ch r thanh ghi TDR c cha d liu truyn hay khng. [iu kin set] Khi bit TE trong SCR bng 0 Khi d liu c truyn t TDR ti TSR [iu kin xa] Khi 0 c ghi vo TDRE sau khi c TDRE =1 Khi 1 yu cu ngt qung TXI c pht ra cho php DTC hoc DMAC ghi d liu vo TDR
RDRF
R/(W)* C y thanh ghi d liu nhn Ch r thanh ghi RDR c cha d liu nhn hay
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khng. [iu kin set] RSR to RDR Khi vic nhn tun t kt thc bnh thng v d liu c truyn t RSR sang RDR [iu kin xa] Khi 0 c ghi vo RDRF sau khi c RDRF =1 Khi mt yu cu ngt qung RXI c pht ra cho php DTC hoc DMAC c d liu t RDR C RDRF vn gi nguyn gi tr trc khi bit RE trong SCR b xa. Ch rng khi vic truyn tip theo c hon thnh khi c RDRF bng 1, mt li overrun s xy ra v d liu nhn b mt. 5 ORER 0 R/(W)* Li overrun Cho bit c mt li overrun xy ra trong qu trnh nhn v qu trnh nhn kt thc bt thng. [iu kin set] Khi vic truyn tip theo hon thnh trong khi RDRF = 1 Trong thanh ghi RDR, d liu nhn gy ra mt li overrun s c lu tr, nhng d liu nhn sau li overrun s b mt. Khi c ORER c set ln 1, vic truyn tun t tip sau s khng xy ra. Ch rng, trong ch ng b clock, vic truyn tun t cng khng th tip tc. [iu kin xa] Khi 0 c ghi vo ORER sau khi c ORER =1 Ngay c khi bit RE trong SCR b xa, c ORER vn khng b nh hng v gi nguyn gi tr trc . 4 ERS 0 R/(W)* Trng thi tn hiu li [iu kin set] Khi mt tn hiu li thp c ly mu
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[iu kin xa] Khi 0 c ghi vo ERS sau khi c ERS = 1 3 PER 0 R/(W)* Li parity Cho bit c mt li parity xy ra trong qu trnh nhn ch bt ng b v qu trnh nhn kt thc bt thng. [iu kin set] Khi c mt li parity c nhn ra trong qu trnh nhn D liu nhn khi c li parity xy ra s c chuyn vo RDR, tuy nhin, c RDRF s khng c lp. Ch rng khi c PER l 1, qu trnh nhn tun t tip theo s khng th c thc thi. Trong ch ng b clock, vic truyn tun t cng khng th tip tc. [iu kin xa] Khi 0 c ghi vo PER sau khi c PER = 1 Ngay c khi bit RE trong SCR b xa, bit PER vn khng b nh hng v vn gi nguyn gi tr. 2 TEND 1 R Kt thc truyn Bit ny bng 1 khi khng c tn hiu li c truyn t bn nhn, v d liu truyn tip theo sn sng c chuyn vo TDR. [iu kin set] Khi c bit TE v ERS trong SCR l 0 Khi ERS = 0 v TDRE = 1 mt khong thi gian nht nh sau khi hon thnh vic truyn 1 byte d liu. Thi gian c thit lp ph thuc vo vic thit lp cc thanh ghi nh sau: Khi GM = 0 v BLK = 0, 2.5 etu sau khi qu trnh truyn bt u Khi GM = 0 v BLK = 1, 1.5 etu sau khi qu trnh truyn bt u Khi GM = 1 v BLK = 0, 1.0 etu sau khi qu trnh truyn bt u Khi GM = 1 v BLK = 1, 1.0 etu sau khi qu trnh truyn bt u
384
[iu kin xa] Khi 0 c ghi vo TEND sau khi c TEND =1 Khi mt yu cu ngt qung TXI c pht ra cho php DTC hay DMAC ghi d liu k tip vo TDR 1 0 MPB MPBT 0 0 R R/W Bit a x l Khng dng trong ch giao din smart card. Truyn bit a x l Ghi 0 vo bit ny trong ch giao din smart card. Ch : * Ch c ghi 0, xa c. 12.3.8 Thanh ghi Ch Smart Card (SCMR) SCMR la chn ch giao din smart card v nh dng ca n.
Bit Tn bit
Gi tr khi ng Tt c l 1 0
R/W
c t
7 ti 4 3
--
Khng dng.
SDIR
R/W Chiu truyn d liu Smart Card Chn nh dng chuyn tun t/song song. 0: Truyn vi LSB u tin 1: Truyn vi MSB u tin Bit ny ch c gi tr khi nh dng d liu 8 bit c dng cho vic truyn/nhn, khi nh dng 7 bit d liu c s dng, d liu lun lun c truyn/nhn vi LSB u tin.
SINV
R/W o d liu Smart Card o cp logic d liu truyn/nhn. Bit ny khng nh hng n cp logic ca bit parity. o bit
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parity, ta o bit O/E trong SMR. 0: Ni dung TDR c truyn y nguyn. D liu nhn c lu tr nh trong thanh ghi RDR. 1: Ni dung TDR c o trc khi truyn. D liu nhn c lu tr ngc vi trong thanh ghi RDR. 1 0 -SMIF 1 0 R Khng dng. Khi bit ny c lp ln 1, ch giao din smart card c chn. 0: Ch bt ng b bnh thng hoc ng b clock 1: Ch giao din smart card 12.3.9 Thanh ghi tc bit (BRR) BBR l mt thanh ghi 8 bit dng iu chnh tc bit. Bi v SCI iu khin tc baud c lp cho tng knh, cc tc bit khc nhau cng s c thit lp cho tng knh. Bng 12.2 cho thy mi quan h gia thit lp N trong BRR v tc bit B cho ch bt ng b bnh thng, ch ng b clock, v ch giao din smart card. Gi tr khi u ca BRR l HFF, v n c th c c hoc vit bi CPU mi lc. Bng 12.2 Mi quan h gia thit lp N v tc bit B R/W La chn ch giao din Smart Card
[Ch thch] B: Tc bit (bit/s) N: Thit lp BRR cho b pht tc baud (0 N 255) Pf: Tn s hot ng (MHz) n v S: c quyt nh bi thit lp ca SMR nh bng di.
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Thit lp SMR CKS1 0 0 1 1 CKS0 0 1 0 1 n 0 1 2 3
Thit lp SMR BCP1 0 0 1 1 BCP0 0 1 0 1 S 32 64 372 256
Bng 12.3 cho thy cc mu thit lp N trong BRR ch bt ng b bnh thng. Bng 12.4 cho thy thit lp tc bit ti a cho tng tn s hot ng. Bng 12.6 v 12.8 cho thy cc mu thit lp N trong BRR ch ng b clock v ch giao din smart card. Trong ch giao din smart card, s chu k clock c bn S trong thi gian truyn d liu 1 bit c th c la chn. bit thm chi tit, xem phn 12.7.4, Thi gian ly mu d liu truyn v nhn. Bng 12.5 v 12.7 cho thy tc bit ti a vi ng nhp clock ngoi. Bng 12.3 V d v vic thit lp BRR cho cc tc bit khc nhau (ch bt ng b)(1)
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Bng 12.3 V d v vic thit lp BRR cho cc tc bit khc nhau (ch bt ng b)(2)
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Bng 12.4 Tc bit ti a cho tng tn s hot ng (Ch bt ng b)
Bng 12.5 Tc bit ti a vi ng nhp clock ngoi (Ch bt ng b)
Bng 12.6 Thit lp BRR cho cc tc bit khc nhau (Ch ng b clock)
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[Ch thch] (B trng) : Thit lp b cm. : C th thit lp, nhng s xy ra li. * : Khng th tip tc vic truyn/nhn.
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Bng 12.7 Tc bit ti a vi ng nhp clock ngoi (Ch ng b clock)
Bng 12.8 Thit lp BRR cho cc tc bit khc nhau (Ch giao din smart card, n = 0, S = 372)
Bng 12.9 Tc bit ti a vi ng nhp clock ngoi (Ch giao din smart card, n = 0, S = 372)
12.4 Hot ng trong ch bt ng b

Hnh 12.2 cho thy nh dng chung cho vic giao tip tun t bt ng b. 1 frame gm 1 bit khi u (mc thp), tip theo l d liu truyn/nhn, mt bit parity, v cui cng l bit dng (mc cao). Trong giao tip tun t bt ng b, ng giao tip thng c to ra bi trng thi nh du (mc cao). SCI s kim tra ng
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giao tip, v khi n chuyn sang trng thi trng (mc thp), n s tip nhn bit khi u v khi ng giao tip tun t. Bn trong SCI, b truyn v b nhn l hai n v c lp, cho php mt giao tip full-duplex. C b truyn v b nhn u c cu trc b m kp, v th d liu c th c c hoc ghi trong qu trnh truyn hay nhn, cho php vic truyn nhn d liu lin tc.
Hnh 12.2 nh dng d liu trong giao tip bt ng b (V d vi d liu 8-Bit, bit parity, 2 bit dng) 12.4.1 nh dng truyn d liu Bng 12.10 cho thy nh dng truyn d liu c th c s dng trong ch bt ng b. Bt k nh dng no trong 12 nh dng trn u c th c chn da trn thit lp thanh ghi SMR. bit thm chi tit v bit a x l, xem phn 12.5, Chc nng giao tip a x l. Bng 12.10 Cc nh dng truyn tun t (Ch bt ng b)
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[Ch thch] S: Bit khi u STOP: Bit dng P: Bit parity MPB: Bit a x l. 12.4.2 nh thi mu d liu nhn v Reception Margin trong ch bt ng b Trong ch bt ng b, SCI hot ng trn mt clock c bn c tn s gp 16 ln tc bit. Trong qu trnh nhn, SCI s dng clock c bn ly mu cc cnh xung ca bit khi ng, v bt u qu trnh ng b ha ni. Bi v d liu nhn c ly mu ti cnh ln ca xung th 8 trong clock cn bn, d liu s c ci gia mi bit, nh hnh 12.3. V vy, reception margin trong ch bt ng b s c xc nh nh cng thc (1) bn di.
Cng thc (1)
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M: Reception margin N: T l gia tc bit v clock (N = 16) D: Duty cycle of clock (D = 0.5 ti 1.0) L: di khung (L = 9 ti 12) F: Gi tr tuyt i ca lch tn s clock Gi s gi tr ca F = 0, v D = 0.5 trong cng thc (1), reception margin c xc nh bi cng thc sau.
Mc d vy, y ch l gi tr tnh ton, mt margin t 20% ti 30% c th c chp nhn trong thit k h thng.
Hnh 12.3 nh thi mu d liu nhn trong ch bt ng b 12.4.3 Clock C clock ni (pht ra bi bt pht tc baud ni) v clock ngoi trn chn SKC u c th c la chn lm clock truyn SCI, da vo thit lp ca bit C/A trong SMR v bit CKE1, CKE0 trong SCR. Khi mt clock ngoi c a vo chn SCK, tn s clock nn gp 16 ln tc bit s dng. Khi SCI hot ng bi 1 clock ni, clock c th xut ra t chn SCK. Tn s clock xut trong trng hp ny bng vi tc bit, v cnh ln ca clock s xy ra gia bit d liu truyn, nh trong hnh 12.4
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Hnh 12.4 Mi quan h v pha gia Clock xut v D liu truyn (Ch bt ng b) 12.4.4 Khi to SCI (Ch bt ng b) Trc khi truyn nhn d liu, trc ht ta phi xa bit TE v RE trong SCR, sau khi to SCI nh m t trong s mu hnh 12.5. Trong qu trnh hot ng, mun thay i ch (nh nh dng truyn v.v), bit TE v RE cn phi c xa trc khi i. Khi bit TE bng 0, c TDRE c set ln 1. Ch rng xa bit RE s khng khi to cc c RDRF, PER, FER, ORER, hay RDR. Khi clock ngoi c s dng trong ch bt ng b, clock phi c cung cp ngay c trong qu trnh khi to.
Hnh 12.5 Lu khi to SCI mu Ch thch: [1] Thit lp bit trong ICR cho tng ng vi d liu nhn hoc s dng 1 clock ngoi. [2] Thit lp la chn clock trong SCR. Chc chn rng cc bit RIE, TIE, TEIE, MPIE, TE v RE u bng 0.
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Khi clock ngoi c chn trong ch bt ng b, clock s c pht ra ngay lp tc sau khi thit lp SCR. [3] Thit lp nh dng truyn d liu trong SMR v SCMR [4] Ghi gi tr tng ng vi tc bit trong BRR. Bc ny khng cn thit nu s dng 1 clock ngoi. [5] i t nht 1 bit ngh tri qua, sau set bit TE hoc RE trong SCR ln 1. ng thi set lun cc bit RIE, TIE, TEIE, v MPIE. Set cc bit TE v RE ln 1 s cho php cc chn TxD, RxD c s dng. 12.4.5 Truyn d liu tun t (ch bt ng b) Hnh 12.6 cho thy 1 v d ca vic truyn trong ch bt ng b. Trong khi truyn, SCI hot ng nh m t sau. 1. SCI theo di c TDRE trong SSR, v nu c ny bng 0, n s nhn bit rng d liu c ghi vo TDR, v truyn d liu t TDR sang TSR. 2. Sau khi truyn d liu t TDR sang TSR, SCI set c TDRE ln 1 v bt u truyn. Nu bit TIE trong SCR bng 1 trong thi gian ny, mt yu cu ngt qung TXI s c pht ra. Bi v chng trnh x l ngt qung s ghi d liu truyn tip theo vo TDR trc khi vic truyn d liu hin ti chm dt, vic truyn lin tc s c cho php. 3. D liu c gi i t chn TxD s theo th t sau: bit khi ng, d liu truyn, bit parity hoc bit a x l (c th b i ty theo nh dng), v bit dng. 4. SCI s kim tra c TDRE trong khi truyn bit dng. 5. Nu c TDRE bng 0, d liu truyn tip theo s c truyn t TDR sang TSR, bit dng s c truyn, v sau vic truyn tun t frame tip theo s c bt u. 6. Nu c TDRE bng 1, c TEND trong SSR c set ln 1, bit dng s c gi, v bc vo trng thi mark (output lun bng 1). Nu bit TEIE trong SCR bng 1 trong thi gian ny, 1 ngt qung TEI s c pht ra. Hnh 12.7 cho thy 1 lu mu cho qu trnh truyn trong ch bt ng b.
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Hnh 12.6 V d v hot ng truyn trong Ch bt ng b (V d vi d liu 8 bit, parity, v 1 bit dng)
Hnh 12.7 Lu truyn tun t mu Ch thch:
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[1] Khi to SCI: Chn TxD c thit k l chn xut d liu truyn. Sau khi bit TE c set ln 1, s 1 s c xut ra nh l 1 frame, v vic truyn c cho php. [2] SCI kim tra trng thi v ghi d liu truyn: c SSR v kim tra c TDRE c bng 1 khng, sau ghi d liu truyn vo TDR v xa c TDRE. [3] Th tc truyn tun t lin tc: tip tc qu trnh truyn tun t, c 1 t c TDRE xc nhn rng vic ghi c cho php, sau ghi d liu vo TDR, v xa c TDRE. Tuy nhin, c TDRE s c kim tra v xa t ng khi DTC hay DMAC c khi ng bi 1 ngt qung TXI v ghi d liu vo TDR. [4] dng vic xut khi kt thc truyn: Lp DDR cho port tng ng chn TxD ln 1, xa DR, xa bit TE trong SCR. 12.4.6 Nhn d liu tun t (ch bt ng b) Hnh 12.8 cho thy 1 v d ca qu trnh nhn trong ch bt ng b. Trong khi nhn, SCI hot ng nh sau. 1. SCI theo di ng lin lc, v nu c 1 bit khi ng c pht hin, n s bt u qu trnh ng b ni, lu tr d liu nhn RSR, v kim tra bit parity, bit dng. 2. Nu c 1 li overrun (khi nhn xong d liu tip theo trong lc c RDRF trong SSR vn cn l 1) xy ra, bit ORER trong SSR s c set ln 1. Nu bit RIE trong SCR cng bng 1 trong thi gian ny, mt yu cu ngt qung ERI s c pht ra. D liu nhn s khng c chuyn ti RDR. C RDRF vn gi gi tr 1. 3. Nu c 1 li parity xy ra, bit PER trong SSR s c set ln 1 v d liu nhn c chuyn sang RDR. Nu bit RIE trong SCR c set ln 1 trong thi gian ny, 1 yu cu ngt qung ERI s c pht ra. 4. Nu c 1 li framing (khi bit dng l 0) c pht hin, bit FER trong SSR s c set ln 1 v d liu nhn s c chuyn vo RDR. Nu bit RIE trong SCR cng c set ln 1 trong thi gian ny, 1 yu cu ngt qung ERI s c pht ra. 5. Nu vic nhn kt thc thnh cng, bit RDRF trong SSR s c set ln 1, v d liu nhn s c chuyn vo RDR. Nu bit RIE trong SCR bng 1 trong thi gian ny, mt yu cu ngt qung RXI s c pht ra. Bi v chng trnh x l ngt qung RXI s c d liu nhn vo RDR trc khi vic nhn d liu tip theo kt thc, vic nhn lin tc s kh thi.
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Hnh 12.8 V d v hot ng nhn trong Ch bt ng b (V d vi d liu 8 bit, parity, v 1 bit dng) Bng 12.11 cho thy trng thi ca cc c trng thi SSR v vic x l d liu nhn khi c 1 li nhn c pht hin. Trong trng hp c li nhn, c RDRF vn gi nguyn gi tr ca n trc khi nhn d liu. Vic nhn s khng c tip tc khi c 1 c li nhn vn cn gi tr 1. V vy, cn phi xa c ORER, FER, PER v RDRF trc khi tip tc qu trnh nhn. Hnh 12.9 cho thy 1 lu mu cho vic nhn d liu tun t. Bng 12.11 Cc c trng thi SSR v Qu trnh x l d liu nhn C trng thi SSR RDRF* ORER 1 0 0 1 1 0 1 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 D liu nhn Mt Chuyn vo RDR Chuyn vo RDR Mt Mt Chuyn vo RDR Mt Kiu li nhn Li overrun Li framing Li parity Li overrun v li framing Li overrun v li parity Li framing v li parity Li overrun+li parity+li framing
Ch : C RDRF s gi nguyn gi tr nh trc khi nhn d liu
399
Hnh 12.9 Lu mu nhn tun t Ch thch: [1] Khi to SCI: Chn RxD c thit k mc nh l chn nhp d liu nhn. [2] [3] X l li nhn v pht hin break: Nu c 1 li nhn xy ra, ta c cc c ORER, PER, FER trong SSR xc nh li. Sau khi dng chng trnh x l li tng ng, hy nh xa cc c ORER, PER, FER v 0. Vic nhn s khng c tip tc khi c 1 trong cc c ny = 1. Trong trng hp li framing, 1 break c th c pht hin bi vic c gi tr ca cng nhp tng ng vi chn RxD. [4] SCI kim tra trng thi v c d liu nhn: c SSR v kim tra xem bit RDRF c bng 1 khng. Sau c d liu nhn ti RDR v xa c RDRF. Vic chuyn bit RDRF ny t 0 ln 1 cng phi c xc nh bi mt ngt qung RXI. [5] Th tc nhn tun t lin tc: lin tc mt qu trnh nhn tun t, trc khi bit dng ca frame hin ti c nhn, c c RDRF v RDR, sau xa c RDRF. Tuy nhin, c RDRF cng s c xa t ng khi c 1 DTC hoc DMAC c khi ng bi 1 ngt qung RXI v c d liu t RDR.
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12.5 Chc nng giao tip a x l

Vic s dng chc nng giao tip a x l cho php truyn d liu gia mt s b x l c chia s ng giao tip, bng cch giao tip tun t bt ng b s dng nh dng a x l, tc l s c thm 1 bit a x l c truyn chung vi d liu. Khi hot ng giao tip a x l lm vic, mi trm nhn u c nh a ch bi 1 m ID ring. Mt chu k giao tip tun t bao gm hai chu k thnh phn: mt chu k truyn ID nh v trm nhn, v mt chu k truyn d liu cho trm nhn . Bit a x l c dng phn bit gia chu k truyn ID v chu k truyn d liu. Nu bit a x l l 1, giao tip ang trong chu k truyn ID; ngc li, giao tip ang trong chu k truyn d liu. Hnh 12.10 cho thy 1 v d ca vic giao tip gia cc b x l s dng nh dng a x l. Trm truyn trc tin gi ra d liu cha m ID ca trm nhn v bit a x l = 1. Sau n truyn d liu truyn vi bit a x l = 0. Trm nhn b qua d liu cho ti khi c 1 d liu vi bit a x l = 1 c gi ti. Sau khi nhn c khi d liu ny, n s so snh d liu vi ID ca chnh n. Trm no c s ID trng vi d liu nhn s nhn d liu tip theo. Trm no khng c s ID trng vi d liu nhn th s tip tc b qua d liu cho n khi c 1 d liu vi bit a x l bng 1 khc c gi ti. SCI s dng bit MPIE trong SCR thc thi chc nng ny. Khi bit MPIE bng 1, vic truyn d liu nhn t RSR ti RDR, pht hin c li, v thit lp cc c trng thi trong SSR (set RDRF, FER, ORER ln 1) u b cm cho ti khi c mt d liu vi bit a x l bng 1 c nhn. Khi nhn c 1 d liu nh vy, bit MPBR trong SSR c set ln 1 v bit MPIE t ng c xa, do vic nhn s c ti din. Nu bit RIE trong SCR c set ln 1 lc ny, mt ngt qung RXI s c pht ra. Khi nh dng a x l c la chn, thit lp bit parity s khng cn gi tr. Tt c cc thit lp bit khc v clock s dng s ging nh ch bt ng b bnh thng.
Hnh 12.10 V d v Giao tip s dng nh dng a x l (Truyn d liu HAA ti Trm A Station A) 12.5.1 Qu trnh truyn d liu tun t a x l Hnh 12.11 cho thy 1 lu mu cho vic truyn d liu tun t a x l. Cho mt chu k truyn ID, set bit MPBT trong SSR ln 1 trc khi truyn. Cho mt chu
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k truyn d liu, xa bit MPBT trong SSR trc khi truyn. Tt c cc hot ng khc ca SCI u ging nh trong ch bt ng b.
Hnh 12.11 Lu mu truyn d liu tun t a x l Ch thch: [1] Khi to SCI: Chn TxD c thit k l chn xut d liu truyn. Sau khi bit TE c set ln 1, s 1 s c xut ra nh l 1 frame, v vic truyn c cho php. [2] SCI kim tra trng thi v ghi d liu truyn: c SSR v kim tra c TDRE c bng 1 khng, sau ghi d liu truyn vo TDR, lp bit MPBT trong SSR ln 1 v cui cng v xa c TDRE. [3] Th tc truyn tun t lin tc: tip tc qu trnh truyn tun t, c 1 t c TDRE xc nhn rng vic ghi c cho php, sau ghi d liu vo TDR, v xa c TDRE. Tuy nhin, c TDRE s c kim tra v xa t ng khi DTC hay DMAC c khi ng bi mt ngt qung TXI v ghi d liu vo TDR. [4] dng vic xut khi kt thc truyn:
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Set DDR cho port tng ng chn TxD ln 1, xa DR, xa bit TE trong SCR. 12.5.2 Qu trnh nhn d liu tun t a x l Hnh 12.13 cho thy lu mu ca qu trnh nhn d liu tun t a x l. Nu bit MPIE trong SCR bng 1, d liu s c b qua cho ti khi c khi d liu vi bit a x l bng 1 c gi. Trong qu trnh nhn d liu vi bit a x l bng 1, d liu nhn s c chuyn vo RDR. Mt ngt qung RXI c pht ra trong lc ny. Tt c cc hot ng khc ca SCI u ging nh ch bt ng b. Hnh 12.12 cho thy mt v d v hot ng ca SCI trong qu trnh nhn theo nh dng a x l.
Hnh 12.12 V d hot ng nhn ca SCI (V d vi d liu 8-Bit, Bit a x l, mt bit dng)
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Hnh 12.13 Lu d mu qu trnh nhn tun t a x l Ch thch: [1] Khi to SCI: Chn RxD c thit k mc nh l chn nhp d liu nhn. [2] Chu k nhn ID: Set bit MPIE trong SCR ln 1. [3] SCI kim tra trng thi, kim tra ID nhn v so snh: c SSR v kim tra xem c RDRF c bng 1 khng, sau c d liu nhn trong RDR v so snh n vi ID ca trm. Nu d liu ny khng trng vi ID ca trm, set bit MPIE ln 1 tr li, v xa c RDRF. Nu d liu trng vi ID ca trm, xa c RDRF. [4] SCI kim tra trng thi v d liu nhn: c SSR v kim tra xem c RDRF c c set ln 1 khng, sau c d liu nhn trong RDR. [5] X l li nhn v pht hin break: Nu c 1 li nhn xy ra, c c ORER v FER trong SSR xc nh li. Sau khi thc hin x l li, phi chc rng ORER v FER u c xa. Vic nhn s khng c ti din nu 1 trong 2 c ny vn cn l 1. Trong trng hp c li framing, 1 break c th c pht hin bi c gi tr chn RxD.
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12.6 Hot ng trong ch ng b clock

Hnh 12.14 cho thy nh dng chung cho giao tip ng b clock. Trong ch ng b clock, d liu c truyn hoc nhn mt cch ng b vi xung clock. Mt k t trong d liu truyn bao gm 8 bit d liu. Trong qu trnh truyn d liu, SCI xut d liu trong khong t 1 cnh xung ca clock ng b ti 1 cnh xung tip theo. Trong qu trnh nhn d liu, SCI nhn d liu ng b vi 1 cnh ln ca clock ng b. Sau khi xut 8 bit, ng truyn gi li trng thi xut ca MSB. Trong ch ng b clock, bit parity v bit a x l s khng c thm vo. Bn trong SCI, b truyn v b nhn l hai n v c lp, cho php giao tip full-duplex bng mt clock chung. C b truyn v b nhn u c cu trc b m kp, v th d liu truyn tip theo c th c ghi trong khi truyn, hay d liu nhn trc c th c c trong qu trnh nhn, cho php vic truyn d liu lin tc.
Ch : * Gi mc cao, tr khi ang trong khi truyn lin tc Hnh 12.14 nh dng d liu trong giao tip ng b clock (LSB truyn trc) 12.6.1 Clock Ta c th la chn gia mt clock ni (pht ra bi b pht tc baud ni) hoc mt clock ng b ngoi thng qua chn SCK, da vo thit lp ca cc bit CKE1 v CKE0 trong SCR. Khi SCI hot ng vi mt clock ni, clock ng b s c xut ra chn SCK. Tm xung clock ng b c xut ra truyn 1 k t, v khi khng c hot ng truyn, clock s c c nh mc cao. Ch rng trong qu trnh nhn, clock ng b s c xut ra cho ti khi c mt li overrun xy ra, hoc ti khi bit RE c xa. 12.6.2 Khi to SCI (Ch ng b clock) Trc khi truyn nhn d liu, ta phi xa bit TE v RE trong SCR, sau khi ng SCI nh m t trong lu mu hnh 12.15. Khi ch hin hnh (nh nh dng truyn) b thay i, bit TE v RE bt buc phi b xa trc khi thay i. Khi bit TE b xa, c TDRE c set ln 1. Tuy nhin, xa bit RE s khng khi to cc c RDRF, PER, FER, ORER, hay RDR.
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Ch thch: [1] Set bit trong ICR cho chn tng ng khi nhn d liu hoc s dng 1 clock ngoi. [2] Thit lp la chn clock trong SCR. Cn phi chc chn rng cc bit RIE, TIE, TEIE, MPIE, TE, RE c xa. [3] Thit lp nh dng truyn d liu trong SMR v SCMR [4] Ghi gi tr tc bit vo BRR. Bc ny khng cn thit khi ta s dng 1 clock ngoi. [5] Ch 1 khong thi gian t nht l 1 bit, sau set bit TE v RE trong SCR ln 1. ng thi set cc bit RIE, TIE, TEIE, MPIE ln 1. Vic lp cc bit TE v RE s cho php cc chn TxD, RxD hot ng. Ch : Trong hot ng truyn nhn ng thi, bit TE v bit RE cn c xa v lp cng lc. Hnh 12.15 Lu mu qu trnh khi to SCI 12.6.3 Qu trnh truyn d liu tun t (Ch ng b clock) Hnh 12.16 cho thy v d v hot ng truyn d liu trong ch ng b clock. Trong khi truyn, SCI hot ng nh sau. 1. SCI quan st c TDRE trong SSR, nu c bng 0, n nhn ra rng d liu c ghi vo TDR, do n s truyn d liu t TDR sang TSR. 2. Sau khi truyn d liu t TDR sang TSR, SCI set c TDRE ln 1 v bt u truyn. Nu bit TIE trong SCR bng 1 lc ny, mt yu cu ngt qung TXI s c pht ra. Bi chng trnh x l ngt qung TXI s ghi d liu truyn tip theo vo TDR trc khi qu trnh truyn ca d liu hin ti kt thc, vic truyn lin tc s c th c thc hin. 3. D liu 8 bit c gi t chn TxD ng b vi clock xut khi ch clock xut c chn, v ng b vi clock nhp khi ta s dng 1 clock ngoi. 4. SCI kim tra c TDRE trong lc gi bit cui cng 5. Nu c TDRE c xa, d liu truyn tip theo s c chuyn t TDR sang TSR, v qu trnh truyn tun t ca frame tip theo s bt u. 6. Nu c TDRE c set ln 1, c TEND trong SSR s c set ln 1, v chn TxD s gi nguyn trng thi xut bit cui. Nu bit TEIE trong SCR c set ln 1 lc
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ny, mt yu cu ngt qung TEI s c pht ra. Chn SCK c gi mc in p cao. Hnh 12.17 cho thy lu mu cho qu trnh truyn d liu tun t. Ngay c khi c TDRE c xa, qu trnh truyn vn khng c bt u khi c 1 c li nhn (ORER, FER, hay PER) c gi tr 1. Cn chc chn xa cc c ny trc khi bt u qu trnh truyn. Ch rng xa bit RE khng lm cho cc c ny c xa.
Hnh 12.16 V d hot ng truyn trong Ch ng b clock
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Ch thch [1] Khi to SCI: Chn TxD c mc nh l chn xut d liu. [2] SCI kim tra trng thi v ghi d liu truyn: c SSR v kim tra c TDRE c bng 1 khng, sau ghi d liu truyn vo TDR v xa c TDRE. [3] Th tc truyn tun t lin tc: tip tc qu trnh truyn tun t, c 1 t c TDRE xc nhn rng vic ghi c cho php, sau ghi d liu vo TDR, v xa c TDRE. Tuy nhin, c TDRE s c kim tra v xa t ng khi DTC hay DMAC c khi ng bi 1 ngt qung TXI v ghi d liu vo TDR.
Hnh 12.17 Lu mu qu trnh truyn d liu tun t 12.6.4 Qu trnh nhn d liu tun t (Ch ng b clock) Hnh 12.18 cho thy 1 v d v hot ng nhn ca SCI trong ch ng b clock. Trong qu trnh nhn tun t, SCI hot ng nh sau. 1. SCI bt u khi to ni v ng b vi clock ng b nhp/xut, bt u nhn d liu, v cha d liu nhn vo RSR. 2. Nu c 1 li overrun (khi nhn xong d liu sau m c RDRF trong SSR vn bng 1) xy ra, bit ORER trong SSR c set ln 1. Nu bit RIE trong bng 1 lc ny, mt yu cu ngt qung ERI c pht ra. D liu nhn s khng c chuyn vo RDR. C RDRF vn gi gi tr 1. 3. Nu qu trnh nhn kt thc thnh cng, bit RDRF trong SSR c gi tr 1, v d liu nhn c chuyn vo RDR. Nu bit RIE trong SCR bng 1 lc ny, mt yu cu ngt qung RXI s c pht ra. Bi chng trnh x l ngt qung RXI s c d liu nhn truyn vo RDR trc khi qu trnh nhn d liu tip theo kt thc, vic nhn d liu lin tc c th c thc hin.
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Hnh 12.18 V d v hot ng nhn trong Ch ng b clock Qu trnh truyn s khng c tip tc khi c 1 c li nhn c gi tr 1. V vy, cn phi xa cc bit ORER, FER, PER v RDRF trc khi tip tc qu trnh truyn. Hnh 12.19 cho thy 1 lu mu cho qu trnh truyn d liu tun t.
Hnh 12.19 Lu mu qu trnh nhn tun t Ch thch:
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[1] Khi to SCI: Chn RxD c thit k mc nh l chn nhp d liu nhn. [2] [3] X l li nhn: Khi c mt li nhn xy ra, c c ORER trong SSR, v sau khi thc hin x l li, xa c ORER. Vic nhn khng c tip tc nu c ORER vn bng 1. [4] SCI kim tra trng thi v c d liu nhn: c SSR v kim tra chc rng c RDRF bng 1, sau c d liu nhn c trong RDR v xa c RDRF. Vic chuyn trng thi c RDRF t 0 sang 1 cng c th c thc thi bi mt ngt qung RXI. [5] Th tc truyn tun t lin tc: qu trnh nhn c lin tc, trc khi bit MSB (bit 7) ca frame hin ti c nhn, ta c c RDRF, c RDR v xa RDRF. Tuy nhin, c RDRF s c xa t ng khi DTC hay DMAC c khi ng bi ngt qung RXI v c d liu t RDR. 12.6.5 Qu trnh truyn nhn d liu tun t ng thi (Ch ng b clock) Hnh 12.20 cho thy lu mu ca hot ng truyn v nhn ng thi. Sau khi khi ng SCI, cc th tc tip theo cn phi c s dng truyn v nhn d liu ng thi. chuyn t ch truyn sang ch truyn nhn ng thi, sau khi SCI hon thnh vic truyn v c TDRE, TEND l 1, ta xa bit TE. Sau ng thi set bit TE v RE ln 1 vi ch 1 cu lnh n. chuyn t ch nhn sang ch truyn nhn ng thi, sau khi SCI hon thnh vic nhn, xa bit RE. Sau xa bit RDRF v cc c li nhn (ORER, FER, PER), ng thi set bit TE v RE ln 1 vi ch mt cu lnh n.
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Ch thch: [1] Chn TxD v RxD c mc nh l cc chn xut v nhp d liu. [2] SCI kim tra trng thi v ghi d liu truyn: c SSR v kim tra c TDRE c bng 1, sau ghi d liu truyn ln TDR v xa TDRE. Vic chuyn trng thi t 0 ln 1 ca c TDRE c th c thc hin bi 1 ngt qung TXI. [3] X l li nhn: Nu c 1 li nhn xy ra, c c ORER trong SSR, v sau khi thc hin x l li, xa ORER. Qu trnh nhn s khng c tip tc nu c ORER vn bng 1. [4] SCI kim tra trng thi v c d liu nhn: c SSR v kim tra c RDRF c bng 1, sau c d liu nhn t RDR v xa c RDRF. Qu trnh nhn s khng c tip tc nu RDRF vn bng 1. [5] Th tc truyn nhn tun t lin tc: vic truyn/nhn c lin tc, trc khi bit MSB (bit 7) ca frame hin ti c c xong, ta phi c c RDRF, c RDR v xa RDRF. Tng t, trc khi MSB (bit 7) ca frame hin ti c truyn, c 1 t TDRE chc rng vic ghi c cho php. Sau ghi d liu vo TDR v xa TDRE. Tuy nhin, c TDRE s c kim tra v xa t ng khi DTC hay DMAC c khi ng bi ngt qung TXI, v ghi d liu vo TDR. Tng t vy, RDRF s c kim tra v xa t ng khi DTC/DMAC c kch hot bi 1 ngt qung RXI, v c d liu t RDR.
Hnh 12.20 Lu mu cho vic truyn nhn ng thi
12.7 Hot ng trong ch giao din smart card

SCI h tr giao din IC card (smart card), tun theo chun ISO/IEC 7816-3 (Card nhn din), nh l mt chc nng giao din giao tip tun t m rng. Ch giao din smart card c th c la chn bng cch thit lp cc thanh ghi cn thit. 12.7.1 Kt ni mu Hnh 12.21 cho thy mt kt ni mu gia smart card v vi iu khin ny. Nh trong hnh, vi iu khin ny giao tip vi IC card thng qua mt ng truyn n, ni gia chn TxD, RxD v ko ng truyn d liu ln Vcc thng qua mt in tr. Set cc bit RE v TE ln 1 v khng ni kt vi IC card s cho php ng vic truyn nhn t kim tra. cung cp xung clock pht ra t SCI cho IC card, ta ni chn SCK vo chn CLK ca IC card. Mt tn hiu reset c th c cung cp thng qua cng xut ca vi iu khin ny.
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Hnh 12.21 Kt ni chn cho giao din smart card 12.7.2 nh dng d liu (ngoi tr trng hp ang trong ch truyn khi) Hnh 12.22 cho thy nh dng truyn d liu trong ch giao tip smart card. Mt frame cha d liu 8 bit v 1 bit parity trong ch bt ng b. Trong sut qu trnh truyn, t nht 2 etu (elementary time unit: thi gian cn truyn 1 bit) cn c xem l thi gian m bo sau khi truyn xong bit parity v trc lc bt u frame tip theo. Nu c mt li parity xy ra trong qu trnh nhn, mt tn hiu li thp s c xut ra trong 1 etu sau 10.5 etu k t khi truyn bit u tin. Nu c mt tn hiu li c ly mu trong qu trnh truyn, d liu tng t s c t ng truyn li sau t nht 2 etu.
Hnh 12.22 nh dng d liu trong Ch giao din smart card giao tip vi IC card bng quy c thun hay quy c nghch, ta theo cc th tc sau.
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Hnh 12.23 Quy c thun (SDIR = SINV = O/E = 0) Vi quy c thun, mc logic 1 v 0 tng ng vi trng thi Z v A, v d liu truyn i vi bit LSB u tin, nh trong hnh 12.23. V th, d liu trong k t u tin trong hnh l H3B. Khi cn dng quy c thun, ghi 0 vo bit SINV v SDIR trong SCMR. Ghi 0 vo bit O/E trong SMR s dng parity chn theo chun ca smart card.
Hnh 12.24 Quy c nghch (SDIR = SINV = O/E = 1) Vi quy c nghch, mc logic 1 v 0 tng ng vi trng thi A v Z, d liu c truyn vi bit MSB u tin, nh trong hnh 12.24. V vy, d liu vi k t u tin trong hnh l H3F. Khi cn dng quy c nghch, ghi 1 vo bit SDIR v SINV trong SCMR. Bit parity mc logic 0 to ra parity chn theo chun ca smart card, v tng ng vi mc Z. V bit SNIV ca vi iu khin ny ch o cc bit d liu t D7 ti D0, ta ghi 1 vo bit O/E trong SMR o bit parity trong c hai chiu truyn v nhn. 12.7.3 Ch truyn khi Ch truyn khi khc bit vi ch giao din smart card trong cc trng hp sau. Ngay c khi c mt li parity xy ra trong qu trnh nhn, khng c mt tn hiu li no c xut ra ngoi. V bit PER trong SSR c lp bi vic pht hin li, ta phi xa bit PER trc khi nhn bit parity ca frame tip theo. Trong qu trnh truyn, cn t nht 1 etu lm thi gian bo m sau khi kt thc bit parity v trc khi bt u frame tip theo. Bi v d liu ging nhau s khng c truyn li trong qu trnh truyn, c TEND cn c set ln 1 sau khi qu trnh truyn bt u c 11.5 etu. Mc d c ERS trong ch truyn khi hin th trng thi tn hiu li ging nh ch giao din smart card bnh thng, c ny s lun c c l 0 bi v khng c tn hiu li no c truyn. 12.7.4 nh thi ly mu d liu nhn v Reception Margin Ch c clock ni c to bi b pht tc baud trn chip l c th c s dng nh mt clock truyn trong ch giao din smart card. Trong ch ny, SCI c th hot ng da trn 1 clock c bn vi tn s gp 32, 64, 372, hoc 256 ln tc bit da vo thit lp ca cc bit BCP1 v BCP0 (tn s lun bng 16 ln tc bit trong ch bt ng b bnh thng). Khi nhn, cnh xung ca bit khi ng c ly mu da vo clock c bn thc hin qu trnh ng b ni. D liu nhn c ly mu cc cnh ln th 16, 32, 186, hay 128 ca clock c bn, v th n c th ci gia cc bit nh trong hnh 12.25. Reception margin y c xc nh bi cng thc sau.
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M: Reception margin (%) N: T l clock trn tc bit (N = 32, 64, 372, 256) D: Chu k thc hin nhim v ca clock (D = 0 to 1.0) L: di frame (L = 10) F: Gi tr tuyt i lch tn s clock Gi s F = 0, D = 0.5, v N = 372 trong cng thc trn, reception margin c xc nh bi cng thc sau.
Hnh 12.25 nh thi ly mu d liu nhn trong Ch giao din smart card (Khi tn s clock gp 372 ln tc bit) 12.7.5 Khi ng Trc khi truyn nhn d liu, ta khi to SCI theo cc bc sau. Vic khi to l cn thit trc khi chuyn t truyn sang nhn v ngc li. 1. Xa bit TE v RE trong SCR. 2. Set bit ICR cho chn tng ng ln 1. 3. Xa cc c ERS, PER v ORER. 4. Thit lp cc bit GM, BLK, O/E, BCP1, BCP0, CKS1, CKS0 trong SMR cho thch hp. ng thi set bit PE ln 1. 5. Thit lp cc bit SMIF, SDIR v SINV trong SCMR cho thch hp Khi DDR tng ng vi chn TxD c xa, chn TxD v RxD c chuyn t chn port sang chn SCI, t cc chn ny vo trng thi tr khng cao. 6. Thit lp gi tr tng ng vi tc bit vo BRR.
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7. Thit lp cc bit CKE1 v CKE0 trong SCR cho thch hp. Xa cc bit TIE, RIE, TE, RE, MPIE, TEIE v 0 cng lc. Khi bit CKE0 bng 1, chn SCK s cho php xut xung clock. 8. Thit lp cc bit TIE, RIE, TE v RE trong SCR cho thch hp sau khi ch t nht 1 khong 1 bit. Set bit TE v RE ln 1 cng lc s b cm, tr trng hp ang t chn on. chuyn t nhn sang truyn, trc tin cn chc chn rng vic nhn hon thnh, sau ta khi to li SCI. Cui qu trnh khi to, RE v TE cn c thit lp l 0 v 1. Kt thc nhn c th c xc minh bi vic c cc c RDRF, PER hay ORER. chuyn t truyn sang nhn, trc tin phi xc minh vic truyn hon thnh, sau khi to li SCI. Cui qu trnh khi to, bit TE v RE cn phi c gn gi tr 0 v 1. Kt thc truyn c th c xc minh bi vic c c TEND. 12.7.6 Qu trnh truyn d liu (Tr khi trong Ch truyn khi) Qu trnh truyn d liu trong ch giao din smart card khc so vi ch giao din giao tip tun t thng thng, trong mt tn hiu li s c ly mu v d liu c th c truyn li. Hnh 12.26 cho thy d liu c truyn li trong qu trnh truyn. 1. Nu c 1 tn hiu li t lc kt thc qu trnh nhn c ly mu sau khi 1 frame d liu c truyn, bit ERS trong SSR c set ln 1. Ti y, mt yu cu ngt qung ERI s c pht ra nu bit RIE trong SCR bng 1. Xa bit ERS trc khi bit parity tip theo c ly mu. 2. Vi frame c tn hiu li khi nhn, bit TEND trong SSR s khng c set ln 1. D liu c truyn li t TDR sang TSR thng qua mt qu trnh truyn li d liu mt cch t ng. 3. Nu c mt tn hiu li c tr v t lc kt thc nhn, bit RES trong SSR c set ln 1. 4. Trong trng hp ny, mt frame d liu c xc nh xem c c truyn i (hoc truyn li) hay khng, v bit TEND trong SSR c set l 1. Ti y, mt yu cu ngt qung TXI nu bit TIE trong SCR bng 1. Ghi d liu truyn vo TDR s bt u vic truyn d liu tip theo. Hnh 12.28 cho thy mt lu mu cho vic truyn. Tt c cc bc x l u c t ng thc thi thng qua vic s dng mt ngt qung TXI kch hot DTC v DMAC. Trong ch qu trnh truyn, bit TEND v TDRE trong SSR s c set ln 1 ng thi, v th s c mt ngt qung TXI pht ra mi khi bit TIE trong SCR c set ln 1. Ngt qung ny s kch hot DTC/DMAC, do s cho php truyn d liu nu ngt qung TXI c chn lm ngun kch hot DTC/DMAC. C TDRE v TEND c xa t ng khi truyn d liu bi DTC/DMAC. Nu c mt li xy ra, SCI s t ng truyn li d liu b li. Trong qu trnh truyn li, TEND vn gi gi tr 0, nn n khng kch hot DTC/DMAC. Do vy, SCI v DTC/DMAC t ng truyn mt s lng byte nht nh, bao gm nhng byte phi truyn li trong trng hp c li xy ra. Tuy nhin, c ERS s khng c xa t ng; m phi c xa
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trc khi set bit RIE ln 1 cho php ngt qung ERI c to ra khi c li pht sinh. Khi truyn nhn d liu bng DTC/DMAC, cn phi cho php DTC/DMAC c u tin cao thit lp SCI. thit lp cho DTC/DMAC, xem phn 7, B iu khin DMA (DMAC) v phn 8, B iu khin truyn d liu (DTC).
Hnh 12.26 Hot ng truyn li d liu trong ch truyn SCI Ch rng c TEND c lp ti thi im khc vi khi lp bit GM trong SMR. Hnh 12.27 din t vic nh thi lp bit TEND.
Ch thch: Ds: Bit khi ng D0-D7: Bit d liu Dp: Bit parity DE: Tn hiu li Hnh 12.27 nh thi lp c TEND trong qu trnh truyn
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Hnh 12.28 Lu mu qu trnh truyn 12.7.7 Qu trnh nhn d liu (Tr khi trong Ch truyn khi) Qu trnh nhn d liu trong ch giao din smart card ging vi trong ch giao din giao tip tun t thng thng. Hnh 12.29 cho thy vic truyn li d liu trong qu trnh truyn. 1. Nu c mt li parity c pht hin trong qu trnh truyn, bit PER trong SSR s c lp ln 1. Ti y, mt yu cu ngt qung s c pht ra nu bit RIE trong SCR l 1. Xa bit PER trc khi bit parity tip theo c ly mu. 2. Vi frame c li parity, bit RDRF trong SSR s khng c set ln 1. 3. Nu khng c li parity no c pht hin, bit PER trong SSR s khng c set ln 1. 4. Trong trng hp ny, d liu s c coi l c nhn thnh cng, v bit RDRF trong SSR c set ln 1. y, mt ngt qung RXI s c pht ra
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nu bit RIE trong SCR c set ln 1. Hnh 12.30 cho thy mt lu mu cho qu trnh nhn. Tt c cc bc u c th lm t ng nh s dng ngt qung RXI kch hot DTC/DMAC. Trong qu trnh nhn, set bit RIE ln 1 s cho php ngt qung RXI nu c RDRF bng 1. Kch hot DTC/DMAC bi mt ngt qung RXI s cho php truyn d liu nhn nu RXI c thit lp lm ngun kch hot DTC/DMAC. Nu c mt li xy ra trong qu trnh nhn, ngha l, mt trong 2 c ORER hay PER c set ln 1, mt ngt qung li truyn nhn (ERI) s c pht ra v c li phi c xa. Nu c 1 li xy ra, DTC/DMAC s khng c kch hot v d liu nhn s b b qua, v th, s byte d liu nhn trong DTC/DMAC s c truyn i. Ngay c khi c 1 li parity xy ra, v bit PER bng 1 trong qu trnh nhn, d liu nhn vn c truyn vo RDR, v vy cho php d liu c th c c. Ch : V hot ng ca ch truyn khi, xem phn 12.4, Hot ng trong ch bt ng b.
Hnh 12.29 Hot ng truyn li d liu trong ch nhn SCI
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Hnh 12.30 Lu mu qu trnh nhn 12.7.8 iu khin xut clock Xut clock c th c c nh bng cc bit CKE1 v CKE0 trong SCR khi bit GM trong SMR bng 1. c bit, chiu di ti thiu ca xung clock c th c xc nh. Hnh 12.31 cho thy mt v d ca vic nh thi c nh xut clock khi bit CKE0 c iu khin vi GM = 1 v CKE1 = 0.
Hnh 12.31 nh thi c nh xut clock Ti thi im bt ngun v chuyn ra/vo ch standby phn mm, s dng th tc sau bo m mt chu k clock thc hin nhim v thch hp. Ti thi im bt ngun m bo mt chu k clock thc hin nhim v thch hp ngay khi bt ngun, ta dng th tc sau. 1. u tin, cng nhp c cho php trng thi Hi-Z. c nh mc cao, ta s dng mt in tr ko ln hoc ko xung.
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2. C nh chn SCK xut (bng cch dng bit CKE1 trong SCR). 3. Thit lp SMR v SCMR cho php ch giao din smart card. Set bit CKE0 trong SCR ln 1 bt u xut clock. Ti thi im chuyn ch o Chuyn t ch giao din smart card sang ch standby phn mm 1. Thit lp thanh ghi DR v DDR tng ng vi chn SCK xut ra mt trng thi c nh trong ch standby phn mm. 2. Ghi 0 vo bit TE v RE trong SCR dng qu trnh truyn/nhn. ng thi, set bit CKE1 xut ra mt trng thi c nh trong ch standby phn mm. 3. Ghi 0 vo bit CKE0 trng SCR dng clock. 4. Ch mt chu k ca clock tun t. Trong khi , clock xut s c c nh khi chu k thc hin nhim v vn cn. 5. Thc hin vic chuyn i ch . o Chuyn t ch standby phn mm sang ch giao din smart card 1. Xa ch standby phn mm. 2Ghi 1 vo bit CKE0 trong SCR bt u xut clock. Mt tn hiu clock vi chu k thc hin nhim v thch hp s c pht ra.
Hnh 12.32 Dng clock v th tc restart
12.8 Ngun ngt qung

12.8.1 Ngt qung trong Ch giao din giao tip tun t bnh thng Bng 12.12 cho thy ngun ngt qung trong ch giao din giao tip tun t bnh thng. Mt vector ngt qung khc s c gn vo mt ngun ngt qung, v tng ngun ngt qung ring bit s c cho php/cm thng qua iu chnh cc bit trong SCR. Khi c TDRE trong SSR c set ln 1, mt yu cu ngt qung TXI c pht ra. Khi c TEND trong SSR c set ln 1, mt yu cu ngt qung TEI c pht ra. Mt ngt qung TXI c th kch hot DTC/DMAC cho php truyn d liu. C TDRE c xa t ng khi truyn d liu bi DTC/DMAC. Khi c RDRF trong SSR c set ln 1, mt yu cu ngt qung RXI c pht ra. Khi ORER, PER, hay FER trong SSR c set ln 1, mt yu cu ngt qung ERI
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c pht ra. Mt ngt qung RXI c th c kch hot bi DTC/DMAC cho php truyn d liu. C RDRF c t ng xa khi truyn d liu bi DTC/DMAC. Mt ngt qung TEI c yu cu khi c c TEND ln bit TEIE u bng 1. Nu c 1 ngt qung TEI v 1 ngt qung TXI cng xy ra ng thi, ngt qung TXI s c u tin cao hn. Tuy nhin, cn phi ch rng nu c TDRE v TEND c xa ng thi bi chng trnh x l ngt qung TXI, SCI khng th nhy vo chng trnh x l ngt qung TEI sau . Bng 12.12 Ngun ngt qung SCI Tn ERI RXI TXI TEI Ngun ngt qung Li nhn y d liu nhn Ht d liu truyn Li truyn C ngt qung ORER,FER,P ER RDRF TDRE TEND Kch hot DTC Khng th C th C th Khng th Kch hot DMAC Khng th C th C th Khng th Thp u tin Cao
12.8.2 Ngt qung trong Ch giao din smart card Bng 12.13 cho thy ngun ngt qung trong ch giao din smart card. Mt yu cu ngt qung kt thc truyn (TEI) khng th c s dng trong ch ny. Bng 12.13 Ngun ngt qung SCI T n Ngun ngt qung C ngt qung ORER,PER,E RS RDRF TDRE Kch hot DTC Khng th Kch hot DMAC Khng th u tin Cao
ERI Li nhn hoc pht hin tn hiu li RX I TX I y d liu nhn Ht d liu truyn
C th C th
C th C th Thp
Truyn nhn d liu s dng DTC/DMAC vn c cho php trong ch giao din smart card, ging nh trong ch SCI bnh thng. Trong qu trnh truyn, c TEND v TDRE trong SSR c set ln 1 ng thi, v vy s pht ra mt ngt qung TXI. Nu ngt qung TXI c chn lm ngun kch hot DTC/DMAC, DTC/DMAC s c kch hot truyn d liu. C TDRE v TEND sau s c t ng xa khi DTC/DMAC truyn d liu. Nu c 1 li xy ra, SCI t ng truyn
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li d liu tng t. Trong qu trnh truyn li, c TEND vn gi gi tr 0, do khng kch hot DTC/DMAC. V vy, SCI v DTC/DMAC t ng truyn s byte, k c byte c truyn li trong trng hp c li xy ra. Tuy nhin, c ERS trong SSR, c bo li, s khng c xa t ng; c ERS cn phi c xa trc khi set bit RIE trong SCR cho php mt ngt qung ERI c pht ra khi c li. Khi truyn nhn d liu s dng DTC/DMAC, cn phi chc chn cho php DTC/DMAC thit lp SCI. chnh thit lp cho DTC/DMAC, xem phn 7 v phn 8. Trong qu trnh nhn, mt ngt qung RXI c pht ra khi c RDRF trong SSR bng 1. Nu ngt qung RXI c chn lm ngun kch hot DTC/DMAC, DTC/DMAC s c kch hot truyn d liu. C RDRF s c xa t ng khi DTC/DMAC truyn d liu. Nu c li xy ra, c RDRF s khng c set nhng c li s c set. V vy, DTC/DMAC s khng b kch hot v mt yu cu ngt qung s c pht ti CPU; c li cn c xa.
12.9 Ch s dng
12.9.1 Thit lp ch dng module Hot ng ca SCI c th c cho php/xa s dng thanh ghi iu khin dng module. Thit lp ban u lm cho hot ng ca SCI b dng. Truy cp thanh ghi c cho php khi xa ch dng module. bit thm chi tit, xem phn 19, Cc ch power-down. 12.9.2 Pht hin break v x l Khi pht hin c 1 li frame, mt break c th c pht hin bng cch c trc tip gi tr chn RxD. Trong mt break, gi tr nhp t chn RxD u l 0, v c FER s c set, c PER cng c th c set. Ch rng, v SCI tip tc qu trnh nhn ngay c khi nhn c 1 break, v ngay c khi c FER b xa, n cng c th c set ln 1 tr li. 12.9.3 Trng thi mark v pht hin break Khi bit TE bng 0, chn TxD c dng nh cng I/O, hng (nhp hay xut) v mc ca n s c xc nh bi DR v DDR. N c th c dng set chn TxD vo trng thi mark (mc cao) hoc gi mt break trong qu trnh truyn d liu tun t. sa cha giao tip trong trng thi mark (trng thi 1) cho ti khi TE c set ln 1, ta set c DR v DDR l 1. V bit TE c xa trong thi im ny, chn TxD tr thnh cng I/O, v 1 c xut t TxD. gi 1 break trong qu trnh truyn tun t, u tin ta set DDR l 1 v DR l 0, sau xa bit TE. Khi bit TE c xa, b truyn s c khi ng bt k trng thi truyn hin ti, chn TxD tr thnh cng I/O v 0 c xut ra t TxD. 12.9.4 C li nhn v Hot ng truyn (Ch trong ch ng b clock) Qu trnh truyn khng th c khi ng khi c mt c li nhn (ORER, FER hay RER) bng 1, ngay c khi c TDRE bng 0. Cn chc chn rng cc c trn
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c xa trc khi bt u qu trnh truyn. Ch rng c li khng th xa c khi bit RE bng 0. 12.9.5 Mi quan h gia Ghi vo TDR v c TDRE C TDRE trong SSR l mt c trng thi cho bit d liu truyn c chuyn t TDR sang TSR cha. Khi SCI chuyn d liu t TDR sang TSR, c TDRE c set ln 1. D liu c th c ghi vo TDR bt chp trng thi c TDRE. Tuy nhin, nu d liu mi c ghi vo TDR khi c TDRE bng 0, d liu c lc y cha c chuyn ht vo TSR, v ta s c nguy c b mt d liu. V vy, cn chc rng d liu truyn c ghi vo TDR sau khi bit c c TDRE bng 1. 12.9.6 Hn ch ca vic s dng DTC/DMAC Khi ngun clock ngoi c s dng lm clock ng b, ta cn cp nht TDR bng DTC/DMAC v ch t nht 5 chu k clock trc khi cho php clock truyn c nhp. Nu clock truyn c nhp vo trong vng 4 chu k sau khi TDR c chnh sa, SCI c th b li (hnh 12.33). Khi s dng DTC/DMAC c RDR, cn chc rng thit lp ngt qung ngng nhn (RXI) lm ngun kch hot DMAC.
Ch : Khi clock ngoi c cung cp, t > 4 chu k
Hnh 12.33 Qu trnh truyn mu s dng DTC/DMAC trong Ch ng b clock 12.9.7 Hot ng ca SCI trong qu trnh chuyn ch Qu trnh truyn: Trc khi thc hin vic chuyn t ch dng module hoc ch standby phn mm, ta dng hot ng truyn (TE = TIE = TEIE = 0). TSR, TDR, v SSR c reset. Trng thi cc chn xut trong ch dng module hay ch standby phn mm ty thuc vo thit lp cng, v cc chn ny xut ra tn hiu mc cao sau khi ch b hy. Nu vc chuyn xy ra trong qu trnh truyn d liu, d liu c truyn s khng xc nh. truyn d liu trong cng ch truyn sau khi ch b hy, set li bit TE, c SSR, ghi vo TDR, xa TDRE v bt u truyn. truyn d liu trong ch truyn khc, ta phi khi to SCI trc.
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Hnh 12.34 cho thy lu mu ca vic chuyn ch trong qu trnh truyn. Hnh 12.34 v 12.36 cho thy trng thi cc chn trong qu trnh chuyn i. Trc khi chuyn i t ch truyn s dng DTC sang ch dng module hay ch standby phn mm, ta phi dng tt c cc hot ng truyn (TE = TIE = TEIE = 0). Set bit TE v TIE ln 1 sau khi hy ch s set c TXI bt u truyn bng DTC. Qu trnh nhn: Trc khi chuyn sang ch dng module hay ch standby phn mm, ta phi dng mi hot ng nhn (RE = 0). RSR, RDR v SSR s c reset. Nu vic chuyn ch xy ra trong qu trnh nhn, d liu c nhn s khng cn gi tr. nhn d liu trong cng ch nhn sau khi hy ch , set bit RE ln 1 v bt u nhn. nhn d liu trong ch khc, ta phi khi to SCI trc. Hnh 12.37 cho thy lu mu ca vic chuyn ch trong qu trnh nhn.
Ch thch [1] D liu c truyn b mt trn ng. D liu c th c truyn bnh thng t CPU bng cch set bit TE ln 1, c SSR, ghi vo TDR, v xa bit TDRE sau khi xa ch standby phn mm; tuy nhin, nu DTC c kch hot, d liu cn li trong RAM ca DTC s c truyn khi c hai bit TE v TIE bng 1. [2] Xa bit TIE v TEIE khi chng bng 1 [3] Ch xa module cng nm trong y
Hnh 12.34 Lu mu vic chuyn ch trong qu trnh truyn
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Hnh 12.35 Trng thi chn port trong qu trnh chuyn (clock ni, truyn bt ng b)
Ch : * Khi to trong ch standby phn mm
Hnh 12.36 Trng thi chn port trong qu trnh chuyn (Clock ni, truyn ng b clock)
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Ch thch [1] D liu c nhn khng hp l [2] Ch dng module cng nm trong y
Hnh 12.37 Lu mu vic chuyn ch trong qu trnh nhn
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Chng 13 B giao tip tun t ng b (SSU)

B vi iu khin ny c 3 knh SSU ring bit. SSU c hai ch master v slave. ch master, vi iu khin s xut clock cho hot ng giao tip tun t ng b. ch slave, clock c nhp vo t mt thit b ngoi phc v cho hot ng giao tip tun t ng b. Giao tip tun t ng b c th c thc thi bi cc thit b vi cc clock khc cc v pha vi nhau. Hnh 13.1 cho thy s khi ca SSU.
13.1 c im
La chn gia ch SSU v ch ng b clock La chn gia ch master v ch slave La chn gia ch tiu chun v ch hai chiu Giao tip tun t ng b vi nhiu thit b vi cc clock khc cc v pha La chn gia cc di d liu truyn nhn 8/16/32 bit C th giao tip full-duplex C thm thanh ghi dch, cho php truyn nhn c thc hin ng thi. Giao tip tun t lin tc La chn gia truyn bit LSB trc hoc bit MSB trc. La chn gia cc ngun clock P/4, P/8, P/16, P/32, P/64, P/128, P/256, hoc mt clock ngoi Nm ngun ngt qung Kt thc truyn, Rng thanh ghi d liu truyn, y d liu nhn, li overrun, v li xung t Ch dng module c th c thit lp* Ch : * Ch dng module c lu s dng. bit thm chi tit, xem phn 13.6.2. Hnh 13.1 cho thy s khi ca SSU.
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Ch thch: SSCHR: SSCHL: SSCR2: SSMR: SSER: Thanh ghi iu khin SS cao Thanh ghi iu khin SS thp Thanh ghi iu khin SS 2 Thanh ghi ch SS Thanh ghi cho php SS
SSTDR0 ti SSTDR3: Thanh ghi truyn d liu SS t 0 ti 3 SSRDR0 ti SSRDR3: Thanh ghi nhn d liu SS t 0 ti 3 SSTRSR: Thanh ghi dch d liu
Hnh 13.1
S khi ca SSU
13.2 Cc chn xut nhp

Bng 13.1 cho thy cu hnh chn ca SSU Knh 0 Vit tt SSCK0 SSI0 SSO0 SCS0 1 SSCK1 SSI1 I/O I/O I/O I/O I/O I/O I/O Chc nng Clock nhp/xut SSU knh 0 D liu nhp/xut SSU knh 0 D liu nhp/xut SSU knh 0 Chip select SSU knh 0 Clock nhp/xut SSU knh 1 D liu nhp/xut SSU knh 1
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SSO1 SCS1 2 SSCK2 SSI2 SSO2 SCS2
I/O I/O I/O I/O I/O I/O
D liu nhp/xut SSU knh 1 Chip select SSU knh 1 Clock nhp/xut SSU knh 2 D liu nhp/xut SSU knh 2 D liu nhp/xut SSU knh 2 Chip select SSU knh 2
13.3 M t thanh ghi

SSU c cc thanh ghi sau (1) Knh 0 Thanh ghi iu khin SS H_0 (SSCRH_0) Thanh ghi iu khin SS L_0 (SSCRL_0) Thanh ghi ch SS_0 (SSMR_0) Thanh ghi cho php SS_0 (SSER_0) Thanh ghi trng thi SS_0 (SSSR_0) Thanh ghi iu khin SS 2_0 (SSCR2_0) Thanh ghi d liu truyn 0_0 (SSTDR0_0) Thanh ghi d liu truyn 1_0 (SSTDR1_0) Thanh ghi d liu truyn 2_0 (SSTDR2_0) Thanh ghi d liu truyn 3_0 (SSTDR3_0) Thanh ghi d liu nhn 0_0 (SSRDR0_0) Thanh ghi d liu nhn 1_0 (SSRDR1_0) Thanh ghi d liu nhn 2_0 (SSRDR2_0) Thanh ghi d liu nhn 3_0 (SSRDR3_0) Thanh ghi dch SS_0 (SSTRSR_0) (2) Knh 1 Thanh ghi iu khin SS H_1 (SSCRH_1) Thanh ghi iu khin SS L_1 (SSCRL_1) Thanh ghi ch SS_1 (SSMR_1) Thanh ghi cho php SS_1 (SSER_1) Thanh ghi trng thi SS_1 (SSSR_1) Thanh ghi iu khin SS 2_1 (SSCR2_1) Thanh ghi d liu truyn 0_1 (SSTDR0_1)
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Thanh ghi d liu truyn 1_1 (SSTDR1_1) Thanh ghi d liu truyn 2_1 (SSTDR2_1) Thanh ghi d liu truyn 3_1 (SSTDR3_1) Thanh ghi d liu nhn 0_1 (SSRDR0_1) Thanh ghi d liu nhn 1_1 (SSRDR1_1) Thanh ghi d liu nhn 2_1 (SSRDR2_1) Thanh ghi d liu nhn 3_1 (SSRDR3_1) Thanh ghi dch SS_1 (SSTRSR_1) (3) Knh 2 Thanh ghi iu khin SS H_2 (SSCRH_2) Thanh ghi iu khin SS L_2 (SSCRL_2) Thanh ghi ch SS_2 (SSMR_2) Thanh ghi cho php SS_2 (SSER_2) Thanh ghi trng thi SS_2 (SSSR_2) Thanh ghi iu khin SS 2_2 (SSCR2_2) Thanh ghi d liu truyn 0_2 (SSTDR0_2) Thanh ghi d liu truyn 1_2 (SSTDR1_2) Thanh ghi d liu truyn 2_2 (SSTDR2_2) Thanh ghi d liu truyn 3_2 (SSTDR3_2) Thanh ghi d liu nhn 0_2 (SSRDR0_2) Thanh ghi d liu nhn 1_2 (SSRDR1_2) Thanh ghi d liu nhn 2_2 (SSRDR2_2) Thanh ghi d liu nhn 3_2 (SSRDR3_2) Thanh ghi dch SS_2 (SSTRSR_2) 13.3.1 Thanh ghi iu khin SS H (SSCRH) SSCRH la chn thit b master/slave, cho php ch hai chiu, chn gi tr xut chn SSO, chn chn SSCK v chn chn SCS.
Bit
Tn bit
Gi tr khi
R/ W
c t
430
ng 7 MSS 0 R/W La chn thit b master/slave Ch ra thit b ny ang c s dng trong ch master hay slave. Khi ch master c chn, clock truyn c xut ra t chn SSCK. Khi bit CE trong SSSR c set, bit ny s t ng c xa. 0: Chn ch slave. 1: Chn ch master. 6 BIDE 0 R/W Cho php ch hai chiu Cho php c chn nhp d liu tun t v chn xut hay ch mt trong hai c s dng. Tuy nhin, truyn v nhn s khng c thc hin ng thi khi ch hai chiu c chn. bit thm chi tit, xem phn 13.4.3, Mi quan h gia cc chn Nhp/Xut d liu v Thanh ghi Dch. 0: Ch chun (hai chn c s dng cho nhp v xut d liu) 1: Ch hai chiu (mt chn c s dng cho nhp v xut d liu) 5 -0 R/W Bit Khng dng. Bit ny lun c c bng 0, v gi tr ghi vo n cng nn l 0. 4 SOL 0 R/W La chn gi tr xut d liu tun t Gi tr xut d liu tun t s gi nguyn mc ca bit cui cng sau khi hon thnh vic truyn. Mc xut trc hoc sau khi truyn c th c ch nh bi vic thit lp bit ny. Khi ch nh mc xut, s dng cu lnh MOV sau khi xa bit SOLP. V vic ghi vo bit ny trong qu trnh truyn d liu s gy ra li, ta khng nn thay i bit ny. 0: Mc xut d liu tun t l mc thp. 1: Mc xut d liu tun t l mc cao. 3 SOLP 1 R/W Chng ghi bit SOL Khi cn thay i mc xut ca d liu tun t, ta ch c th set hoc xa bit SOL sau khi xa bit
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SOLP bng cu lnh MOV. 0: Mc xut c th thay i bi bit SOL 1: Mc xut khng th thay i bi bit SOL. Bit ny lun c c l 1. 2 SCKS 0 R/W La chn hot ng chn SSCK La chn chc nng cho chn SSCK nh mt port hoc mt chn clock tun t. Khi chn SSCK c s dng nh mt chn clock tun t, bit ny cn c set ln 1. 0: Hot ng nh mt port xut nhp. 1: Hot ng nh mt clock tun t. 1 0 CSS1 CSS0 0 0 R/W La chn hot ng chn SCS R/W La chn chc nng cho chn SCS nh mt port hoc xut/nhp SCS. Tuy nhin, khi MSS = 0, chn SCS hot ng nh mt chn nhp bt k thit lp ca cc bit CSS1 v CSS0. 00: Cng xut nhp 01: Hot ng nh chn nhp SCS 10: Hot ng nh chn xut/nhp t ng SCS (hot ng nh chn nhp SCS trc v sau khi truyn, v xut ra gi tr mc thp trong qu trnh truyn) 11: Hot ng nh chn xut t ng SCS (xut ra gi tr mc cao trc v sau khi truyn v xut mc thp trong sut qu trnh truyn) 13.3.2 Thanh ghi iu khin SS L (SSCRL) SSCRL la chn ch hot ng, reset mm, v chiu di d liu truyn/nhn.
Bit
Tn bit --
Gi tr khi ng 0
R/ W R/W Khng dng
c t
Bit ny lun c c l 0. Gi tr ghi vo cng nn l 0.
432
SSU MS
R/W Chn ch truyn l ch SSU hoc ch ng b clock 0: Ch SSU 1: Ch ng b clock
SRES
R/W Reset mm Set bit ny ln 1 s reset sequencer ni ca SSU. Sau , bit ny s t ng c xa. Cc bit ORER, TEND, TDRE, RDRF, CE trong SSSR v TE, RE trong SSER cng c khi to li. Gi tr ca cc bit khc trong cc thanh ghi SSU s c gi li. dng qu trnh truyn, set bit ny ln 1 reset sequencer ni ca SSU
4,3, -2 1 0
R/W Khng dng Cc bit ny lun c c l 0. Gi tr ghi vo cng nn l 0. R/W Chn chiu di d liu truyn nhn R/W 00: 8 bit 01: 16 bit 10: 32 bit 11: Khng c thit lp
DATS 0 1 0 DATS 0
13.3.3 Thanh ghi ch SS (SSMR) SSMR la chn kiu truyn bit LSB hay MSB trc, cc clock, pha clock, v tc clock ca giao tip tun t ng b.
Bit
Tn bit MLS
Gi tr khi ng 0
R/W
M t
R/W La chn ch truyn bit MBS trc hoc bit LSB trc. 0: bit LSB trc 1: bit MSB trc
CPOS 0
R/W La chn cc cho clock SSCK. 0: Xut ra mc cao ch ch, v mc thp

433
ch hot ng 0: Xut ra mc thp ch ch, v mc cao ch hot ng 5 CPHS 0 R/W La chn pha cho clock SSCK (Ch trong ch SSU) 0: D liu thay i cnh u tin 1: D liu c ci cnh u tin. 4, 3 -0 R/W Khng dng Cc bit ny lun c c l 0. Gi tr ghi vo cng nn l 0. 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W Chn tc cho clock (prescaler division rate) khi c mt clock ni c chn. 000: Khng dng 001: P/4 010: P/8 011: P/16 100: P/32 101: P/64 110: P/128 111: P/256 13.3.4 Thanh ghi cho php SS (SSER) SSER thc hin iu khin vic truyn nhn ca qu trnh giao tip tun t ng b v cho php ngt qung.
Bit
Tn bit TE RE
Gi tr khi ng 0 0 0
R/W
c t
7 6
R/W Cho php truyn khi bit ny bng 1 R/W Cho php nhn khi bit ny bng 1 R/W Khng dng Cc bit ny lun c c l 0. Gi tr ghi vo cng nn l 0.
434
5, 4 --
TEIE
R/W Cho php ngt qung kt thc truyn Khi bit ny bng 1, yu cu ngt qung TEI c cho php
TIE
R/W Cho php ngt qung truyn Khi bit ny bng 1, yu cu ngt qung TXI c cho php
RIE
R/W Cho php ngt qung nhn Khi bit ny bng 1, yu cu ngt qung RXI v OEI c cho php.
CEIE
R/W Cho php ngt qung li xung t Khi bit ny bng 1, yu cu ngt qung CEI c cho php.
13.3.5 Thanh ghi trng thi SS (SSSR) SSSR l mt thanh ghi c trng thi cho ngt qung.
Bit
Tn bit --
Gi tr khi ng 0
R/W
c t
R/W Khng dng. Bit ny lun c c l 0. Gi tr ghi vo cng nn l 0.
ORER 0
R/W Li overrun. Nu d liu tip theo c nhn khi RDRF = 1, mt li overrun s xy ra, lm ngng qu trnh. SSRDR lu li 1 frame d liu nhn trc khi c li overrun xy ra, v mt ht d liu nhn sau . Ghi ORER = 1, qu trnh nhn tun t s khng tip tc na, v qu trnh truyn cng vy. [iu kin set] Khi mt byte ca d liu nhn tip theo c nhn hon chnh vi RDRF = 1 [iu kin xa] Khi ghi 0 sau khi c ORER = 1
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5, 4 --
R/W Khng dng. Cc bit ny lun c c l 0. Gi tr ghi vo cng nn l 0.
TEND 1
R/W Kt thc truyn. [iu kin set] Khi bit cui cng ca d liu truyn c truyn xong, v bit TENDSTS trong SSCR2 = 0, bit TDRE = 1. Sau khi bit cui cng ca d liu truyn c truyn xong, v bit TENDSTS trong SSCR2 = 1, bit TDRE = 1. [iu kin xa] Khi ghi 0 sau khi c TEND = 1 Khi ghi d liu vo SSTDR
TDRE 1
R/W Rng thanh ghi d liu truyn. Cho bit thanh ghi SSTDR cn cha d liu truyn hay khng. [iu kin set] Khi bit TE trong SSER bng 0. Khi d liu c truyn t SSTDR sang SSTRSR v SSTDR sn sng ghi vo. [iu kin xa] Khi ghi 0 sau khi c TDRE = 1 Khi ghi d liu vo SSTDR vi TE = 1
RDRF 0
R/W y thanh ghi d liu nhn Cho bit thanh ghi SSRDR c cha d liu nhn hay khng. [iu kin set] Khi d liu nhn c truyn t SSTRSR sang SSRDR sau qu trnh nhn d liu tun t thnh cng [iu kin xa] Khi ghi 0 sau khi c RDRF = 1 Khi c d liu nhn t SSRDR
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CE
R/W Li xung t/cha hon thnh Cho thy c mt li xung t xy ra khi 0 c nhp vo chn SCS vi SSUMS = 0 (ch SSU) v MSS = 1 (ch master). Nu mc in p chn SCS thay i sang 1 vi SSUMS = 0 (Ch SSU) v MSS = 0 (ch slave), mt li khng hon thnh s xy ra v n ch ra c mt thit b master ngng qu trnh truyn. Qu trnh nhn d liu s khng tip tc khi bit CE bng 1. Qu trnh truyn cng vy. Reset sequencer ni ca SSU bng vic set bit SRES trong SSCRL ln 1 trc khi tip tc vic truyn sau khi c li khng hon thnh xy ra. [iu kin set] Khi mt mc in p thp c nhp vo chn SCS trong ch master (bit MSS = 1) Khi chn SCS chuyn sang 1 trong qu trnh truyn ch slave (bit MSS = 0) [iu kin xa] Khi ghi 0 sau khi c CE = 1
13.3.6 Thanh ghi iu khin SS 2 (SSCR2) SSCR2 l thanh ghi cho php/cm ng xut open-drain ca cc chn SSO, SSI, SSCK, SCS, la chn thi gian xc nhn cho chn SCS, nh thi xut d liu ra chn SSO, v thit lp thi gian set bit TEND.
Bit
Tn bit
Gi tr khi ng 0
R/W M t
SDOS
R/W La chn open drain cho cc chn d liu tun t La chn chn xut d liu c s dng l chn xut theo kiu CMOS hay open drain NMOS. Chn no dng xut d liu ty thuc vo thit lp ca thanh ghi. Xem thm chi tit phn 13.4.3, Mi quan h gia cc chn xut/nhp d liu v thanh ghi dch.
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0: ng xut CMOS 1: ng xut open drain NMOS 6 SSCKOS 0 R/W La chn open drain cho chn SSCK La chn chn SSCK c s dng nh l chn xut CMOS hay open drain NMOS. 0: ng xut CMOS 1: ng xut open drain NMOS 5 SCSOS 0 R/W La chn open drain cho chn SCS La chn chn SCS c s dng nh l chn xut CMOS hay open drain NMOS. 0: ng xut CMOS 1: ng xut open drain NMOS 4 TENDSTS 0 R/W Chn thi gian set bit TEND (ch c ngha trong ch SSU v ch master) 0: Set bit TEND khi bit cui cng c truyn. 1: Set bit TEND sau khi bit cui cng c truyn. 3 SCSATS 0 R/W La chn thi gian xc nhn chn SCS (ch c ngha trong ch SSU v ch master) 0: Gi tr thp nht ca tLEAD v tLAG l 1/2 x tSUcyc 1: Gi tr thp nht ca tLEAD v tLAG l 3/2 x tSUcyc 2 SSODTS 0 R/W La chn nh thi xut d liu ca chn SSO (ch c ngha trong ch SSU v ch master) 0: Khi BIDE = 0, MSS = 1, v TE = 1 hoc khi BIDE = 1, TE = 1, v RE = 0, chn SSO s xut d liu 1: Khi BIDE = 0, MSS = 1, v TE = 1 hay khi BIDE = 1, TE = 1, v RE = 0, chn SSO s xut d liu khi SCS b li xung mc in th thp. 1, 0 -0 R/W Khng dng Cc bit ny lun c c l 0. Gi tr ghi vo cng nn l 0.
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13.3.7 Thanh ghi d liu truyn SS t 0 ti 3 (SSTDR0 ti SSTDR3) SSTRD l mt thanh ghi 8 bit cha d liu truyn. Khi chiu di d liu 8 bit c chn bi cc bit DATS1 v DATS0 trong SSCRL, SSTDR0 s c hiu lc. Khi d liu 16 bit c chn, SSTDR0 v SSTDR1 c hiu lc. Khi d liu 32 bit c chn, SSTDR0 ti SSTDR3 c hiu lc. Khi SSU pht hin thy SSTRSR rng, n s chuyn d liu truyn ghi trong SSTDR vo SSTRSR v bt u qu trnh truyn tun t. Nu d liu truyn tip theo c ghi vo SSTDR trong qu trnh truyn tun t, SSU s thc hin qu trnh truyn lin tc. Mc d SSTDR lun lun c th c c hoc ghi bi CPU, DTC/DMAC, c c 1 qu trnh truyn tin cy, ta nn ghi d liu truyn vo SSTDR sau khi xc nhn bit TDRE trong SSSR bng 1.
13.3.8 Thanh ghi d liu nhn 0 ti 3 (SSRDR0 ti SSRDR3) SSRDR l mt thanh ghi 8 bit cha d liu nhn. Khi chiu di d liu 8 bit c chn (bi cc bit DATS1 v DATS0 trong SSCRL), SSRDR0 s c hiu lc. Khi d liu 16 bit c chn, SSRDR0 v SSRDR1 c hiu lc. Khi d liu 32 bit c chn, SSRDR0 ti SSRDR3 c hiu lc. Khi SSU nhn 1 byte d liu, n chuyn d liu nhn t SSTRSR vo SSRDR. Sau , SSTRSR s sn sng cho vic nhn. V SSTRSR v SSRDR hot ng nh b nh kp trong trng hp ny, hot ng nhn c th c thc thi lin tc. c SSRDR sau khi xc nhn bit RDRF trong SSSR bng 1. SSRDR l mt thanh ghi ch c, do , ta khng th dng CPU ghi vo n.
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13.3.9 Thanh ghi dch SS (SSTRSR) SSTRSR l mt thanh ghi dch dng truyn v nhn d liu. Khi d liu c truyn t SSTDR sang SSTRSR, bit 0 ca d liu truyn s l bit 0 ca gi tr SSTDR (MLS = 0: giao tip dng bit LSB trc) v l bit 7 ca SSTDR (MLS = 1: giao tip dng bit MSB trc). SSU chuyn d liu t LSB (bit 0) trong SSTRSR sang chn SSO thc thi qu trnh truyn d liu. Trong qu trnh nhn, SSU ly d liu c nhp vo t chn SSI trong SSTRSR t bit 0 (LSB). Khi 1 byte d liu c nhn, ni dung thanh ghi SSTRSR s c t ng chuyn vo SSRDR. CPU khng th truy xut trc tip thanh ghi SSTRSR.
13.4 Hot ng
13.4.1 Clock truyn Mt clock truyn c th c chn t 8 clock ni v mt clock ngoi. Khi s dng module ny, ta set bit SCKS trong SSCRH ln 1 chn chn SSCK nh mt chn clock. Khi bit MSS trong SSCRG bng 1, mt clock ni c chn v chn SSCK s c s dng lm chn xut. Khi qu trnh truyn bt u, clock (vi tc truyn c thit lp bi cc bit CKS2 ti CKS0 trong SSMR) c xut ra t chn SSCK. Khi MSS = 0, mt clock ngoi c chn v chn SSCK c dng lm chn nhp. 13.4.2 Quan h gia pha, cc ca clock v d liu Mi quan h gia pha clock, cc clock v d liu truyn ph thuc vo s kt hp ca cc bit CPOS v CPHS trong SSMR. Hnh 13.2 cho thy mi quan h . Khi SSUMS = 1, thit lp CPHS s khng cn hiu lc, thit lp ca CPOS th vn cn. Thit lp ca bit MLS trong SSMR s la chn ch giao tip bit MSB hoc LSB trc. Khi MLS = 0, d liu c truyn t LSB ti MSB, v ngc li, khi MSL = 1, d liu c truyn t MSB ti LSB.
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Hnh 13.2 Mi quan h ca cc, pha clock v d liu truyn 13.4.3 Mi quan h gia cc chn nhp/xut d liu v thanh ghi dch Mi quan h gia cc chn xut nhp v thanh ghi SSTRSR ph thuc vo thit lp ca cc bit MSS v BIDE trong SSCRH v bit SSUMS trong SSCRL. Hnh 13.3 cho thy mi quan h ny. SSU truyn d liu t chn SSO v nhn d liu t chn SSI khi hot ng vi bit BIDE = 0 v MSS = 1 (ch master, chun) (xem hnh 13.3 (1)). SSU truyn d liu t chn SSI v nhn d liu t chn SSO khi hot ng vi bit BIDE = 0 v MSS = 0 (ch slave, chun) (xem hnh 13.3(2)). SSU truyn v nhn d liu t chn SSO bt k ang ch master hay slave khi hot ng vi bit BIDE = 1 (ch hai chiu) (xem hnh 13.3 (3) v (4)). Tuy nhin, ngay c khi bit TE v RE bng 1, truyn v nhn cng khng c thc hin ng thi. Mt trong hai bit TE v RE phi c chn. SSU truyn d liu t chn SSO v nhn d liu t chn SSI khi hot ng vi bit SSUMS = 1. Chn SSCK xut clock ni khi MSS = 1 v hot ng nh mt chn nhp khi MSS = 0 (xem hnh 13.3 (5) v (6)).
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Hnh 13.3 Mi quan h gia cc chn nhp/xut d liu v thanh ghi dch 13.4.4 Cc ch giao tip v cc chc nng chn SSU la chn hot ng ca cc chn nhp/xut (SSI, SSO, SSCK v SCS) da vo cc ch giao tip v cc thit lp thanh ghi. Khi mt chn c s dng nh chn nhp, ta set bit tng ng trong thanh ghi ICR ln 1. Mi quan h gia ch giao tip v hot ng cc chn nhp/xut c th hin trong bng 13.2 ti 13.4. Bng 13.2 Cc ch giao tip v Trng thi chn ca cc chn SSI v SSO Ch giao tip Ch giao tip SSU Thit lp thanh ghi SSUM S 0 BIDE 0 MSS 0 TE 0 1 1 0 1 Ch giao tip SSU (hai chiu) 0 1 0 1 Ch giao 1 0 0 0 1 0 1 0 RE 1 0 1 1 0 1 1 0 1 0 1 Trng thi chn SSI -Xut Xut Nhp -Nhp ----Nhp SSO Nhp -Nhp -Xut Xut Nhp Xut Nhp Xut -442
tip ng b clock 1
1 0 1
0 1 1 0 1
-Nhp Nhp -Nhp
Xut Xut -Xut Xut
Ch thch: -- : Khng s dng nh mt chn SSU (c th s dng lm port nhp/xut) Bng 13.3 Cc ch giao tip v Trng thi chn ca chn SSCK Ch giao tip SSUMS Ch giao tip SSU 0 Thit lp thanh ghi MSS 0 1 Ch giao tip ng b clock 1 0 1 Ch thch: -- : Khng s dng nh mt chn SSU Bng 13.4 Cc ch giao tip v Trng thi chn ca chn SCS Ch giao tip SSUMS Ch giao tip SSU 0 Thit lp thanh ghi MSS 0 1 CSS1 x 0 0 1 1 Ch giao tip ng b 1 x x CSS0 x 0 1 0 1 x Trng thi chn SCS Nhp -Nhp T ng nhp/xut Xut -SCKS 0 1 0 1 0 1 0 1 Trng thi chn SSCK -Nhp -Xut -Nhp -Xut
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clock Ch thch: x : Khng cn quan tm -- : Khng s dng nh mt chn SSU 13.4.5 Ch SSU Trong ch SSU, giao tip d liu c thc thi thng qua 4 ng: clock (SSCK), ng nhp d liu (SSI hoc SSO), ng xut d liu (SSI hoc SSO), v ng chn chip (SCS). Thm vo , SSU h tr ch hai chiu, cho php mt chn c th va hot ng nh l chn nhp, va c th hot ng nh l chn xut. (1) Thit lp ban u trong ch SSU Hnh 13.4 cho thy mt v d ca thit lp ban u trong ch SSU. Trc khi d liu c truyn i, ta xa c 2 bit TE v RE trong SSER thit lp gi tr khi ng. Ch : Trc khi chuyn ch hot ng v nh dng giao tip, ta phi xa bit TE v RE. Mc d vic xa bit TE s set bit TDRE ln 1, vic xa bit RE s khng lm nh hng ti gi tr cc bit RDRF v ORER trong SSRDR. Cc bit ny s vn gi nguyn gi tr trc .
Ch thch: [1] Khi chn ny c s dng nh chn nhp. [2] Ch nh la chn ch master/slave, cho php ch hai chiu, la chn gi tr xut cho chn SSO, chn chn SSCK, v chn chn SCS. [3] Chn ch SSU v ch nh di d liu truyn nhn. [4] Ch nh la chn truyn bit MSB hay LSB trc, chn cc v pha clock, chn tc clock truyn. [5] Cho php/cm yu cu ngt qung ti CPU.
Hnh 13.4 V d v thit lp ban u trong ch SSU (2) Qu trnh truyn d liu Hnh 13.5 cho thy mt v d ca hot ng truyn, v hnh 13.6 cho thy lu ca qu trnh truyn d liu. Khi truyn d liu, SSU hot ng nh sau.
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Trong ch master, SSU xut ra mt clock truyn v d liu. Trong ch slave, khi mt tn hiu mc thp c nhp vo chn SCS v clock truyn c nhp vo chn SSCK, SSU s xut d liu da trn vic ng b vi clock truyn. Ghi d liu truyn vo SSTDR sau khi bit TE c set ln 1 s xa bit TDRE trong SSSR, v ni dung SSTDR c truyn vo SSTRSR. Sau , SSU set bit TDRE ln 1 v bt u truyn. Trong lc ny, nu bit TIE trong SSER bng 1, mt ngt qung TXI s xy ra. Khi 1 frame d liu c truyn vi TDRE = 0, ni dung thanh ghi SSTDR s c truyn vo SSTRSR khi ng vic truyn frame k. Khi bit th 8 ca d liu truyn c truyn i vi TDRE = 1, bit TEND trong SSSR c set ln 1 v trng thi c gi nguyn. Trong lc ny, nu bit TEIE bng 1, mt ngt qung TEI s xy ra. Sau qu trnh truyn, mc xut ca chn SSCK s c c nh l mc cao khi CPOS = 0 hay mc thp khi CPOS = 1. Khi bit ORER trong SSSR bng 1, qu trnh truyn s khng c thc thi. Do ta phi kim tra bit ORER c c xa cha trc khi truyn.
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Hnh 13.5 V d ca hot ng truyn (Ch SSU)
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Ch thch: [1] Thit lp ban u: Ch nh nh dng d liu truyn. [2] Kim tra trng thi SSU v ghi d liu truyn: Ghi d liu truyn vo SSTDR sau khi c v xc nhp bit TDRE bng 1. Bit TDRE c xa t ng v qu trnh truyn s c bt u bng vic ghi d liu vo SSTDR. [3] Th tc truyn d liu lin tc: qu trnh truyn d liu c lin tc, ta cn xc nhn bit TDRE bng 1, ngha l SSTDR sn sng ghi vo. Sau , d liu c th c ghi vo SSTDR. Bit TDRE s c xa t ng bi vic ghi d liu vo SSTDR. 4] Th tc kt thc qu trnh truyn d liu: kt thc qu trnh truyn d liu, xc nhn rng bit TEND c xa. Sau khi hon thnh vic truyn bit cui cng, ta xa bit TE v 0.
Hnh 13.6 Lu v d ca qu trnh truyn d liu (Ch SSU) (3) Qu trnh nhn d liu Hnh 13.7 cho thy mt v d ca hot ng nhn d liu, v hnh 13.8 cho thy mt lu v d ca qu trnh nhn d liu. Khi nhn d liu, SSU hot ng nh sau. Sau khi set bit RE ln 1 v c gi SSRDR, SSU bt u nhn d liu. Trong ch master, SSU xut ra mt clock v nhn d liu. Trong ch slave, khi mt tn hiu mc thp c nhp vo chn SCS v mt clock c nhp vo chn SSCK, SSU nhn d liu c ng b vi clock truyn . Khi mt frame d liu c nhn, bit RDRF trong SSSR c set ln 1 v d liu nhn c lu vo thanh ghi SSRDR. Vo lc ny, nu bit RIE trong SSER bng 1, mt ngt qung RXI s xy ra. Bit RDRF s c xa t ng sau khi c SSRDR. Khi bit RDRF bng 1 ti cnh ln th 8 ca clock truyn, bit ORER trong SSSR s c set ln 1. iu c ngha l c mt li overrun (OEI) xy ra. Vo lc ny, qu trnh nhn d liu s b dng. Khi bit ORER trong SSSR bng 1, qu trnh nhn s khng c thc thi. tip tc qu trnh nhn, ta phi xa bit ORER.
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Hnh 13.7 V d ca hot ng nhn d liu (Ch SSU)
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Ch thch: [1] Thit lp ban u: Ch nh nh dng d liu nhn. [2] Bt u qu trnh nhn: Khi SSRDR c c gi vi bit RE = 1, qu trnh nhn bt u. [3], [6] Qu trnh x l li nhn: Khi c mt li nhn xy ra, ta thc thi chng trnh x l li sau khi c bit ORER trong SSSR, sau xa bit ORER. Khi bit ORER bng 1, qu trnh truyn hay nhn u khng c tip tc. [4] tip tc qu trnh nhn n, ta phi ch mt thi gian tSUcyc trong khi c RDRF c set ln 1 v sau c d liu nhn t SSRDR. Qu trnh nhn n tip theo bt u sau khi c d liu nhn t SSRDR. [5] hon chnh qu trnh nhn: c d liu sau khi xa bit RE. Khi c SSRDRm khng xa bit RE, qu trnh nhn s tip tc.
Hnh 13.8 Lu v d ca qu trnh nhn d liu (Ch SSU) (4) Qu trnh truyn/nhn d liu Hnh 13.9 cho thy lu v d ca qu trnh truyn nhn ng thi. Qu trnh truyn nhn d liu s c thc thi kt hp gia qu trnh truyn d liu v qu trnh nhn d liu nh lit k trn. Qu trnh truyn nhn d liu c khi ng bi vic ghi d liu truyn vo SSTDR vi TE = RE = 1. Trc khi chuyn ch truyn (TE = 1) hoc ch nhn (RE = 1) sang ch truyn nhn ng thi (TE = RE = 1), ta phi xa c hai bit TE v RE. Khi bt u truyn, xc nhn cc bit TEND, RDRF v ORER u c xa, trc khi set bit TE v RE ln 1.
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Ch thch: [1] Thit lp ban u: La chn nh dng d liu truyn/nhn. [2] Kim tra trng thi SS v ghi d liu truyn: Ghi d liu truyn vo SSTDR sau khi c v xc nhn rng bit TDRE = 1. Bit TDRE s c t ng xa v qu trnh truyn nhn s khi ng bng vic ghi d liu vo SSTDR. [3] Kim tra trng thi SSU: c SSSR xc nhn bit RDRF = 1. Mt thay i ca bit RDRF (t 0 sang 1) c th c thng bo bi ngt qung RXI. [4] X l li nhn: Khi c mt li nhn xy ra, ta thc thi chng trnh x l li tng ng sau khi c bit ORER trong SSSR, sau xa bit ORER. Khi bit ORER bng 1, qu trnh truyn hay nhn u khng c tip tc. [5] Th tc truyn nhn d liu lin tc: Xc nhn bit TDRE = 1 (ngha l SSTDR sn sng ghi vo). Sau , d liu c th c ghi vo SSTDR. Bit TDRE s c xa t ng sau khi ghi d liu vo SSTDR.
Hnh 13.9 Lu v d ca qu trnh truyn nhn d liu ng thi (Ch SSU) 13.4.6 iu khin chn SCS v Arbitration Khi bit CSS1 v CSS0 trong SSCRH c ch nh l B10 v bit SSUMS trong SSCRL = 0, chn SCS hot ng nh mt ng nhp (Hi-Z) pht hin arbitration. Thi gian xc nh arbitration l thi gian set bit MSS trong SSCRH ln 1 bt u truyn v sau khi kt thc truyn. Khi c mt tn hiu mc thp c nhp vo chn SCS trong lc ny, mt li xung t s xy ra. Vo lc ny, bit CE trong SSSR = 1 v bit MSS = 0. Ch : Khi bit CE bng 1, qu trnh truyn hay nhn u khng c tip tc. Cn phi xa bit CE trc khi tip tc qu trnh truyn nhn.
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Hnh 13.10 Thi gian xc nh Arbitration (Trc khi truyn)
Hnh 13.10 Thi gian xc nh Arbitration (Sau khi kt thc truyn) 13.4.7 Ch giao tip ng b clock Trong ch giao tip ng b clock, giao tip d liu c thc hin thng qua 3 ng: clock (SSCK), ng nhp d liu (SSI), v ng xut d liu (SSO). (1) Thit lp ban u trong ch giao tip ng b clock. Hnh 13.12 cho thy 1 v d ca thit lp ban u trong ch giao tip ng b clock. Trc khi truyn d liu, ta xa c 2 bit TE v RE trong SSER thit lp gi tr khi u. Ch : Trc khi chuyn ch hot ng v nh dng giao tip, phi xa c 2 bit TE v RE. Mc d vic xa bit TE s set bit TDRE ln 1, vic xa bit RE s khng lm nh hng ti gi tr cc bit RDRF v ORER trong SSRDR. Cc bit ny s vn gi nguyn gi tr trc .
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Ch thch: [1] Khi chn ny c s dng nh mt chn nhp. [2] La chn ch master/slave v la chn chn SSCK. [3] La chn ch giao tip ng b clock v ch nh di d liu truyn nhn. [4] La chn cc clock v tc clock truyn. [5] Cho php/cm yu cu ngt qung ti CPU.
Hnh 13.12 V d ca qu trnh thit lp ban u (Ch giao tip ng b clock) (2) Qu trnh truyn d liu Hnh 13.13 cho thy mt v d ca hot ng truyn, v hnh 13.14 cho thy lu v d ca qu trnh truyn d liu. Khi truyn d liu trong ch giao tip ng b clock, SSU hot ng nh sau. Trong ch master, SSU xut ra mt clock v truyn d liu. Trong ch slave, khi mt clock truyn c nhp vo chn SSCK, SSU xut ra d liu c ng b vi clock truyn. Ghi d liu truyn vo SSTDR sau khi set bit TE s xa bit TDRE trong SSSR, v ni dung SSTDR s c truyn ti SSTRSR. Sau , SSU set bit TDRE v bt u truyn. Vo lc ny, nu bit TIE trong SSER bng 1, mt ngt qung TXI s c pht ra. Khi 1 frame d liu c truyn vi TDRE = 0, ni dung thanh ghi SSTDR s c truyn vo SSTRSR khi ng vic truyn frame k. Khi bit th 8 ca d liu truyn c truyn i vi TDRE = 1, bit TEND trong SSSR c set ln 1 v trng thi c gi nguyn. Trong lc ny, nu bit TEIE bng 1, mt ngt qung TEI s xy ra. Cn phi xa bit ORER trc khi thc thi qu trnh truyn.
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Hnh 13.13 V d ca hot ng truyn (Ch giao tip ng b clock)
Ch thch: [1] Thit lp khi u: Chn nh dng d liu truyn. [2]Kim tra trng thi SSU v ghi d liu truyn: Ghi d liu truyn vo SSTDR sau khi c v xc nhn bit TDRE bng 1. Bit TDRE c xa t ng v qu trnh truyn bt u bi vic ghi d liu vo SSTDR. [3] Th tc truyn d liu lin tc: truyn d liu lin tc, ta phi xc nhn bit TDRE bng 1, ngha l SSTDR sn sng ghi vo. Sau , d liu c th c ghi vo SSTDR. Bit TDRE c xa t ng khi ghi d liu vo SSTDR [4] Th tc kt thc truyn d liu: kt thc truyn d liu, ta xc nhn bit TEND bng 0. Sau khi truyn bit d liu cui cng, ta xa bit TE.
Hnh 13.14 Lu v d ca qu trnh truyn d liu (Ch giao tip ng b clock) (3) Qu trnh nhn d liu
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Hnh 13.15 cho thy mt v d ca hot ng nhn d liu, v hnh 13.16 cho thy lu v d ca qu trnh nhn d liu. Khi nhn d liu, SSU hot ng nh sau. Sau khi set bit RE trong SSER, SSU bt u nhn d liu. Trong ch master, SSU xut ra mt clock truyn v nhn d liu. Trong ch slave, khi mt clock truyn c nhp vo chn SSCK, SSU s nhn d liu c ng b vi clock truyn. Sau mt frame d liu c nhn, bit RDRF trong SSSR c set v d liu nhn c lu vo SSRDR. Vo lc ny, nu bit RIE c set, mt ngt qung RXI s c pht ra. Bit RDRF s c xa t ng bi vic c SSRDR. Khi bit RDRF c set ti cnh ln th 8 ca clock truyn, bit ORER s bng 1, bo hiu mt li overrun xy ra. Ti lc ny, qu trnh nhn d liu s c dng li. Khi bit ORER bng 1, qu trnh nhn s khng c tip tc. V th ta cn xa bit ORER trc khi tip tc qu trnh nhn.
Hnh 13.15 V d ca hot ng nhn d liu (Ch giao tip ng b clock)
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Ch thch: [1] Thit lp khi u: Chn nh dng d liu truyn. [2] Bt u qu trnh nhn: Khi set bit RE, qu trnh nhn bt u. [3], [5] X l li nhn: Khi c 1 li nhn xy ra, ta thc thi chng trnh x l li tng ng sau khi c bit ORER trong SSSR. Sau , xa bit ORER, nu khng, vic truyn hoc nhn s khng c tip tc. [4] hon tt qu trnh nhn: Ta phi c d liu nhn sau khi xa bit RE. Khi c SSRDR m khng xa bit RE, qu trnh nhn s khng c tip tc.
Hnh 13.16 Lu v d ca qu trnh nhn d liu (Ch giao tip ng b clock) (4) Qu trnh truyn nhn d liu Hnh 13.17 cho thy mt lu v d ca qu trnh truyn nhn ng thi. Qu trnh truyn nhn d liu ng thi c thc hin bng cch kt hp truyn d liu v nhn d liu nh cp trn. Qu trnh truyn nhn d liu c bt u bi vic ghi d liu truyn ln SSTDR vi TE = RE = 1. Trc khi chuyn t ch truyn (TE = 1) hoc ch nhn (RE = 1) sang ch truyn nhn ng thi (TE = RE = 1), ta phi xa bit TE v RE. Khi bt u truyn, cn xc nh cc bit TEND, RDRF, ORER u c xa trc khi set bit TE hay RE.
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Ch thch: [1] Thit lp ban u: La chn nh dng d liu truyn/nhn. [2] Kim tra trng thi SS v ghi d liu truyn: Ghi d liu truyn vo SSTDR sau khi c v xc nhn rng bit TDRE = 1. Bit TDRE s c t ng xa v qu trnh truyn nhn s khi ng bng vic ghi d liu vo SSTDR. [3] Kim tra trng thi SSU: c SSSR xc nhn bit RDRF = 1. Mt thay i ca bit RDRF (t 0 sang 1) c th c thng bo bi ngt qung RXI. [4] X l li nhn: Khi c mt li nhn xy ra, ta thc thi chng trnh x l li tng ng sau khi c bit ORER trong SSSR, sau xa bit ORER. Khi bit ORER bng 1, qu trnh truyn hay nhn u khng c tip tc. [5] Th tc truyn nhn d liu lin tc: Xc nhn bit TDRE = 1 (ngha l SSTDR sn sng ghi vo). Sau , d liu c th c ghi vo SSTDR. Bit TDRE s c xa t ng sau khi ghi d liu vo SSTDR.
Hnh 13.17 Lu v d ca qu trnh truyn nhn d liu ng thi (Ch giao tip ng b clock)
13.5 Yu cu ngt qung

Cc yu cu ngt qung ca SSU l ngt qung li overrun, li xung t, y thanh ghi d liu nhn, rng thanh ghi d liu truyn, v kt thc truyn. T cc ngun ngt qung ny, cc ngt qung y thanh ghi d liu nhn, rng thanh ghi d liu truyn v kt thc truyn c th kch hot DTC/DMAC truyn d liu. V c hai ngt qung li overrun v li xung t u ch ti a ch vector SSERI, v c hai ngt qung rng thanh ghi d liu truyn v kt thc truyn u ch ti a ch vector SSTXI, ngun ngt qung cn phi c xc nh bi c ca chng. Bng 13.5 lit k danh sch cc ngun ngt qung. Khi mt iu kin ngt qung hnh 13.5 c tha mn, mt ngt qung s c pht ra. Xa ngun ngt qung bng cch cho CPU, DTC/DMAC truyn d liu. Bng 13.5 Ngun ngt qung
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Knh Vit tt
Ngun ngt qung
K hiu
iu kin ngt qung
Kch hot DTC --C
Kch hot DMAC --C
SSERI0 Li overrun Li xung t SSRXI0 y thanh ghi d liu nhn SSTXI0 Rng thanh ghi d liu truyn Kt thc truyn
OEI0 (RIE = 1) v (ORER = 1) CEI0 (CEIE = 1) v (CE = 1) RXI0 (RIE = 1) v (RDRF = 1) TXI0 (TIE = 1) v (TDRE = 1) TEI0
(TEIE = 1) v (TEND C = 1) --C
C --C
SSERI1 Li overrun Li xung t SSRXI1 y thanh ghi d liu nhn SSTXI1 Rng thanh ghi d liu truyn Kt thc truyn
(TEIE = 1) v (TEND C = 1) --C
C --C
SSERI2 Li overrun Li xung t SSRXI2 y thanh ghi d liu nhn SSTXI2 Rng thanh ghi d liu truyn Kt thc
(TEIE = 1) v (TEND C
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truyn
= 1)
13.6 Ch s dng
13.6.1 Thit lp ca ch dng module SSU c th c cho php/cm bng cch thit lp thanh ghi iu khin dng module v b cm bi gi tr khi ng. Vic hy b ch dng module s cho php truy xut n thanh ghi ca SSU. bit thm chi tit, xem phn 19. 13.6.2 Ch v vic xa ch dng module Khi xa ch dng module, cn phi ch nhng iu sau. Khi s dng SSU knh 1 (hoc 2), SSU knh 1 (hoc 2) s khng c xa ch dng module khi cha xa cc bit sau. 1. Bit dng module cho knh 1 (hoc 2): MSTPC9 (hoc MSTPC10) 2. Bit dng module cho knh 0: MSTPC8. Khi knh 0 ca SSU khng c s dng cho hot ng ca SSU, cc chn cng xut/nhp tham gia vo hot ng ca knh 0 SSU c th c s dng nh cc chn xut/nhp, tr khi ch dng module c xa v knh 0 SSU c cho php truyn nhn d liu.
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Chng 14 B iu khin bus (BSC)

Vi iu khin ny c mt b iu khin bus ni (BSC). BSC ny c mt chc nng phn quyn bus v iu khin hot ng ca cc bus chnh bn trong ca CPU, DMAC v DTC.
14.1 Cc c im
S dng buffer cho vic ghi d liu Vic ghi vo mt thit b ngoi vi gn trong v truy cp b nh gn trong c th c thc hin song song. Chc nng phn quyn bus L mt b phn quyn bus c th cho php CPU hoc DMAC s dng bus. Quyn s dng bus c th chia s gia CPU, DMAC v DTC khi c xung t xy ra. Chc nng multi-clock Cc chc nng ngoi vi ni c th c ng b vi ng h ca cc thit b ngoi vi ni (P). Hnh 14.1 trnh by s khi ca b iu khin bus.
Hnh 14.1 S khi b iu khin bus
14.2 M t thanh ghi

B iu khin bus c cc thanh ghi sau. Thanh ghi iu khin bus 2 (BCR2)
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14.2.1 Thanh ghi iu khin bus 2 (BCR2) BCR2 c dng iu khin vic phn quyn bus cho CPU, DMAC, DTC, v cho php / cm chc nng dng buffer trong vic ghi d liu vo cc thit b ngoi vi.
Bit
Tn bit
Gi tr khi ng 0
R/W
c t
7,6 --
Khng dng. y l nhng bit ch c v khng c chnh sa.
--
R/W Khng dng. Bit ny lun c c l 0, gi tr ghi vo cng nn l 0.
IBCCS
R/W Chn iu khin chu k bus ni Chn chc nng phn quyn s dng bus ni. 0: Phn quyn lm ch bus da theo u tin. 1: Thc thi chu k bus thay phin nhau khi c s xung t gia yu cu ca CPU v yu cu ca DMAC/DTC.
3,2 --
Khng dng. y l nhng bit ch c v khng c chnh sa.
--
R/W Khng dng. Bit ny lun c c l 1, gi tr ghi vo cng nn l 1.
PWDBE 0
R/W Bit cho php s dng buffer trong vic ghi d liu vo thit b ngoi vi. 0: Chc nng buffer ghi d liu khng c dng. 1: Chc nng buffer ghi d liu c dng.
14.3 Cu hnh bus
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Hnh 14.2 cho thy cu hnh bus ni ca vi iu khin ny. Bus ni ny bao gm hai loi sau. Bus h thng ni 1 Mt bus kt ni vi CPU, DTC, DMAC, ROM ni, RAM ni, v bus ngoi vi ni. Bus ngoi vi ni Mt bus truy cp c ti cc thanh ghi trong DMAC, b iu khin bus, b iu khin ngt qung v cc thanh ghi ca thit b ngoi vi nh SCI v b nh thi.
Hnh 14.2 Cu hnh bus ni
14.4 Chc nng multi-clock

Cc chc nng ni ca vi iu khin ny hot ng ng b vi clock h thng (I) hoc cc clock ca thit b ngoi vi (P). Bng 14.1 cho thy clock ng b v cc chc nng tng ng ca chng. Bng 14.1 Clock ng b v cc chc nng tng ng Clock ng b I Tn chc nng Ch hot ng MCU B iu khin ngt qung B iu khin bus CPU DTC DMAC B nh ni B to xung clock iu khin power down
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Cc cng xut nhp TPU PPG WDT SCISSU A/D
Tn s ca tng clock ng b c ch nh bi thanh ghi iu khin clock h thng (SCKCR) mt cch c lp. bit thm chi tit, xem phn 18, B to xung clock.
14.5 Bus ni
14.5.1 Truy cp ti khng gian a ch ni Khng gian a ch ni ca vi iu khin ny l cc khng gian ROM ni, RAM ni v thanh ghi cho cc thit b ngoi vi ni. S chu k cn truy cp s khc nhau ty theo khng gian. Bng 14.2 cho thy s lng chu k cn truy cp tng khng gian b nh ni. Bng 14.2 S lng chu k cn truy cp tng khng gian b nh ni Khng gian truy cp Khng gian ROM ni Khng gian RAM ni Truy cp c c Ghi S chu k Mt chu k I Mt chu k I Hai chu k I
Trong vic truy cp cc thanh ghi ca thit b ngoi vi gn trong, s chu k cn thit s khc nhau ty theo thanh ghi no c truy cp. Khi t l chia ca clock hot ng ca bus master l 1:n, chu k ng b s dng mt clock Bng 14.3 S lng chu k cn truy cp thanh ghi ca cc thit b ngoi vi Module cn truy cp Thanh ghi DMAC Ch hot ng MCU, b to xung clock, b iu khin powerdown, b iu khin ngt qung, v thanh ghi ca b iu khin bus 2 I S lng chu k c 2 I 3 I Ghi Chc nng buffer ghi d liu Cm Cm
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Cc thanh ghi PFCR cng xut nhp v cc thanh ghi WDT TPU, PPG, SCI, cc thanh ghi A/D, v cc thanh ghi cng xut nhp khc PFCR Thanh ghi SSU
2 P
3 P
Cm
2 P
Cho php
3 P
Cho php
14.6 Hot ng b m d liu ghi

14.6.1 Bus Hot ng b m d liu ghi cho bus d liu ngoi Vi iu khin ny c chc nng s dng buffer cho vic ghi d liu cc bus d liu ngoi. S dng chc nng ny cho php vic ghi d liu ngoi v truy cp b nh ni c thc hin ng thi. Chc nng ny c cho php bng cch set bit PWDBE trong BCR2 ln 1. Hnh 14.3 cho thy mt v d ca vic nh thi khi chc nng buffer ghi d liu c s dng. Khi chc nng ny c s dng, nu mt vic ghi d liu ln khng gian a ch ngoi c din ra trong 2 chu k hoc hn, v c mt truy cp trong k tip, th ghi d liu ngoi ch c thc thi trong 2 chu k u tin. Tuy nhin, t chu k tip theo tr i, vic truy cp b nh ni v ghi vo khng gian a ch ngoi thay v i s c thc thi song song.
Hnh 14.3 V d vic nh thi khi chc nng buffer ghi d liu c bt
14.7 Phn quyn bus

Vi iu khin ny c th phn quyn lm ch hot ng ca bus ca CPU, DTC v DMAC.
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B phn quyn bus s quyt nh u tin da trn vic nh trc thi gian, v quyn s dng bus bng mt tn hiu ACK yu cu bus. 14.7.1 Hot ng B phn quyn bus s pht hin cc tn hiu yu cu bus, v nu bus c yu cu, n s gi mt tn hiu ACK v cho b phn mun s dng bus. Nu c nhiu b phn cng c yu cu bus mt lc, tn hiu ACK s c gi v cho b phn c u tin cao nht. Khi mt b phn nhn c ACK, n s chim quyn s dng bus cho ti khi tn hiu ny c hy b. u tin ca vic phn quyn bus ni: (High) DMAC > DTC > CPU (Low) Nu DMAC hoc DTC ang s dng bus, CPU c th c set u tin cao hn DMAC v DTC thc thi bus lun phin vi DMAC hoc DTC, bng cch set bit IBCCS trong BCR2. 14.7.2 nh thi chuyn quyn trn bus Ngay c khi mt yu cu bus c nhn t b phn c u tin cao hn b phn ang s dng bus, bus cng khng cn phi c chuyn quyn s dng ngay. CPU: CPU l b phn c u tin thp nht, v nu mt yu cu bus c nhn t DMAC hay DTC, b phn quyn bus s chuyn quyn s dng bus cho b phn pht ra tn hiu yu cu. Thi gian chuyn quyn s dng bus l cui mi chu k bus. Trong ch ng (sleep), bus s c chuyn quyn ng b vi clock. Ch , mc d vy, bus s khng b chuyn quyn trong cc trng hp sau. Vic truy cp word hoc longword ang din ra gia chng. X l stack xy ra trong nhiu chu k bus. D liu ang c c hoc ghi bi cc cu lnh truyn d liu b nh, lnh truyn d liu khi hoc lnh TAS. (Trong cc lnh truyn d liu khi, bus c th b chuyn quyn s dng gia chu k ghi v chu k c k tip.) T mt mc tiu c ghi trong cc cu lnh x l bit hoc cu lnh thc thi b nh. (Trong mt cu lnh khng thc thi vic ghi ty thuc vo iu kin lnh, ta cn thm mt chu k tng ng vi chu k ghi ) DTC: DTC gi mt yu cu bus ti b phn quyn bus ni khi c mt yu cu kch hot c pht ra. Khi DTC truy cp mt khng gian bus ngoi, trc ht DTC s ly quyn iu khin bus t b phn quyn bus ni, v sau yu cu bus t b phn quyn bus ngoi. Mt khi DTC chim c quyn iu khin bus, DTC s thc hin lin tip cc chu k truyn d liu. Nu mt b phn khc c u tin cao hn DTC yu cu bus,
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DTC s chuyn quyn s dng bus cho b phn kia. Nu bit IBCCS trong BCR2 c set ln 1, DTC s chuyn bus cho CPU. Ch , mc d vy, bus s khng b chuyn quyn trong cc trng hp sau. Trong lc c thng tin truyn. Trong chu k chuyn d liu u tin. Trong lc ghi li thng tin truyn. DTC s gii phng bus khi chu k chuyn d liu c hon tt. DMAC: DMAC gi mt yu cu bus ti b phn quyn bus ni khi c mt yu cu kch hot c pht ra. Mt khi DMAC chim quyn iu khin bus, n s thc hin vic truyn d liu lin tip, hoc gii phng bus sau mi chu k truyn. Ch , mc d vy, bus s khng b chuyn quyn trong cc trng hp sau. Gia mt chu k c v chu k ghi tng ng trong ch a ch kp Khi bit IBCCS trong BCR2 c xa, bus s khng b chuyn quyn s dng trong cc trng hp sau. Khi 1 khi d liu ang c truyn trong ch truyn d liu khi Khi ang din ra qu trnh chuyn quyn s dng bus. DMAC s gii phng bus khi chu k chuyn d liu c hon tt, tr cc chu k trn.
14.8 Hot ng ca b iu khin bus trong khi Reset

Trong mt reset, vi iu khin ny, k c b iu khin bus, s bc vo trng thi reset ngay lp tc, v tt c cc chu k bus ang hot ng s b hy b.
14.9 Ch s dng
Ch dng tt c clock module: Nu bit ACSE trong thanh ghi MSTPCR c set ln 1 vi mt thit lp dng tt c ng h module ngoi vi (MSTPCR = 0xFFFFFFFF), th vi iu khin ny s vo ch dng tt c ng h module. bit thm chi tit, xem phn 19, Cc ch Power-down.
465
Chng 15 RAM
Thit b ny c 12Kbyte RAM tnh trn chip (tc truy xut cao). RAM c kt ni vi CPU thng qua bus d liu 32-bit, cho php CPU c 1-trng thi v truy xut ghi 2-trng thi i vi tt c d liu byte, word, hay longword. RAM trn chip c th b cm/cho php bi bit RAME trong thanh ghi iu khin h thng SYSCR. Chi tit v SYSCR, tham kho phn 3.2.2, thanh ghi iu khin h thng SYSRC. Phn loi sn phm Phin bn b nh flash H8SX/1582 Kch thc RAM 12 kbytes a ch RAM H'FF9000 to H'FFC000
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Chng 16 B nh Flash
B nh flash c cc tnh cht sau. Hnh 16.1 l mt s khi ca b nh flash.
16.1 Cc tnh cht

Kch thc Phn loi sn phm Kch thc ROM 256 kbytes a ch ROM
H8SX/1582
R5F61582
H'000000 to H'03FFFF (ch 1 n 3)
2 b nh MAT a ch bt u ca 2 vng b nh (b nh MAT) c cp pht cng 1 a ch. Vic thit lp ch khi khi ng s quyt nh b nh MAT no s c khi ng trc. Cc b nh MAT c th c chuyn qua li ln nhau bng cch s dng phng php chuyn bng (bank-switching) sau khi khi ng. User MAT c khi ng trong ch ngi dng: 256Kbyte User Boot MAT c khi ng trong ch user boot: 10 Kbyte. Lp trnh/xa bi vic download chng trnh trn chip Thit b ny c mt chng trnh lp trnh/xa. Sau khi download chng trnh ny vo RAM trn chip, th vic lp trnh/xa c th c thc hin bi vic thit lp cc tham s (parameter) Thi gian Lp trnh/xa Thi gian lp trnh: tP ms (typ) cho vic lp trnh 128-byte ng thi, tP/128 s mi byte. Thi gian xa: tE ms (typ) mi khi (64Kbyte) S ln lp trnh S ln lp trnh ti thiu l NWEC (ngha l cc ln lp trnh t 1 n NWEC l c m bo ng) Ba ch lp trnh trn board Ch Boot: S dng knh SCI 4 trn chip, trong ch boot th vng user MAT v vng user boot MAT l c th c lp trnh/xa. V trong ch ny, th tc gia my tnh v thit b (CPU H8SX) c th c iu chnh mt cch t ng Ch user program: S dng mt desired interface, vng user MAT c th c lp trnh/xa
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Ch user Boot: S dng mt desired interface, chng trnh user boot c th c lm v vng user MAT c th c lp trnh/xa. Ch lp trnh off-board Ch programer: s dng mt chng trnh lp trnh PROM (PROM programmer) vng user MAT v user boot MAT c th c lp trnh/xa Bo v lp trnh/xa Vic cm vic lp trnh/xa ca b nh flash c th c thit lp bi s bo v bi phn cng, bo v bng phn mm, hay bo v bi li Chc nng m phng b nh flash s dng RAM trn chip S m phng thi gian thc ca vic lp trnh b nh flash c th c thc hin bi phn c ph ca vng b nh flash (user MAT) v RAM trn chip
Hnh 16.1 S khi ca b nh flash
16.2 S chuyn ch
Khi cc chn thit lp ch c thit lp trong trng thi khi ng v bt u khi ng th thit b ny s vo cc trng thi hot ng nh hnh 16.2. Mc d b nh flash c th c c trong ch user, tuy nhin n khng th b lp trnh hay xa. B nh flash c th c lp trnh/xa trong ch boot, ch user program,
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ch user boot, v ch programmer. S khc bit gia cc ch boot, user program, user boot, v programmer c trnh by trong bng 16.1
Hnh 16.2 S chuyn ch ca b nh flash Bng 16.1 S khc bit gia cc ch boot, ch user program, user boot, v ch programmer. Loi Mi trng lp trnh/xa Cc vng MAT cho php lp trnh/xa Ch boot Lp trnh onboard - User MAT - User Boot MAT Giao din lp trnh/xa O O T thit b mong mun thng qua RAM Giao din lp trnh/xa O O T thit b mong mun thng qua RAM Ch User Program Lp trnh onboard - User MAT Ch User Boot Lp trnh onboard - User MAT Ch Programmer Lp trnh offboard - User MAT - User Boot MAT Lnh O (t ng) X Thng qua programer
iu khin lp Lnh trnh/xa Xa tt c Xa khi O (T ng) O*1
Truyn d liu T my tnh chng trnh thng qua SCI
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M phng RAM Reset initiation MAT Chuyn sang ch user Ch :
X Vng cha chng trnh nhng Chuyn ch v reset
O User MAT
O User boot MAT*2 Chuyn ch v reset
X ---
lp trnh/xa hon ton*3
---
1. Xa tt c c thc hin. Sau , khi c ch nh c th c xa. 2. u tin, vector reset c np t vng lu tr chng trnh nhng. Sau khi cc thanh ghi lin quan n b nh flash c kim tra, thi reset vector c c c vo t vng user boot MAT. 3. Trong thit b ny, ch user programming c nh ngha nh l thi khong k t thi im mt chng trnh lin quan n vic lp trnh v xa c bt u n thi im khi m chng trnh hon tt. Chi tit v mt chng trnh lin quan n vic lp trnh v xa, tham kho phn 16.8.2, ch user program.
16.3 Cu hnh vng b nh MAT

Cc vng MAT ca b nh flash trong thit b ny bao gm vng user MAT 256Kbyte v vng user boot MAT 10-Kbyte. a ch bt u ca vng user MAT v user boot MAT l trng nhau. Chnh v vy m khi thc thi chng trnh hay truy xut d liu c thc hin gia 2 vng ny, th cc vng MAT phi c chuyn i bi thanh ghi la chn vng MAT ca b nh flash (FMATS) Vng user MAT hay user boot MAT c th c c trong tt c cc ch . Tuy nhin, vng user boot MAT c th c lp trnh hay xa ch trong ch boot v trong ch programmer. Kch thc ca vng user MAT th khc vi kch thc ca vng user boot MAT. Cc a ch m vt qu vng kch thc 10-Kbyte ca user boot MAT s khng c truy xut. Tuy nhin nu c gng c th d liu c c s l mt gi tr khng xc nh.
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Hnh 16.3 Cu hnh b nh MAT
16.4 Cu trc ca cc khi (block)

Hnh 16.4 trnh by cu trc khi ca vng user MAT 256-kbyte. Cc khung ng m l ch cc khi xa (vic xa s c thc hin theo tng khi ny). Cc khung ng nh l ch cc n v lp trnh v cc gi tr trong cc khung l i din cho cc a ch. Vng user MAT c chia thnh 3 khi 64-kbyte, mt khi 32-Kbyte, v 8 khi 4-Kbyte. Vng user MAT c th c xa theo cc khi n v ny. Vic lp trnh c thc hin theo n v 128-byte bt u t ni m a ch thp l H00 hay H80. S m phng RAM c th c thc hin trong 8 khi 4K-byte.
471
Hnh 16.4 Cu trc khi ca User MAT
16.5 Giao din Lp trnh/xa

Vic lp trnh/xa b nh flash c thc hin bi vic download chng trnh lp trnh/xa trn chip vo RAM trn chip v vic ch nh a ch bt u ca vng lp trnh, d liu lp trnh, v s khi xa s dng cc thanh ghi giao din lp trnh/xa v cc tham s ca giao din lp trnh/xa. Tin trnh lp trnh cho ch user program v ch user boot c thc hin bi ngi dng. Hnh 16.5 Trnh by tin trnh to ra mt chng trnh lp trnh. Chi tit, tham kho phn 16.8.2, Ch User Program.
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Hnh 16.5 Tin trnh to ra mt chng trnh lp trnh. (1) La chn chng trnh on-chip s c download lp trnh/xa, th bit FLSHE trong thanh ghi iu khin h thng (SYSCR) phi c thit lp ln 1 la chn ch user program. Trong thit b ny c cc chng trnh lp trnh/xa m c th c download vo RAM on-chip. Chng trnh on-chip m c download l c la chn bi cc thanh ghi giao din ca vic lp trnh/xa. a ch bt u ca RAM on-chip ni m mt chng trnh on-chip s c download s c ch nh bi thanh ghi a ch ch truyn b nh flash (FTDAR). (2) Qu trnh download chng trnh on-chip Chng trnh on-chip s c download mt cch t ng bi vic thit lp thanh ghi key code flash (FKEY) v bit SCO trong thanh ghi trng thi/iu khin code flash (FCCS) sau khi khi ng thanh ghi nn vector (VBR). B nh MAT c thay th bi vng lu tr chng trnh nhng trong sut qu trnh download. V b nh MAT l khng th c trong khi lp trnh/xa, tin trnh lp trnh phi c thc thi trong mt vng khng gian khc vng b nh flash (v d, RAM onchip). Kt qu download c tr v cho cc tham s giao din lp trnh/xa, ni ln liu qu trnh download l c thc thi mt cch bnh thng hay khng. Ni dung ca VBR c th b thay i sau khi qu trnh download c hon tt. (3) khi ng vic lp trnh/xa Mt xung vi mt thi khong xc nh phi c s dng trong khi lp trnh hay xa. rng ca xung ny c thc hin bi cch thc m trong vng lp ch c cu hnh bi cu lnh CPU. Do , tn s hot ng ca CPU cn c thit lp trc khi lp trnh/xa. Tn s hot ng ca CPU c thit lp bi thng s giao din lp trnh/xa.
473
(4) Thc thi vic lp trnh/xa lp trnh/xa, th bit FLSHE trong thanh ghi SYSCR phi c thit lp ln 1 chuyn i sang ch user program. a ch bt u ca vng lp trnh v d liu lp trnh c ch nh theo n v 128-byte khi lp trnh. Khi c xa l c ch nh vi ch s ca khi v xa theo n v khi. S ch nh a ch bt u ca vng lp trnh, d liu lp trnh, v ch s khi c xa c thc hin bi cc tham s giao din lp trnh/xa. Chng trnh lp trnh on-chip c thc thi s dng cu lnh JSR hay BSR v vic thc thi hm con ca a ch c ch nh trong RAM on-chip. Kt qu ca vic thc thi c tr v cho cc tham s giao din lp trnh/xa. Vng c lp trnh phi b xa trc khi chng trnh c ghi vo b h flash. Tt c cc ngt qung u b cm trong qu trnh lp trnh/xa. (5) Khi vic lp trnh/xa c thc thi mt cch lin tc Khi vic thc thi khng kt thc bi vic lp trnh 128-byte hay vic xa 1 khi, th vic lp trnh/xa lin tc c th c thc hin bi vic cp nht li a ch bt u ca vng lp trnh v d liu lp trnh, hay ch s khi xa. V vy m chng trnh download on-chip vn cn trn RAM on-chip thm ch sau khi vic lp trnh/xa hon tt, vic download v khi ng l khng c yu cu khi mt qu trnh tng t c thc thi mt cch lin tc.
16.6 Cc chn xut/nhp

B nh flash c iu khin thng qua cc chn nh trnh by bng 16.2 Bng 16.2 Cu hnh chn Tn chn
RES
Xut/nhp Input Input Output Input Reset
Chc nng Thit lp ch hot ng ca thit b Ng xut d liu truyn tun t (s dng trong ch boot) Ng nhp d liu nhn tun t (s dng trong ch boot)
MD1 and MD0 TxD4 RxD4
16.7 c t thanh ghi

B nh flash c cc thanh ghi sau. truy xut cc thanh ghi ny, th bit FLSHE trong thanh ghi iu khin h thng SYSCR phi c thit lp ln 1. Chi tit v SYSCR, tham kho thm phn 3.2.2, Thanh ghi iu khin h thng (SYSCR). Cc thanh ghi giao din lp trnh/xa Thanh ghi trng thi/iu khin code flash (FCCS) Thanh ghi la chn code chng trnh flash (FPCS)
474
Thanh ghi la chn code xa flash (FECS) Thanh ghi code key flash (FKEY) Thanh ghi la chn MAT flash (FMATS) Thanh ghi a ch ch truyn flash (FTDAR) Cc tham s giao din lp trnh/xa Tham s kt qu download tht bi v thnh cng (DPFR) Tham s kt qu tht bi v thnh cng Flash (FPFR) Tham s tn s lp trnh/xa flash (FPEFEQ) Tham s vng a ch nhiu mc ch flash (FMPAR) Tham s vng ch d liu nhiu mc ch flash (FMPDR) Tham s la chn khi xa flash (FEBS)
C mt vi ch hot ng cho vic truy xut b nh flash. Tng ch , thanh ghi v cc thng s c ch nh cho vng user MAT v user boot MAT. S tng ng gia cc ch hot ng v cc thanh ghi s dng c trnh by trong bng 16.3 Bng 16.3 Cc thanh ghi/cc tham s v cc ch ch (target mode) Thanh ghi/tham s Download Cc thanh ghi giao din lp trnh/xa FCCS FPCS FECS FKEY FMATS FTDAR O O O O --O Khi to --------------O O --------Lp trnh ------O O* ----O --O O ----1
Xa
M phng RAM ---------
------O O* ----O ------O --1
--------O* ----------------2
----------------O
Cc tham s DPFR O giao din lp FPFR --trnh/xa FPEFEQ --FMPAR FMPDR FEBS RAM emulation Ch : -------
RAMER ---
475
1. Yu cu phi thit lp vo thanh ghi ny khi xa hay lp trnh vng user MAT trong ch user boot. 2. Vic thit lp c th c yu cu thng qua s kt hp ca ch khi ng v c b nh ch (target) MAT. 16.7.1 Cc thanh ghi giao din lp trnh/xa Cc thanh ghi giao din lp trnh/xa l cc thanh ghi 8-bit m ch c th truy xut theo byte. Cc thanh ghi ny c khi ng bi mt reset (power-on reset). (1) Thanh ghi trng thi/iu khin code flash (FCCS) Thanh ghi FCCS gim st li trong lc lp trnh/xa b nh flash v yu cu chng trnh on-chip c download ln RAM on-chip.
Bit
Tn bit ------FLER
Gi tr khi ng 1 0 0 0
R/W
c t
7 6 5 4
R R R R
Khng dng y l nhng bit ch c v khng th hiu chnh gi tr ca n. Bit li b nh flash Bit ny ch ra rng mt li xy ra trong qu trnh lp trnh hay xa b nh flash. Khi bit ny c thit th mc in th cao c p vo b nh flash trong. gim h hng cho b nh flash, th tn hiu reset phi c gii phng sau khi mt k reset t nht l 100 s (RES = 0) 0: b nh flash hot ng mt cch bnh thng [iu kin xa] - Mt tn hiu reset (power-on) 1: Mt li xy ra trong qu trnh lp trnh/xa b nh flash [iu kin set] Khi mt ngt qung, v d NMI, xy ra trong qu trnh lp trnh/xa Khi b nh flash c c trong qu trnh lp trnh/xa (bao gm mt vector read v
476
mt instruction fetch) Khi cu lnh SLEEP c thc thi trong qu trnh lp trnh/xa (bao gm ch standby phn mm) Khi mt b phn iu khin bus (bus master) khc CPU, v d nh DMAC v DTC, chim gi bus trong sut qu trnh lp trnh/xa.
3~1
---
Khng dng y l cc bit ch c v khng th hiu chnh gi tr ca n.
SCO
(R)/W* Bit sao chp chng trnh ngun Yu cu chng trnh lp trnh/xa on-chip download xung RAM on-chip. Khi bit ny c thit lp ln 1, th chng trnh on-chip m c la chn bi FPCS hay FECS c t ng download vo vng RAM on-chip vng m c ch nh bi FTDAR. thit lp bit ny ln 1, th ch m phng RAM phi b t chi (hay b hy), gi tr HA5 phi c ghi vo FKEY, v hot ng ny phi c thc thi trong RAM on-chip. Hot ng Dummy Read (c gi) ca FCCS phi c thc thi 2 ln ngay lp tc sau khi thit lp bit ny ln 1. Tt c cc ngt qung phi b cm trong qu trnh download. Bit ny b s xa khi qu trnh download hon tt. Trong qu trnh chng trnh download m c khi ng bi bit ny, qu trnh x l ring bit m h tr cho vic chuyn i vng lu tr chng trnh c thc thi. Trc khi mt yu cu download, khi ng ni dung ca thanh ghi VBR l H0000 0000. Sau khi hon tt vic download, ni dung ca VBR c th b thay i. 0: vic download chng trnh lp trnh/xa l khng c yu cu. [iu kin xa] Khi m hot ng download hon thnh 1: vic Download chng trnh lp trnh/xa l c yu cu
477
[iu kin set] (khi tt c cc iu kin sau tha mn) Khng nm trong ch m phng RAM (bit RAMS trong thanh ghi RAMER bng 0) Gi tr c ghi vo FKEY l HA5 Vic thit lp bit ny c thc hin trong RAM on-chip.
Ch : * l nhng bit ch ghi. Bit ny lun c c vi gi tr l 0 (v ch c ghi) (2) Thanh ghi la chn code chng trnh flash (FPCS) FPCS la chn chng trnh lp trnh c download.
Bit
Tn bit
Gi tr khi ng 0
R/W
c t
7~1
---
Khng dng y l cc bit ch c v khng th hiu chnh gi tr ca n.
PPVS
R/W
Bit kim tra xung lp trnh Bit ny la chn chng trnh lp trnh s c download 0: chng trnh lp trnh khng c chn [iu kin xa] Khi hot ng truyn hon tt 1: Chng trnh lp trnh c la chn.
(3) Thanh ghi la chn code xa flash (FECS) FECS la chn chng trnh xa s c download.
478
Bit
Tn bit
Gi tr khi ng 0
R/W
c t
7~1
---
Khng dng Cc bit ny l bit ch c v khng th thay i gi tr ca n.
EPVB
R/W
Khi xc nhn xung xa La chn chng trnh xa c download. 0: chng trnh xa khng c chn [iu kin xa] Khi hot ng truyn hon tt. 1: chng trnh xa c la chn.
(4) Thanh ghi Key code flash (FKEY) Thanh ghi FKEY l mt thanh ghi bo v phn mm m cho php vic download chng trnh on-chip v thc hin vic xa/lp trnh ca b nh flash
Bit
Tn bit
Gi tr khi ng 0 0 0 0 0 0 0 0
R/W
c t
7 6 5 4 3 2 1 0
K7 K6 K5 K4 K3 K2 K1 K0
R/W R/W R/W R/W R/W R/W R/W R/W
Cc bit Key Code Khi gi tr c ghi vo FKEY l HA5, th vic ghi vo bit SCO trong thanh ghi FCCS l c cho php. Khi mt gi tr khc HA5 c ghi vo FKEY th bit SCO s khng c thit lp ln 1. V vy, chng trnh on-chip s khng c download vo RAM on-chip. Ch khi gi tr c ghi vo l H5A th vic lp trnh/xa b nh flash mi c thc thi. Khi mt gi tr khc H5A c ghi vo, thm ch nu chng trnh c lp trnh/xa th n vn khng th thc thi. HA5: vic ghi vo bit SCO s c cho php (SCO s khng c thit lp l 1 khi gi tr trong FKEY khc HA5) H5A: vic lp trnh/xa b nh flash c cho
479
php (Khi gi tr ghi vo FKEY khc H5A th khng th vo trng thi bo v phn mm). H00: gi tr khi u (5) Thanh ghi la chn vng MAT flash (FMATS) Thanh ghi FMAT la chn vng user MAT hay user boot MAT. Vic ghi vo FMATS nn c thc hin khi mt chng trnh trn RAM on-chip ang c thc thi.
Ch : * Bit ny c thit lp ln 1 trong ch user boot, cn cc ch khc b xa. Bit Tn bit Gi tr khi ng 0/1* 0 0/1* 0 0/1* 0 0/1* 0 R/W c t
7 6 5 4 3 2 1 0
MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0
R/W R/W R/W R/W R/W R/W R/W R/W
La chn MAT Cc vng b nh MAT c th c chuyn i bng cch ghi gi tr vo FMATS. Khi gi tr HAA c ghi vo FMATS, th vng user boot MAT c la chn. Khi ghi gi tr khc HAA c ghi vo, th vng user MAT c la chn. Qu trnh chuyn b nh MAT trong vng 16.11, Chuyn i vng user MAT v user boot MAT. Vng user boot MAT khng th la chn bi thanh ghi FMATS trong ch user programming. Vng user boot MAT c th c la chn trong ch boot hay trong ch programmer. HAA: vng user boot MAT c la chn (vng user MAT c la chn khi FMATS c gi tr khc HAA). (l gi tr khi ng trong ch user boot). H00: la chn vng user MAT (l gi tr khi ng trong cc ch tr user boot)
Ch : * bit ny c thit lp l 1 trong ch user boot, ngc li th n b xa. (6) Thanh ghi a ch ch truyn flash (FTDAR)
480
Thanh ghi FTDAR ch nh a ch bt u ca RAM on-chip c dng download chng trnh on-chip. Thanh ghi FTDAR phi c thit lp trc khi thit lp bit SCO trong thanh ghi FCCS ln 1.
Bit
Tn bit
Gi tr khi ng 0
R/W
c t
TDER
R/W
Bit li thit lp a ch ch truyn Bit ny c set ln 1 khi mt li xy ra trong vic thit lp a ch bt u m c ch nh bi cc bit TDA6 n TDA0. Mt li a ch bt u c xc nh bi liu gi tr trong cc bit TDA6 n TDA0 c thuc gii hn t H00 n H02 hay khng, khi vic download c thc hin bi vic set bit SCO trong thanh ghi FCCS ln 1. Phi chc chn rng bit ny s c xa trc khi set bit SCO ln 1 v gi tr c ch nh trong cc bit TDA0 n TDA6 l nm trong phm vi t H00 n H02. 0: Gi tr c ch nh trong cc bit t TDA0 n TDA6 l nm trong gii hn. 1: Gi tr c ch nh trong cc bit t TDA0 n TDA6 l nm gia H03 n HFF v vic download s b dng li.
6 5 4 3 2 1 0
TDA6 TDA5 TDA4 TDA3 TDA2 TDA1 TDA0
0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W
Cc bit a ch ch truyn Ch nh a ch bt u ca RAM on-chip ca ch download. Mt gi tr gia H00 v H02, v di 4kbyte c th c ch nh l a ch bt u cho RAM on-chip. H00: gi tr HFF9000 c ch nh l a ch bt u H01: gi tr HFFA000 c ch nh l a ch bt u H02: gi tr HFFB000 c ch nh l a ch bt u H03 n H7F: Cm thit lp (vic ch nh gi tr gia H03 n H7F thit
481
lp bit TDER ln 1 v dng vic download chng trnh on-chip) 16.7.2 Cc tham s giao din lp trnh/xa Cc tham s giao din lp trnh/xa ch nh tn s hot ng, vng lu tr d liu chng trnh, v a ch bt u ca ch lp trnh, v ch s khi xa, v trao i kt qu thc thi. Cc tham s s dng cc thanh ghi a dng ca CPU (ER0 n ER1) hay vng RAM on-chip. Gi tr ban u ca cc thng s giao din lp trnh/xa l khng xc nh khi reset (power-on) hay khi chuyn sang ch standby phn mm. V cc thanh ghi ca CPU tr thanh ghi R0 l c lu trong stack trong qu trnh download chng trnh on-chip, khi ng, lp trnh, hay xa, nm vng stack trc khi thc hin cc hot ng (kch thc stack ti a l 128byte). Gi tr tr v ca kt qu thc thi l c ghi vo R0. Cc tham s giao din lp trnh/xa l c s dng trong vic iu khin download, khi ng trc khi lp trnh hay xa. Bng 16.4 trnh by cc tham s c th s dng v cc ch ch (target mode). ngha ca cc bit trong tham s kt qu thnh cng v tht bi flash (FPFR) l khc nhau trong cc hot ng khi ng, lp trnh hay xa. Bng 16.4 Cc tham s v cc ch ch (target mode) Thng s DPFR FPFR FPEFE Q FMPA R FMPD R FEBS Download Kh i to O O ----------O O ------Lp trnh --O --O O --Xa --O ------O R/ W Gi tr khi ng V tr
R/W Khng nh R/W Khng nh R/W Khng nh R/W Khng nh R/W Khng nh R/W Khng nh
xc RAM On-chip * xc R0L ca CPU xc ER0 ca CPU xc ER1 ca CPU xc ER0 ca CPU xc ER0 ca CPU
Ch : * mt byte n ca a ch bt u ca RAM on-chip c ch nh bi thanh ghi FTDAR. iu khin download: Chng trnh on-chip c download t ng bi vic thit lp bit SCO trong thanh ghi FCCS ln 1. Vng RAM on-chip download chng trnh on-chip l vng 4kbyte bt u t a ch bt u c ch nh bi thanh ghi FTDAR. Vic download c ch nh bi cc thanh ghi giao din lp
482
trnh/xa, v cc tham s kt qu thnh cng v tht bi ca vic download (DPFR) ch nh gi tr tr v. Khi ng trc khi lp trnh/xa: chng trnh on-chip bao gm chng trnh khi ng. Mt xung vi rng chu k c xc nh phi c thc hin trong khi lp trnh hay xa. rng ca xung c ch nh ny c to thnh bi cch thc m trong vng lp i c cu hnh bi cc cu lnh ca CPU. Do , tn s hot ng ca CPU phi c thit lp. Chng trnh khi ng c thit lp nh l mt tham s ca chng trnh lp trnh/xa m c download thc thi cc vic thit lp ny. a ch bt u ca ch lp trnh trn vng user MAT phi c lu trong thanh ghi a dng ER1. Tham s ny c gi l tham s vng a ch nhiu mc ch flash (multipurpose) (FMPAR). D liu chng trnh lun lun c tnh theo n v 128-byte. Khi d liu chng trnh khng tha 128-byte, th chng trnh 128-byte s c to thnh bi vic thm vo cc code gi (HFF). Bin ca a ch bt u ca ch lp trnh trn vng user MAT c tng thch vi mt a ch ni m cc bit thp ca a ch ny (A0 n A7) l H00 hay H80. D liu lp trnh ca vng user MAT phi c t trong cc vng lin tc. D liu lp trnh phi nm trong mt vng khng gian lin tc vng khng gian m c th c truy xut bng cch s dng cu lnh MOV.B ca CPU v vng khng gian phi khc vng khng gian b nh flash a ch bt u ca vng m lu d liu s c ghi vo vng user MAT phi c thit lp trong thanh ghi a dng ER0. Tham s ny c gi l tham s vng ch d liu nhiu mc ch ca b nh flash (FMPDR). Chi tit v tin trnh lp trnh, tham kho phn 16.8.2, Ch user program. Hot ng xa: khi b nh flash c xa, ch s khi trn vng user MAT phi c a vo chng trnh xa chng trnh m s c download. Ch s khi xa trn vng user MAT phi c thit lp trong thanh ghi ER0. Tham s ny c gi l tham s chn khi xa flash (FEBS) Ch s khi c chn t cc ch s t 0 n 11. Chi tit v tin trnh xa, tham kho phn 16.8.2, ch user program. (1) Tham s kt qu thnh cng v tht bi ca vic download (DPFR: mt byte n ca a ch bt u trong vng RAM on-chip c ch nh bi thanh ghi FTDAR) DPFR ch nh gi tr tr v ca kt qu hot ng download. Gi tr ca DPFR c s dng xc nh kt qu download.
Bit
Tn
Gi tr
R/W
c t
483
bit 7~3 2 --SS
khi ng ------R/W Khng dng Cc bit ny lun tr v 0. Bit kim tra li chn ngun Ch mt loi chng trnh on-chip m c th c download. Khi chng trnh c download khng c chn, th c nhiu hn 2 loi chng trnh c chn, hay mt chng trnh m khng c nh x c chn, khi mt li s pht sinh. 0: Vic chn chng trnh l bnh thng. 1: Vic chn chng trnh l khng bnh thng.
FK
---
R/W
Bit kim tra li thanh ghi key flash Kim tra gi tr trong thanh ghi FKEY (HA5) v tr v kt qu. 0: vic thit lp thanh ghi FKEY l bnh thng (HA5). 1: vic thit lp thanh ghi FKEY l khng bnh thng (mt gi tr khc HA5).
SF
---
R/W
Bit thnh cng/tht bi Tr v kt qu ca hot ng download. c tr li chng trnh c download vo RAM onchip v quyt nh liu n c chuyn vo RAM on-chp hay cha. 0: Vic download chng trnh kt thc mt cch bnh thng (khng c li). 1: Vic download chng trnh kt thc mt cch khng bnh thng ( c li pht sinh).
(2) Tham s thnh cng v tht bi flash (FPFR: thanh ghi a dng R0L ca CPU) FPFR ch ra gi tr ra v ca kt qu khi ng, lp trnh v xa. Gi tr ca cc bit trong FPFR l c nhiu ngha khc nhau ty thuc vo vic x l. (a) khi ng trc khi lp trnh/xa FPFR ch ra gi tr tr v ca kt qu khi ng
484
Bit
Tn bit --FQ
Gi tr khi ng -----
R/W
c t
7~2 1
--R/W
Khng dng Cc bit ny lun tr v 0. Kim tra li tn s So snh tn s c ch nh cho CPU vi tn s hot ng c h tr bi thit b v tr v kt qu. 0: Vic thit lp tn s l bnh thng 1: Vic thit lp tn s l khng bnh thng
SF
---
R/W
Thnh cng/tht bi Tr v kt qu ca vic khi ng 0: vic khi ng kt thc mt cch bnh thng (khng c li) 0: vic khi ng kt thc mt cch khng bnh thng (c li xy ra)
(b) Lp trnh FPFR ch ra gi tr tr v ca kt qu lp trnh.
Bit
Tn bit
Gi tr khi ng -----
R/W
c t
7 6
--MD
--R/W
Khng dng Tr v 0. Bit kim tra li thit lp lin quan n vic lp trnh ch . Kim tra trng thi bo v li (error protection) v tr v kt qu. Khi vo trng thi bo v li, th bit ny c thit lp ln 1. Vic c vo trng thi bo v li hay khng c th c khng nh bi bit FLER trong thanh ghi FCCS. iu kin vo trng thi ny, tham kho phn 16.9.3, Bo v li (Error Protection).
EE
---
R/W
Kim tra li thc thi lp trnh. Ghi gi tr 1 vo bit ny khi d liu c ch nh

485
khng th ghi vo vng user MAT (v n cha c xa). Nu bit ny c thit lp ln 1, th c kh nng ln l vng user MAT c ghi cha hon chnh. Trong trng hp ny, th sau khi loi b cc h s li (error factor), xa vng user MAT. Nu FMATS c ghi vo gi tr l HAA v vng c chn l vng user boot MAT, th mt li s pht sinh khi vic lp trnh c thc thi. Trong trng hp ny th vng user MAT v user boot MAT u khng c php ghi. Vic lp trnh cho vng user boot MAT nn c thc thi trong ch boot hay trong ch programmer. 0: Vic lp trnh kt thc mt cch bnh thng. 0: Vic lp trnh kt thc mt cch khng bnh thng. 4 FK --R/W Bit Kim tra li thanh ghi Key Flash. Kim tra gi tr trong thanh ghi FKEY (HA5) trc khi bt u lp trnh, v tr v kt qu. 0: Vic thit lp cho thanh ghi FKEY l bnh thng (H5A). 0: Vic thit lp cho thanh ghi FKEY l khng bnh thng (mt gi tr khc H5A). 3 2 --WD ------R/W Khng dng. Tr v 0. Bit kim tra a ch ghi d liu. Khi mt a ch khng c trong vng a ch flash c ch nh l a ch bt u cho vng ch lu tr cho d liu ca chng trnh, th mt li s pht sinh. 0: vic thit lp a ch bt u ca vng ch lu tr cho d liu chng trnh l bnh thng. 1: vic thit lp a ch bt u ca vng ch lu tr cho d liu chng trnh l khng bnh thng. 1 WA --R/W Bit kim tra li a ch ghi. Khi mt a ch nh bn di c ch nh l a ch bt u ca vng ch lp trnh th mt li
486
s pht sinh. Mt vng nh khng phi l b nh flash. Mt a ch khng tng thch vi 128byte (8 bit thp ca a ch l khc vi H00 v H80).
0: vic thit lp a ch bt u cho vng lp trnh l bnh thng. 1: vic thit lp a ch bt u cho vng lp trnh l khng bnh thng. 0 SF --R/W Thnh cng/tht bi. Tr v kt qu ca vic lp trnh. 0: Vic lp trnh kt thc mt cch bnh thng (khng c li). 1: Vic lp trnh kt thc mt cch khng bnh thng (c li xy ra). (c) Xa Thanh ghi FPFR ch ra gi tr tr v ca kt qu xa
Bit
Tn bit --MD
Gi tr khi ng -----
R/W
c t
7 6
--R/W
Khng dng. Tr v gi tr 0. Bit kim tra li thit lp lin quan n ch xa. Kim tra trng thi bo v li (error protection) v tr v kt qu. Khi vo trng thi ny, th bit ny c set ln 1. Vic c vo trng thi ny hay khng c khng nh bi bit FLER trong thanh ghi FCCS. V iu kin vo trng thi ny th c th tham kho phn 16.9.3, Bo v li (Error Protection).
EE
---
R/W
Bit kim tra li thc thi xa. Tr v 1 khi vng user MAT khng th xa c hay khi vic thit lp cc thanh ghi lin quan n
487
b nh flash. Nu bit ny c thit lp ln 1, th c kh nng ln l vng user MAT b xa khng hon chnh. Trong trng hp ny, thi sau khi loi b h s li (error factor), xa vng user MAT. Nu thanh ghi FMATS c ghi vo gi tr l HAA v vng user boot c chn, th mt li s pht sinh khi vic xa thc hin. Trong trng hp ny, c vng user MAT v user boot MAT nn c lp trnh trong ch boot. 0: Vic xa hon tt mt cch bnh thng. 1: Vic xa hon tt mt cch khng bnh thng. 4 FK --R/W Kim tra li thanh ghi Key flash. Kim tra gi tr trong thanh ghi FKEY (HA5) trc khi bt u vic xa, v tr v kt qu. 0: vic thit lp trong thanh ghi FKEY l bnh thng (H5A). 1: vic thit lp trong thanh ghi FKEY l khng bnh thng (gi tr khc H5A). 3 EB --R/W Bit Kim tra li la chn khi xa Kim tra liu ch s khi xa c ch nh c nm trong gii hn ca vng user MAT hay khng, v tr v kt qu. 0: vic thit lp ch s khi xa l bnh thng 1: vic thit lp ch s khi xa l khng bnh thng 2,1 0 --SF ------R/W Khng dng Cc bit ny lun tr v gi tr 0. Thnh cng/tht bi Ch ra kt qu vic xa. 0: Xa hon tt mt cch bnh thng (khng c li). 1: Xa hon tt mt cch khng bnh thng (c li xy ra). (3) Tham s tn s lp trnh/xa flash (FPEFEQ: thanh ghi a dng ER0 ca CPU) Thanh ghi FPEFEQ thit lp tn s hot ng ca CPU. Tn s hot ng cho php ca CPU trong thit b ny c gii hn l 8 MHz n 40 MHz.
488
Bit
Tn bit
Gi tr khi ng ---
R/W
c t
31 ~16 15 ~0
---
--R/W
Khng dng. Tr v gi tr 0. Cc bit thit lp tn s. Cc bit ny thit lp tn s hot ng ca CPU. Khi chc nng nhn PLL c s dng, thit lp tn s nhn. Gi tr thit lp phi c tnh ton nh sau: 1. Tn s hot ng c tnh theo n v MHz m phi c lm trn thnh mt s vi 3 k s thp phn v c hin th di dng mt s vi 2 k s thp phn. 2. Gi tr c nhn vi 100 c chuyn thnh s nh phn v c ghi vo FPEFEQ (thanh ghi a dng ER0) V d, khi tn s hot ng ca CPU l 33.000MHz th gi tr nh sau: 1. S vi 3 ch s thp phn ca 33.000 c lm trn 2. Gi tr 33.00 x 100 = 3300 c chuyn sang s nh phn B0000 1100 1110 0100 (H0CE4) c thit lp vo thanh ghi ER0.
F15~F0 ---
(4) Tham s vng a ch nhiu mc ch flash (FMPAR: thanh ghi a dng ER1 ca CPU) FMPAR lu a ch bt u ca ch lp trnh trn vng user MAT. Khi mt a ch trong mt vng khng thuc vng b nh flash c thit lp, hay a ch bt
489
u ca vng ch lp trnh khng tng thch vi 128byte, th mt li s pht sinh. Li pht sinh c ch nh bi bit WA trong thanh ghi FPFR.
Bit
Tn bit
Gi tr khi ng
R/W
c t
31 ~0
MOA31 --~ MOA0
R/W
Cc bit ny lu a ch bt u ca ch lp trnh trn vng user MAT. Vic lp trnh 128-byte lin tc c thc thi bt u t a ch bt u c ch nh ca vng user MAT. V vy, a ch bt u c ch nh ca ch lp l tng thch vi 128-byte, v cc bit t MOA0 n MOA6 l lun c xa.
(5) Tham s ch d liu nhiu mc ch flash (FMPDR: thanh ghi a dng ER0 ca CPU) FMPDR lu tr a ch bt u trong vng m lu tr d liu s c lp trnh trong vng user MAT. Khi ch lu tr d liu chng trnh l b nh flash, th mt li s pht sinh. Li pht sinh c ch nh bi bit WD trong thanh ghi FPFR.
Bit
Tn bit
Gi tr
R/W
c t
490
khi ng 31 ~0 MOD31 --~ MOD0 R/W Cc bit ny lu a ch bt u ca vng m lu d liu lp trnh cho vng user MAT. D liu lin tc 128-byte c lp trnh cho vng user MAT bt u t a ch bt u xc nh
(6) Tham s chn khi flash xa (FEBS: thanh ghi a dng ER0 ca CPU) Tham s FEBS ch nh ch s khi xa. Ch mt ch s khi c php ch nh ti mt thi im.
Bit
Tn bit
Gi tr khi ng -------------------------
R/W
c t
31 ~12 11 10 9 8 7 6 5 4 3 2 1
--EBS11 EBS10 EBS9 EBS8 EBS7 EBS6 EBS5 EBS4 EBS3 EBS2 EBS1
--R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Khng dng Cc bit ny nn c xa. Cc bit ch nh khi xa Cc bit ny thit lp ch s khi xa (ch s ny nm trong gii hn t 0 n 11). Ch s 0 tng ng vi khi EB0 v 11 tng ng vi khi EB11. Li s pht sinh nu mt ch s khng thuc khong 0 n 11 c thit lp.
491
EBS0
---
R/W
16.7.3 Thanh ghi m phng RAM (RAMER) Thanh ghi RAMER ch nh vng user MAT c ph ln bi mt phn ca RAM on-chip (HFFA000 n HFFAFFF) khi hot ng m phng vic lp trnh cho vng user MAT. Thanh ghi RAMER nn c thit lp trong ch user hay trong ch user program. m bo vic m phng mt cch chn thc, th b nh MAT c m phng phi khng c truy xut tc th sau khi thay i ni dung ca thanh ghi RAMER. Khi b truy xut vo khong thi gian ny, s ng n ca hot ng khng c m bo.
Bit
Tn Bit ---
Gi tr khi ng 0
R/W
c t
7~4
Khng dng. y l nhng bit chi c v khng th thay i gi tr ca n.
RAMS
R/W
Bit chn RAM. La chn chc nng m phng b nh flash s dng RAM on-chip. 0: Cm chc nng m phng RAM. 1: Cho php chc nng m phng RAM (tt c cc khi ca vng user MAT l c bo v khi vic lp trnh v xa).
2 1 0
RAM2 RAM1 RAM0
0 0 0
R/W R/W R/W
Bit la chn vng b nh flash. Cc bit ny la chn vng user MAT c ph ln vi RAM on-chip khi bit RAMS = 1. Cc vng sau tng ng vi cc khi xa 4 KB. 000: H000 000 n H000 FFF (EB0) 001: H001 000 n H001 FFF (EB1) 010: H002 000 n H002 FFF (EB2) 011: H003 000 n H003 FFF (EB3) 100: H004 000 n H004 FFF (EB4) 101: H005 000 n H005 FFF (EB5)
492
110: H006 000 n H006 FFF (EB6) 111: H007 000 n H007 FFF (EB7)
16.8 Ch lp trnh on-board

Khi cc chn ch (MD0, MD1 v MD2) c thit lp ch lp trnh onboard v bt u khi ng li, CPU s chuyn sang trng thi lp trnh on-board trng thi m b nh flash on-chip c th lp trnh/xa. Ch lp trnh on-board c ba ch hot ng: ch boot, user boot, v ch user program. Bng 16.5 trnh by vic thit lp cc chn cho mi ch . Chi tit v s chuyn i trng thi ca tng ch cho b nh flash, tham kho hnh 16.2 Bng 16.5 Vic thit lp ch lp trnh on-board Thit lp ch Ch boot ngi dng Ch boot 0 1 MD1 1 0 1 MD0
Ch lp trnh ngi 1 dng 16.8.1 Ch boot
Ch boot thc thi vic lp trnh/xa vng user MAT hay vng user boot MAT bng cch s dng cc cu lnh iu khin v d liu lp trnh c truyn t my tnh thng qua kt ni giao tip ni tip SCI_4. Trong ch boot, th cng c truyn cu lnh iu khin v d liu lp trnh, v d liu lp trnh phi c chun b trong my tnh. Ch giao tip tun t c thit lp l ch giao tip bt ng b. Cu hnh h thng trong ch boot c trnh by trong hnh 16.6. Cc ngt qung c b qua trong ch boot. Cu hnh h thng user cc ngt qung khng xy ra.
Hnh 16.6 Cu hnh h thng trong ch boot. (1) vic thit lp giao tip tun t bi my ch (my tnh) Knh SCI_4 c thit lp ch giao tip bt ng b, v nh dng truyn nhn c thit lp l 8-bit d liu, 1 stop bit, v khng kim tra chn.
493
Khi c mt hot ng chuyn trng thi, chng trnh boot c nhng trong thit b ny s khi ng. Khi chng trnh boot c khi ng, th thit b s o chui tn hiu thp ca d liu giao tip tun t bt ng b (H00) c truyn mt cch lin tip bi my ch, tip l tnh ton tc bit, v iu chnh tc bit ca SCI_4 cho ph hp vi my ch. Khi vic iu chnh tc bit hon tt, th thit b ny s truyn 1 byte H00 vo my ch thng bo kt thc vic iu chnh tc bit. Khi my ch nhn c tn hiu kt thc vic iu chnh, th n s truyn 1 byte H55 cho thit b. Khi nhn c tn hiu thc thi khng bnh thng, th ch boot s c khi ng li. Tc bit c th khng c iu chnh trong gii hn cho php tuy thuc vo s kt hp ca tc bit ca my ch v tn s clock h thng ca thit b. Chnh v vy m tc truyn ca my ch v tn s hot ng clock h thng ca thit b phi c trnh by trong bng 16.6.
Hnh 16.7 Hot ng iu chnh tc bit t ng Bng 16.6 Tn s clock h thng cho hot ng iu chnh tc bit t ng Tc bit ca my ch 9,600 bps 19,200 bps Tn s clock h thng ca thit b 8 to 18 MHz 16 to 18 MHz Tn s clock ngoi 4 to 9 MHz 8 to 9 MHz
(2) S khi hot ng truyn trng thi S shuyn trng thi sau khi ch boot c khi ng c trnh by trong hnh 16.8
494
Hnh 16.8 S khi hot ng chuyn trng thi ch boot 1. Sau khi khi ng ch boot, th tc bit ca knh SCI_4 c iu chnh vi my ch. 2. Yu cu thng tin v kch thc, cu hnh, a ch bt u, v trng thi h tr ca vng user MAT c truyn vo my ch. 3. Sau khi cc yu cu kt thc, th tt c cc vng user MAT v user boot MAT u t ng b xa. 4. Khi cc thng bo chun b lp trnh c nhn th thit b s vo trng thi ch d liu lp trnh. a ch bt u ca ch lp trnh v d liu lp trnh phi c truyn sau khi lnh lp trnh c truyn. Khi vic lp trnh hon tt, th a ch ca vng ch lp trnh phi c thit lp HFFFF FFFF v truyn i. Sau , t trng thi ch lp trnh, thit b s c tr v trng thi ch cu lnh lp trnh/xa. Khi cc thng bo chun b xa c nhn, thit b s vo trng thi ch d liu khi xa. Ch s khi xa phi c truyn sau khi truyn cu lnh xa. Khi hot ng xa hon tt, ch s khi xa phi c
495
thit lp l HFF v truyn i. Sau , t trng thi ch d liu xa, khi d liu c tr v trng thi ch cu lnh lp trnh/xa. Hot ng xa phi c thc thi khi khi c ch nh c lp trnh, m khng cn khi ng li sau khi vic lp trnh c thc thi trong ch boot. Khi vic lp trnh c th c thc hin bi ch mt hot ng, tt cc cc khi u c xa trc khi vo trng thi ch cu lnh lp trnh/xa hay mt cu lnh khc no . V vy trong trng hp ny, hot ng xa s khng c yu cu. Cc cu lnh khng phi l cu lnh lp trnh/xa thc thi vic kim tra khi, kim tra khi (kim tra xa), v c b nh ca vng user MAT/user boot MAT v t c thng tin trng thi hin ti. Vic c b nh ca vng user MAT/user boot MAT ch c th c c d liu c lp trnh sau khi tt c cc vng user MAT/user boot MAT c t ng xa. 16.8.2 Ch User Program Vic lp trnh/xa vng user MAT c thc thi bi vic download chng trnh on-chip. Vng user boot MAT khng th c lp trnh/xa trong ch user program. Tin trnh lp trnh/xa c trnh by trong hnh 16.9. V mc cao ca in th c p vo b nh flash trong c qu trnh lp trnh/xa, nn mt hot ng chuyn trng thi sang trng thi khi ng hay ch standby phn cng s khng c thc hin trong qu trnh lp trnh. Hot ng chuyn trng thi sang trng thi khi ng hay ch standby phn cng trong qu trnh lp trnh/xa c th lm h b nh flash. Nu mt tn hiu nhp yu cu reset, th hot ng reset phi c gii phng sau khi chu k nhp reset t nht l 100 s.
Hnh 16.9 Quy trnh lp trnh/xa (1) Bn a ch khi hot ng lp trnh/xa c thc thi Cc phn ca tin trnh lp trnh c thc hin bi use, nh yu cu download, tin trnh lp trnh/xa, v quyt nh ca kt qu, phi c thc thi trong RAM onchip. V chng trnh on-chip c download l c nhng trong RAM on-chip, nn phi chc chn rng chng trnh on-chip v tin trnh lp trnh l khng ph (overlap). Hnh 16.10 trnh by vng m chng trnh on-chip s c download.
496
Hnh 16.10 Bn RAM khi hot ng lp trnh/xa ang c thc thi. (2) Quy trnh lp trnh trong ch user program Quy trnh download chng trnh on-chip, khi ng, v lp trnh c trnh by trong hnh 16.11
Hnh 16.11 Quy trnh lp trnh trong ch user program.

497
Quy trnh lp trnh phi c thc thi trong mt vng khng phi l vng b nh flash m s c lp trnh. Vic thit lp bit SCO trong thanh ghi FCCS ln 1 yu cu download phi c thc thi trong RAM on-chip. Cc vng m c th c thc thi (RAM on-chip, user MAT, v vng nh m rng) trong nhng bc ca quy trnh lp trnh c trnh by trong phn 16.8.4, Vng lu tr v lp trnh cho d liu lp trnh. Nhng c t sau gi thit rng vng c lp trnh l vng user MAT. D liu lp trnh cho hot ng lp trnh lun l 128 byte. Khi d liu lp trnh vt qu 128byte, th a ch bt u ca ch lp trnh v cc tham s d liu lp trnh s c cp nht theo n v 128 byte v vic lp trnh s c lp li. Khi d liu chng trnh nh hn 128 byte, d liu khng c ngha s c thm vo c vng d liu 128 byte. Nu d liu c thm vo l HFF, th thi gian lp trnh c th c rt ngn. 1. La chn chng trnh on-chip s c download v ch s download. Khi bit PPVS trong thanh ghi FPCS c thit lp ln 1, vic lp trnh chng trnh c la chn. Nhiu chng trnh lp trnh/xa khng th c chn cng mt lc. Nu nhiu chng trnh c chn cng lc, th vic download s pht sinh li, li ny s tc ng n bit SS trong tham s DPFR. a ch bt u ca RAM on-chip ca ch lp trnh c ch nh bi thanh ghi FTDAR. 2. Ghi gi tr HA5 vo thanh ghi FKEY. Nu khng ghi gi tr HA5 vo thanh ghi ny, th bit SCO trong thanh ghi FCCS khng th c thit lp ln 1 yu cu download chng trnh on-chip. 3. Sau khi khi ng thanh ghi VBR thnh H0000 0000, thit lp bit SCO ln 1 thc hin vic download. thit lp bit SCO ln 1, tt c cc iu kin sau phi c tha mn: Ch m phng RAM b hy (b qua) Gi tr trong thanh ghi FKEY l HA5 Vic thit lp bit SCO c thc thi trn RAM on-chip Khi bit SCO c thit lp ln 1, th vic download c khi ng mt cch t ng. V bit SCO s b xa khi tin trnh lp trnh c phc hi, nn bit SCO khng th chc chn l 1 trong tin trnh lp trnh. Kt qu download c th c xc nhn bi gi tr tr v ca tham s DPFR. trnh nhng quyt nh sai, th trc khi thit lp bit SCO ln 1, thit lp mt byte ca a ch bt u ca RAM on-chip c ch nh bi FTDAR,(tham s DPFR), thnh mt gi tr khc tr v (HFF). Vng user MAT c chuyn sang vng lu chng trnh on-chip. Sau khi chng trnh c download v a ch bt u ca RAM on-chip c ch nh bi FTDAR c kim tra, th chng c truyn vo vng RAM on-chip. FPCS, FECS v bit SCO trong thanh ghi FCCS u b xa. Gi tr tr v c thit lp trong tham s DPFR
498
Sau khi vng lu tr chng trnh on-chip c tr v cho vng userMAT, th qu trnh lp trnh c phc hi. Sau , thanh ghi VBR c th c thit lp tr li. Gi tr ca cc thanh ghi a dng ca CPU l c gi li. Trong qu trnh download, khng c ngt qung no c th c chp nhn. Tuy nhin, v cc yu cu ngt qung c gi li, nn khi quy trnh lp trnh c phc hi, cc ngt qung s c yu cu. gi mt mc kim tra yu cu ngt qung th ngt qung phi tip tc c nhp vo cho n khi qu trnh download hon tt. Cp pht mt vng stack ln nht l 128 byte trn vng RAM on-chip trc khi thit lp bit SCO ln 1. Nu mt truy xut vo b nh flash c yu cu bi DTC hay DMAC trong qu trnh download, th hot ng s khng c m bo. Phi chc chn rng cc yu cu ca DTC v DMAC s khng c pht sinh. 4. FKEY c xa xung H00 bo v. 5. Kt qu download phi c chc chn bi gi tr ca tham s DPFR. Kim tra gi tr ca tham s DPFR (mt byte a ch bt u ca vng download c ch nh bi thanh ghi FTDAR). Nu gi tr ca tham s DPFR l H00, th vic download c hon tt mt cch bnh thng. Nu gi tr khng phi l H00, nguyn nhn to nn tht bi ca vic download c th c gii thch nh sau: Nu gi tr ca tham s DPFR l ging vi n trc khi download, th vic thit lp a ch bt u ca vng ch download trong thanh ghi FTDAR c th khng bnh thng. Trong trng hp ny, xc nhn vic thit lp ca bit TDER trong thanh ghi FTDAR. Nu gi tr ca tham s DPFR l khc vi gi tr trc khi download, th kim tra bit SS hay bit FK trong tham s DPFR xc nhn vic la chn chng trnh download v vic thit lp FKEY tng ng. 6. Tn s hot ng ca CPU l c thit lp bi tham s FPEFEQ khi ng. Gii hn tn s hot ng ca tham s FPEFEQ l t 8MHz n 40MHz. Khi tn s c thit lp l mt gi tr khc, mt li s c tr v cho tham s FPFR ca chng trnh khi ng v vic khi ng s khng c thc hin. Chi tit v vic thit lp tn s, tham kho phn 16.7.2 (3), Tham s tn s lp trnh/xa flash (FPEFEQ). 7. Khi ng thc thi. Chng trnh khi ng c download vi chng trnh lp trnh vo RAM on-chip. a ch bt u ca chng trnh khi ng nm vng #DLTOP+32 byte (a ch bt u ca ch download c ch nh bi FTDAR). Gi chng trnh con thc thi vic khi ng c thc hin nh sau:
499
Cc thanh ghi m rng khc R0L u c gi li trong chng trnh khi ng. Thanh ghi R0L l mt gi tr ca tham s FPFR V vng stack c s dng trong chng trnh khi ng, nn mt vng stack ln nht phi c cp pht trong RAM. Cc ngt qung c th c cho php trong qu trnh thc thi chng trnh khi ng. Phi chc chn rng vng lu chng trnh v vng stack trong RAM on-chip v cc gi tr thanh ghi l khng b ghi . 8. Gi tr tr v trong chng trnh khi ng, tham s FPFR c xc nh. 9. Tt c cc ngt qung v cc ng dng ca mt bus master khc CPU u b cm trong qu trnh lp trnh/xa. V lun c mt hiu in th p vo b nh flash trong thi gian lp trnh/xa, nn nu cc ngt qung xy ra hay cc b phn s dng bus khc khng phi l CPU chim dng bus trong khi lp trnh/xa, th to ra mt mc nh th vt qu mc in th c ch nh, v b nh flash c th b h. V vy, cc ngt qung l b cm bi vic thit lp bit 7 (bit I) trong thanh ghi code iu kin (CCR) ln 1 trong ch iu khin ngt qung 0 v thit lp cc bit I0 n I2 trong thanh ghi EXR ln B111 trong ch ngt qung 2. V vy, cc ngt qung khc NMI l b gi li v khng c thc thi. ng thi phi cu hnh h thng user m ngt qung NMI khng xy ra. Cc ngt qung m c gi li phi c thc thi sau khi vic lp trnh hon tt. Khi quyn s dng bus c trao cho mt b phn s dng bus khc (DTC hay DMAC), thit b s vo trng thi bo v li (error protection). Chnh v vy, phi chc chn rng DTC v DMAC s khng ginh bus. 10. Thanh ghi FKEY phi c thit lp l H5A v vng user MAT phi c chun b cho vic lp trnh. 11. Cc tham s c yu cu cho vic lp trnh phi c thit lp. a ch bt u ca ch lp trnh trn vng user MAT (tham s FMPAR) c thit lp trong thanh ghi a dng ER1. a ch bt u ca vng lu tr d liu chng trnh (tham s FMPDR) c thit lp trong thanh ghi a dng ER0. V d v vic thit lp tham s FMPAR: Khi mt a ch khng thuc vng user MAT c ch nh l a ch ch ca vic lp trnh, th thm ch nu chng trnh lp trnh thc thi th vic lp trnh cng s khng c thc hin v mt li s c pht sinh cho tham s FPFR. V d liu lp trnh cho mt hot ng lp trnh phi l 128-byte, nn 8 bit thp ca a ch phi c thit lp l H00 hay H80 m c th tng thch vi d liu 128 byte (ngha l cc a ch d liu lp trnh phi l bi s ca 128).
500
V d v vic thit lp tham s FMPDR: Khi ch lu tr ca d liu lp trnh l b nh flash, th thm ch l chng trnh lp trnh c thc thi th vic lp trnh cng khng c thc hin v mt li s c pht sinh cho tham s FPFR. Trong trng hp ny, th d liu lp trnh phi c truyn vo vng RAM on-chip v sau vic lp trnh mi c thc thi. 12. Vic lp trnh c thc thi. a ch bt u ca chng trnh lp trnh dc t trong vng #DLTOP + 16 (a ch bt u ca ch lp trnh c ch nh bi thanh ghi FTDAR).
Thanh ghi a dng khc R0L c gi li trong chng trnh lp trnh Thanh ghi R0L l gi tr tr v ca tham s FPFR. V stack c s dng trong chng trnh lp trnh, nn vng stack ti a 128-byte phi c cp pht trong RAM. 13. Tham s FPFR c ch nh l gi tr tr v trong chng trnh lp trnh. 14. Xc nh liu vic lp trnh ca d liu cn thit kt thc hay cha. Nu d liu nhiu hn 128 byte c lp trnh th cp nht cc tham s FMPAR v FMPDR theo n v 128 byte, v sau lp li cc bc t 11 n 14. Tng a ch ch lp trnh theo n v 128 byte v cp nht chnh xc con tr d liu lp trnh. Nu mt a ch m c lp trnh b ghi , th khng ch s pht sinh li lp trnh m cn lm h b nh flash. 15. Sau khi vic lp trnh hon tt, xa FKEY v ch nh ch bo v phn mm. Nu thit b c khi ng li bi mt tn hiu reset ngay lp tc sau khi vic lp trnh hon tt, th phi m bo rng khon tn hiu reset t nht phi l 100 s (khon m RES = 0). (3) Tin trnh xa trong ch User Program Tin trnh download chng trnh on-chip, khi ng, v xa c trnh by trong hnh 16.12.
501
Hnh 16.12 Tin trnh xa trong ch User Program Chng trnh th tc phi c thc thi trong mt vng khc vi vng user MAT s c xa. Vic thit lp bit SCO trong thanh ghi FCCS ln 1 yu cu vic download phi c thc thi trong RAM on-chip. Vng m c th c thc thi theo cc bc ca tin trnh lp trnh (RAM on-chip, user MAT, v vng khng gian ngoi) c trnh by trong phn 16.8.4, Chng trnh on-chip v vng lu tr d liu lp trnh. Vi vng download chng trnh on-chip, tham kho hnh 16.10. Mt tin trnh xa 1 khi. Chi tit tham kho phn chia khi, tham kho hnh 16.4. xa 2 hay 3 khi, th phi cp nh li ch s khi v lp li tin trnh xa cho tng khi. 1. La chn chng trnh on-chip c download v ch download. Khi bit PPVS trong thanh ghi FPSC c thit tp ln 1, th chng trnh lp trnh c la chn. Nhiu chng trnh lp trnh khng th c la chn cng 1 lc. Nu nhiu chng trnh c la chn, th li download s c tr v cho bit SS trong tham s DPFR. a ch bt u ca RAM on-chip ca ch download c ch nh bi FTDAR. V tin trnh c thc hin sau khi thit lp FKEY, tham kho phn 16.8.2 (2), tin trnh lp trnh trong ch User Program. 2. Thit lp tham s FEBS cn thit cho hot ng xa. Thit lp ch s khi xa (Tham s FEBS) ca vng user MAT trong thanh ghi a dng ER0. Nu mt ch s khng phi l ch s khi ca user MAT c thit lp, th s khng c khi
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no b xa thm ch nu chng trnh xa c thc thi, v mt li s c tr v cho tham s FPFR. 3. Hot ng xa c thc thi. Tng t trong qu trnh lp trnh, th a ch bt u ca chng trnh xa l vng #DLTOP + 16 byte (a ch ca ch download c ch nh bi FTDAR). gi chng trnh thc thi xa thc hin cc bc sau.
Cc thanh ghi a dng khc R0L c gi trong chng trnh xa. R0L l gi tr tr v ca tham s FPFR. V vng stack c s dng trong chng trnh xa, nn vng stack ti a 128-byte phi c cp pht trong vng RAM 4. Tham s FPFR xc nh gi tr tr v trong chng trnh xa. 5. Xc nh liu vic xa ca cc khi cn thit hon tt hay cha. Nu nhiu hn 1 khi xa, th cp nht tham s FEBS v lp li cc bc t 2 n 5. 6. Sau khi hot ng xa hon tt, xa FKEY v ch nh ch bo v phn mm. Nu thit b ny c khi ng li bi mt tn hiu reset ngay lp tc sau khi hot ng xa hon thnh, th phi chc chn rng khon tn hiu reset (khon tn hiu RES = 0) t nht l 100 s, (4) Tin trnh ca hot ng xa, lp trnh, v hot ng m phng RAM trong ch user program Bng cch thay i a ch bt u ca RAM on-chip ca vng ch download trong thanh ghi FTDAR, th chng trnh xa v chng trnh lp trnh c th c download vo cc vng RAM on-chip ring bit. Hnh 16.13 Trnh by tin trnh lp ca hot ng xa, lp trnh, v m phng RAM
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Hnh 16.13 Tin trnh lp ca hot ng xa, lp trnh, v m phng RAM trong ch User Program Trong hnh 16.13, v hot ng m phng RAM c thc hin, nn chng trnh xa/lp trnh phi c download trnh vng 4-kbyte RAM on-chip (HFFA000 n HFFAFFF). Hot ng download v khi ng c thc thi ch mt ln vo lc u. Ch cc iu sau khi thc thi chng trnh. 16.8.3 Ch user boot Vic vo chng trnh lp trnh/xa c chun b bi ngi dng cho php ch user boot (user-arbitrary boot) c s dng Ch c vng user MAT mi c th c lp trnh/xa trong ch user boot. Vic lp trnh/xa vng user boot MAT ch c th c cho php trong ch boot hoc trong ch programmer. (1) Khi ng trong ch user boot Khi bt u reset vi cc chn ch c thit lp l ch user boot, th cc chng trnh kim tra built-in s chy v kim tra trng thi ca vng user MAT v user boot MAT. Trong khi cc hm ny ang chy th cc ngt qung NMI v cc ngt qung khc u khng th c cho php. Kt tip, Vic x l bt u t a ch bt u thc thi ca vector reset trong vng user boot MAT. Vo thi im , th vng user boot MAT c chn l vng b nh MAT thc thi (FMATS = HAA)
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(2) Lp trnh cho user MAT trong ch user boot Hnh 16.14 trnh by tin trnh lp trnh cho vng user MAT trong ch user boot. S khc bit gia tin trnh lp trnh trong ch user program v trong ch user boot l vic chuyn i b nh MAT c trnh by trong hnh 16.14. lp trnh cho vng user MAT trong ch user boot, th vic x l thm c thc hin bi vic thit lp FMATS l cn thit: Vic chuyn i t vng user boot MAT sang user MAT, v vic chuyn i ngc tr li vng user boot MAT sau khi vic lp trnh hon tt.
Hnh 16.14 Tin trnh cho vic lp trnh user MAT trong ch user boot Trong ch user boot, mc d vng user boot MAT c th thy trong vng b nh flash, nhng vng user MAT l b n. V vy m vng user MAT v user boot MAT l c chuyn i qua li trong khi vng user MAT ang c lp trnh. Bi v vng user boot MAT l b n trong khi vng user MAT ang c lp trnh, nn tin trnh lp trnh phi c thc thi trong vng b nh khc vng b nh flash. Sau khi vic lp trnh hon tt, chuyn i vng MAT li trng thi ban u. Vic chuyn i b nh MAT c cho php bi vic thit lp FMATS. Tuy nhin ch rng vic truy xut vo vng b nh MAT l khng cho php cho n chi vic chuyn i b nh MAT hon tt. Trong qu trnh chuyn i, th thit b ny trong trng thi unstable, ngha l nu c mt ngt qung xy ra, ni m vector ngt
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qung b nh MAT c c l khng xc nh. thc thi vic chuyn i b nh MAT tham kho phn 16.11, Vic chuyn i gia vng user MAT v user boot MAT. Ngoi tr vic chuyn i b nh MAT, tin trnh lp trnh trong ch ny l ging vi trong ch user program. Vng m c thc thi theo tng bc trong tin trnh lp trnh (RAM on-chip, user MAT, v vng nh m rng) l c trnh by trong phn 16.8.4, Chng trnh on-chip v vng lu d liu lp trnh. (3) Vic xa vng user MAT trong ch user boot Hnh 16.15 trnh by qu trnh xa user MAT trong ch user boot. im khc bit gia qu trnh xa trong ch user program v trong ch user boot l vic chuyn i gia b nh MAT nh c trnh by trong hnh 16.15. xa vng user MAT trong ch user boot, th vic x l thm c thc hin bi vic thit lp MATS l cn thit: Vic chuyn i vng user boot MAT sang vng user MAT, v vic chuyn i ngc tr li vng user boot MAT sau khi hot ng xa hon tt.
Hnh 16.15 Tin trnh xa vng user MAT trong ch user Boot. Vic chuyn i vng b nh MAT l c cho php bi vic thit lp FMATS. Tuy nhin nn ch rng vic truy xut n b nh MAT l khng c php cho n khi vic chuyn i hon tt. Trong qu trnh chuyn i, th thit b trong trng
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thi khng n nh, ngha l nu c mt ngt qung xy ra, m t vector ngt qung b nh MAT c c l khng xc nh. thc hin vic chuyn i b nh MAT tham kho phn 16.11, Vic chuyn i gia user MAT v user boot MAT. Ngoi tr vic chuyn i b nh MAT, th tin trnh xa trong ch ny l ging vi trong ch user program. 16.8.4 Chng trnh on-chip v vng lu tr cho d liu lp trnh Trong cc c t ca ti liu ny th cc chng trnh on-chip v cc vng lu tr d liu lp trnh l c gi thit l trong RAM on-chip. Tuy nhin, chng c th thc thi trong 1 phn ca b nh flash vng nh m khng c lp trnh hay xa chng no cc iu kin sau tha mn. Chng trnh on-chip c download v thc thi trong RAM on-chip c ch nh bi FTDAR. V vy, vng RAM on-chip ny khng thch hp s dng. V chng trnh on-chip s dng mt vng stack c kch thc ti a l 128 byte. Yu cu download bi vic thit lp bit SCO trong thanh ghi FCCS ln 1 phi c thc thi t RAM on-chip bi v n s yu cu chuyn vng nh MAT. Trong mt ch hot ng m khng gian a ch m rng l khng th truy xut, v d ch single-chip, th cc chng trnh yu cu, bng vector p ng NMI, v cc hm p ng NMI nn c chuyn vo RAM on-chip trc khi bt u vic lp trnh/xa. B nh flash l khng th truy xut trong qu trnh lp trnh/xa. Vic lp trnh/xa c thc hin bi chng trnh c download vo RAM onchip. V vy, chng trnh m khi ng hot ng, bng vector p ng NMI, v cc hm x l ngt qung NMI nn c lu trong RAM on-chip. Sau khi hot ng lp trnh/xa bt u, th hot ng try xut vo b nh flash nn b cm cho ti khi FKEY b xa. Trng thi nhp reset (khon thi gian m RES = 0) nn c thit lp t nht l 100 s khi ch hot ng b thay i v hot ng reset bt u c thc thi hon tt vic xa/lp trnh. S chuyn i sang trng thi reset l b cm trong qu trnh lp trnh/xa. Khi tn hiu nhp yu cu reset, th trng thi nhp reset (RES =0) phi c duy tr t nht l 100 s trc khi tn hiu ny c gii phng. Vic chuyn i vng nh MAT bi FMATS l cn thit khi lp trnh/xa trn b nh user MAT trong ch user boot. Chng trnh m chuyn i vng nh MAT nn c thc thi t RAM on-chip. Chi tit, tham kho phn 16.11, hot ng chuyn i vng nh user MAT v user boot MAT. Phi chc chn rng vng nh MAT no ang c s dng khi chuyn i chng.
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Khi vng lu tr d liu lp trnh l nm trong vng b nh flash, th mt ngt qung s pht sinh thm ch khi d liu c lu l d liu chng trnh bnh thng. Do , d liu phi c chuyn vo RAM on-chip( t a ch m tham s FMPDR ch n vng d liu khc b nh flash.) Cc vng m trong d liu c th c lu tr v thc thi l c xc nh bi s kt hp ca cc ni dung x l, ch hot ng, v cu trc bank ca cc vng nh MAT, c trnh by cc bng 16.7 n 16.11. Bng 16.7 B nh MAT c th thc thi c Cc ni dung x l Lp trnh Xa Ch hot ng Ch User Program Tham kho bng 16.8 Tham kho bng 16.9 Ch User Boot* Tham kho bng 16.10 Tham kho bng 16.11
Ch : * Vic lp trnh/xa l c th i vi vng user MAT Bng 16.8 Vng c th s dng cho vic lp trnh trong ch User Program Vng c th lu tr/ lp trnh On-Chip RAM User MAT Chn la vng MAT. User MAT Embedded Program Storage MAT Vng lu d liu lp trnh O X* O --O --Hot ng la chn chng O trnh on-chip s c download. Hot ng ghi HA5 vo O FKEY Thc thi ghi 1 vo bit SCO O trong thanh ghi FCCS Hot ng xa FKEY Quyt nh download kt O qu O O
O X O O O O X
O O O O O O O O
Hot ng li download
Hot ng thit lp tham s O khi ng Thc thi hot ng khi O ng
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Quyt nh kt qu hot O ng khi ng Hot ng li ca khi O ng Hm x l NMI Hot ng cm ngt qung O O
O O X O O X X X X X
O O O O O O O O O O
Hot ng ghi H5A vo O FKEY Hot ng thit lp tham s O lp trnh Thc thi vic lp trnh O Quyt nh kt qu ca vic O lp trnh Hot ng li lp trnh Hot ng xa FKEY O O
Ch : * ngha l vic chuyn d liu lp trnh vo RAM on-chip trc khi cho php vng ny c s dng. Bng 16.9 Vng c th s dng cho vic xa trong ch User Program Vng c th lu tr/ lp trnh On-Chip RAM User MAT Chn la vng MAT. User MAT Embedded Program Storage MAT Hot ng la chn chng O trnh on-chip s c download Hot ng ghi gi tr HA5 O vo FKEY Thc thi vic thit lp bit O SCO ln 1 trong thanh ghi FCCS Hot ng xa FKEY O Quyt nh kt qu ca vic O download Hot ng li ca download O O O
O X
O O O
O O O
O O O
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Hot ng thit lp tham s O khi ng Thc thi vic khi ng O Quyt nh kt qu ca vic O khi ng Hot ng li ca khi O ng Hm x l NMI Hot ng cm ngt qung O O
O X O O X O O X X X X X
O O O O O O O O O O O O Chn la vng MAT. User MAT User Boot MAT Embedded Program Storage MAT ---
Hot ng ghi H5A vo O FKEY Hot ng thit lp tham s O xa Thc thi hot ng xa Quyt nh kt qu xa Hot ng kt qu li xa Hot ng xa FKEY O O O O
Bng 16.10 vng c th s dng cho vic lp trnh trong ch User Boot Vng c th lu tr/ lp trnh On-Chip RAM User MAT
Vng lu tr d liu lp O trnh Hot ng la chn chng O trnh on-chip c download. Hot ng ghi HA5 vo O FKEY Thc thi vic thit lp bit O SCO ln 1 trong thanh ghi FCCS Hot ng xa FKEY O
X*1 O
---
--O
O X
O O
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Quyt nh kt qu ca hot O ng download Hot ng li download O Hot ng thit lp tham s O khi ng Thc thi vic khi ng O Quyt nh li hot ng O khi ng Hot ng li ca vic khi O ng Hm x l ngt NMI Hot ng cm ngt qung O O
O O O X O O X O X X X X X X*2 X X O O O O O O O
O O O O O O O O
Hot ng chuyn vng O nh MAT bi FMATS Hot ng ghi H5A vo O FKEY Hot ng thit lp tham s O lp trnh Thc thi vic lp trnh O Quyt nh li ca vic lp O trnh Hot ng li lp trnh Hot ng xa FKEY O O
Vic chuyn i vng nh O MAT bi FMATS Ch :
1. Vic chuyn d liu lp trnh vo RAM on-chip trc khi cho php vng ny c s dng 2. Vic chuyn i vng MAT bi FMAT do mt chng trnh trn RAM onchip m cho php vng ny c s dng. Bng 16.11 Cc vng c th s dng xa trong ch User Boot Vng c th lu tr/ lp trnh On-Chip RAM User MAT Chn la vng MAT User MAT User Boot Embedded Program Storage
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MAT Hot ng la chn O chng trnh on-chip c download Hot ng ghi HA5 vo O FKEY Thc thi vic thit lp bit O SCO ln 1 trong thanh ghi FCCS Hot ng xa FKEY O Quyt nh kt qu ca vic O download Hot ng li download O Hot ng thit lp tham s O khi ng Thc thi hot ng khi O ng Quyt nh kt qu ca hot O ng khi ng Hot ng li khi ng Hm x l ngt NMI Hot ng cm ngt qung O O O O --O
MAT ---
O X
O O
O O O O X O O X O X X X X X X* X X O O O O O O O O
O O O O O O O O O
Vic chuyn i b nh O MAT bi FMATS Hot ng ghi H5A vo O FKEY Hot ng thit lp tham s O xa Thc thi hot ng xa Quyt nh li xa Hot ng li xa Hot ng xa FKEY O O O O
Vic chuyn i b nh O MAT bi FMATS
Ch : Vic chuyn i b nh MAT bi FMATS do mt chng trnh trn RAM on-chip m cho php vng ny c s dng.
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16.9 Bo v
C 3 loi bo v li hot ng lp trnh/xa b nh flash: bo v phn cng, phn mm v bo v li. 16.9.1 Bo v phn cng Vic lp trnh v xa b nh flash b cm hay b hon li bi trng thi cm phn cng. Trong trng thi ny, download mt chng trnh on-chip v khi ng l c th. Tuy nhin, vic lp trnh hay xa vng user MAT l khng th thc thi thm ch nu chng trnh lp trnh/xa c khi ng, th li trong vic lp trnh v xa s c pht sinh bi tham s FPFR. Bng 16.12 Bo v phn cng Chc nng b cm Download c t Bo v reset - Cc thanh ghi giao din lp trnh/xa l O c khi ng trong trng thi reset (bao gm c reset bi WDT) v vo trng thi bo v lp trnh/xa - Trng thi reset s khng c vo bi tn hiu reset s dng chn RES tr khi chn RES c gi mc thp cho n khi dao ng n nh c cp ngun. Trong trng hp c mt tn hiu reset pht sinh trong qu trnh hot ng, th gi chn RES mc thp mt khong bng chiu rng ca xung RES c ch nh bi AC. Nu mt tn hiu reset c nhp trong qu trnh lp trnh hay xa, th d liu trong b nh flash s khng c m bo. Trong trng hp ny, thc hin vic xa v sau thc thi li vic lp trnh. 16.9.2 Bo v phn mm Trng thi bo v phn mm bo v vic lp trnh/xa b nh flash bi vic cm hot ng download chng trnh lp trnh/xa, s dng key code, v bi vic thit lp RAMER. Bng 16.13 Bo v phn mm Chc nng b cm c t Download Lp O Lp trnh/xa
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trnh/xa Bo v Vo trng thi bo v lp trnh/xa khi O thng qua bit SCO trong FCCS c xa cm bit SCO download chng trnh lp trnh/xa. Bo v bi Trng thi lp trnh/xa c vo bi O FKEY v hot ng download v lp trnh/xa b cm tr khi key code cn thit c ghi vo FKEY. Bo v m Trng thi bo v lp trnh/xa khi bit O phng RAMS trong thanh ghi m phng RAM (RAMER) c thit lp ln 1. 16.9.3 Bo v li Bo v li l mt k xo b qua lp trnh hay xa. Nu mt li pht sinh trong khi lp trnh/xa b nh flash, th bit FLER trong thanh ghi FCCS c thit lp ln 1 v trng thi bo v li s c vo. Khi mt yu cu ngt qung, v d NMI, pht sinh trong khi lp trnh/xa Khi b nh flash c c trong khi lp trnh/xa (bao gm vic c vector hay mt c lnh (instruction fetch)). Khi mt lnh SLEEP c thc thi (bao gm trng thi standby-phn mm) trong khi ang lp trnh/xa. Khi mt b phn s dng bus khc CPU, v d DTC hay DMAC, nhn c bus trong qu trnh lp trnh/xa Bo v li s b hy bi mt reset. Ch rng tn hiu reset phi c gii phng sau khi khon tn hiu reset t nht l 100 s c p vo. V mc cao ca hiu in th c p vo b nh flash trong c qu trnh lp trnh/xa, nn mt vi hiu in th c th vn cn lu li sau khi trng thi bo v li c vo. V l do ny, nn cn thit gim thiu ri ro lm h hng b nh flash bng cch ko di khon tn hiu reset cho in tch c gii phng. S chuyn trng thi trong hnh 16.16 trnh by s thay i n trng thi bo v li v thay i t trng thi bo v li O
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Hnh 16.16 S chuyn i n trng thi bo v li
16. 10 M phng b nh flash s dng RAM

m phng thi gian thc ca d liu c ghi vo b nh flash s dng RAM on-chip, th vng RAM on-chip c ph ln vi mt vi khi b nh flash (vng user MAT) s dng thanh ghi m phng RAM (RAMER). Vng b ph ln c th c truy xut t c vng user MAT c ch nh bi RAMER v vng RAM b ph. Hot ng m phng c th c thc hin trong ch user Hnh 16.17 Trnh by mt v d ca vic lp trnh hot ng m phng thi gian thc vng user MAT
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Hnh 16.17 Tin trnh m phng RAM Hnh 16.18 trnh by mt v d ca vng khi EB0 ca b nh flash ph.
Hnh 16.18 Bn a ch ca vng RAM b ph Vng nh flash m c m phng l mt vng c la chn bi cc bit RAM0 n RAM2 trong thanh ghi RAMER, cc bit ny s dng chn 8 khi, t khi EB0 n EB7 ca vng user MAT ph mt phn ca RAM on-chip vi khi EB0 m phng thi gian thc, th thit lp bit RAMS trong RAMER ln 1 v cc bit RAM2 n RAM0 c gi tr l B000. lp trnh/xa vng user MAT, th chng trnh bao gm c chng trnh download ca chng trnh on-chip phi c thc thi. Vo lc ny, th vng download phi c ch nh vng RAM b ph l khng b ghi bi vic download chng trnh on-chip. V vng m lu turned data b ph bi vng download khi FTDAR = H01, turned data phi c lu vo mt vng b nh khng s dng no trc Hnh 16.19 Trnh by mt v d v quy trnh lp trnh turned data trong khi EB0 ca vng user MAT
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Hnh 16.19 Lp trnh turned data 1. Sau khi vic chuyn i d liu hon tt, xa bit RAMS trong thanh ghi RAMER hy RAM ph. 2. Chuyn chng trnh user to ra ln vng RAM on-chip 3. Bt chng trnh th tc v download chng trnh on-chip vo RAM on-chip. a ch bt u ca ch download phi c ch n bi FTDAR vng d liu c chuyn khng b ph bi vng download. 4. Khi khi EB0 ca vng user MAT khng b xa, th chng trnh lp trnh phi c download sau khi khi EB0 b xa. Ch nh d liu c chuyn lu vo cc tham s FMPAR v FMPDR v sau thc thi chng trnh. Ch : Vic thit lp bit RAMS ln 1 lm tt c cc khi ca vng user MAT vo trng thi bo v lp trnh xa (trng thi bo v m phng) bt chp vic thit lp ca cc bit RAM0 n RAM2. Thiu iu kin ny, th chng trnh khng th c download. Khi d liu thc s c lp trnh v xa, th xa bit RAMS.
16.11 Vic chuyn i gia vng user MAT v user boot MAT
C th chuyn i gia vng user MAT v user boot MAT. Tuy nhin, quy trnh sau phi c yu cu bi v a ch bt u ca cc vng MAT l trng nhau. Vic chuyn i sang vng user boot MAT cm vic lp trnh v xa. Vic lp trnh vng user boot MAT nn c thc hin trong ch boot v ch programmer. 1. Vic chuyn i b nh MAT bi FMATS nn c thc thi t RAM on-chip. 2. Khi vic truy xut b nh MAT ngay lp tc sau khi vic chuyn i vng nh MAT bi FMATS t RAM on-chip, th vic ngay cng tng t vi vic thc thi lnh NOP trn RAM on-chip 8 ln (iu ny l trnh vic truy xut b nh flash trong khi ang chuyn vng nh MAT) 3. Nu mt ngt qung c pht sinh trong qu trnh chuyn i vng nh MAT, th s khng m bo c vng b nh MAT no s c truy xut. V
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vy lun lun che cc ngt qung trc khi thc hin chuyn vng nh MAT. Thm na phi cu hnh h thng m ngt qung NMI khng xy ra trong qu trnh chuyn vng nh MAT. 4. Sau khi vng nh MAT c chuyn i, th cn thn v bng vector ngt qung s cng c chuyn. Nu x l ngt qung l ging nhau trc v sau khi chuyn vng nh MAT, th phi chuyn hm x l ngt qung vo RAM on-chip v ch nh thanh ghi VBR vo vng bng vector ngt trn RAM onchip. 5. Kch thc b nh ca vng user MAT v user boot MAT l khc nhau. Khi truy xut vng user boot MAT, th khng c truy xut a ch vt qu 10kbyte. Nu mt hot ng truy xut b nh ln hn hay bng vi 10kbyte, th gi tr tr v s l khng xc nh.
Hnh 16.20 Chuyn i gia user MAT v user boot MAT
16.12 Ch programmer
Cng vi ch lp trnh on-board, thit b ny cng cung cp mt ch programmer vi vai tr l mt ch thm cho vic ghi v xa chng trnh v d liu. Trong ch programmer, th mt programmer PROM a dng m h tr cc loi thit b c trnh by trong bng 16.14 c th c s dng ghi chng trnh v ROM on-chip m khng c s hn ch no. Bng 16.14 Cc loi thit b c h tr trong ch programmer. Vng nh ch MAT User MAT User boot MAT Kch thc 256 kbytes 10 kbytes Loi thit b FZTAT256V5A FZTATUSBTV5A
16.13 c im k thut chun giao din giao tip tun t cho ch boot
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Chng trnh boot khi ng trong ch boot thc hin giao tip tun t s dng host v knh SCI_4 on-chip. c im k thut ca giao din giao tip tun t c trnh by nh di y. Chng trnh boot c 3 trng thi. 1. Trng thi iu chnh tc bit Trong trng thi ny, chng trnh boot iu chnh tc bit t c giao tip tun t vi host (my tnh). Vic khi ng ch boot cho php bt u chng trnh boot v iu chnh tc bit. Chng trnh nhn lnh t host (my tnh) iu chnh tc bit. Sau khi iu chnh tc bit xong, th chng trnh s vo trng thi la chn/yu cu. 2. Trng thi yu cu/la chn Trong trng thi ny, chng trnh boot p ng li cc cu lnh yu cu t host (my tnh). Tn thit b, ch clock, tc bit c la chn. Sau khi c la chn cc vic thit lp ny, chng trnh vo trng thi lp trnh/xa bi cu lnh chuyn sang trng thi lp trnh/xa. Chng trnh chuyn cc th vin c yu cu cho vic xa vo RAM on-chip v xa vng user MAT v user boot MAT trc khi chuyn trng thi. 3. Trng thi lp trnh/xa Vic lp trnh v xa bi chng trnh boot xy ra trong trng thi ny. Chng trnh boot c to thnh truyn truyn chng trnh lp trnh/xa vo RAM on-chip bi cc cu lnh t host (my tnh). Vic kim tra tng v kim tra trng (sum check, blank check) c thc hin bi vic gi cc cu lnh ny t host (my tnh). Cc trng thi chng trnh boot c trnh by hnh 16.21
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Hnh 16.21 Cc trng thi chng trnh boot (1) Trng thi kim iu chnh tc bit Tc bit c tnh bi vic do chu k ca vic truyn mt byte thp (H00) t host (my tnh). Tc bit c th b thay i bng cu lnh c mt s la chn tc mi. Sau khi tc bit c iu chnh th chng trnh boot vo trng thi yu cu v la chn. Chui iu chnh tc bit c trnh by hnh 16.22
Hnh 16.22 Chui iu chnh tc bit

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(2) Giao thc giao tip Sau khi iu chnh tc bit, th giao thc giao tip tun t gia host (my tnh) v chng trnh boot c trnh by nh di y: 1. Cc cu lnh 1-byte v cc p ng 1-byte Cc cu lnh 1-byte v cc p ng 1-byte bao gm cc yu cu v p ng (ACK) hon tt thnh cng (successful completion) 2. Cc cu lnh n-byte v cc p ng n-byte Cc cu lnh v p ng c gm c n byte d liu. Chng l s la chn v yu cu p ng Kch thc d liu chng trnh khng bao gm trong cu lnh ny bi v n c xc nh trong cu lnh khc 3. p ng li p ng li l mt p ng hng dn. N bao gm mt p ng li v mt m li v c kch thc 2 byte 4. Lp trnh 128 byte Kch thc khng c ch nh trong cu lnh. Kch thc ca n c ch nh tng ng vi mt n v lp trnh. 5. p ng c b nh p ng ny bao gm 4 byte d liu.
Hnh 16.23 nh dng giao thc giao tip. Cu lnh (1 byte): Cc cu lnh bao gm ch dn (yu cu), la chn, lp trnh, xa, v kim tra p ng (1 byte) : p ng li mt yu cu
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Size (1 byte): s lng d liu truyn bao gm cu lnh, s lng d liu, v kim tra khi. a ch (4 byte): a ch lp trnh D liu (n byte): d liu c lp trnh (kch thc c ch ra trong p ng cho yu cu n v lp trnh) Kch thc (4 byte): p ng 4-byte cho mt hot ng c b nh
(3) Cc trng thi yu cu v la chn Chng trnh boot tr v thng tin t b nh flash thng qua nhng cu lnh yu cu t my ch v thit lp m thit b, ch clock, tc bit thng qua cc cu lnh la chn ca my ch Bng 16.15 Cc cu lnh yu cu v la chn Lnh H'20 H'10 H'21 Tn lnh Yu cu thit b h tr La chn thit b Yu cu ch clock c t Yu cu i vi code thit b La chn code ca thit b Yu cu v s ch clock v gi tr ca mi clock Khi ng ch clock c la chn Yu cu v s loi tn s clock nhn, s t s nhn, v gi tr ca mi b s Yu cu v gi tr ln nht v nh nht ca clock chnh v clock ngoi vi
H'11 H'22
La chn ch clock Yu cu t s nhn
H'23
Yu cu tn s clock hot ng
H'24
Yu cu thng tin ca vng nh Yu cu v s vng nh user user boot MAT boot MAT v a ch bt u v kt thc ca mi vng MAT Yu cu thng tin ca vng user Yu cu v s vng nh user MAT MAT v a ch bt u v kt thc ca mi vng MAT Yu cu thng tin ca khi xa Yu cu thng tin ca s khi xa v a ch bt u v kt thc ca tng khi Yu cu v n v ca d liu lp trnh La chn tc bit mi
H'25
H'26
H'27 H'3F
Yu cu n v lp trnh La chn tc bit mi
522
H'40
Chuyn sang trnh/xa
trng
thi
lp Xa vng nh user MAT v user boot MAT, v chuyn sang trng thi lp trnh/xa
H'4F
Yu cu trng thi chng trnh Yu cu vo trng thi hot boot ng ca chng trnh boot
Cc lnh la chn, chn thit b (H10), la chn ch (H11), v la chn tc bit mi (H3F), nn c truyn t host (my tnh) theo th ng th t nh trn. Khi c 2 hay nhiu cu lnh la chn c truyn vo 1 ln, th cu lnh sau s hp l. Tt c cc cu lnh trn, loi tr cu lnh yu cu trng thi chng trnh boot (H4F), u s hp l cho n khi chng trnh boot nhn c cu lnh chuyn sang trng thi lp trnh/xa (H40). Host (my tnh) c th la chn cc cu lnh cn thit v thc hin yu cu trong khi cc cu lnh trn ang c truyn. H4F l hp l thm ch sau khi chng trnh boot nhn c lnh H40. (a) yu cu thit b h tr Chng trnh khi ng s tr v code thit b ca thit b c h tr v code sn phm trong p ng cho yu cu thit b h tr
Cu lnh: H20 Cu lnh H20 (1 byte): yu cu v cc thit b c h tr.
p ng, H30, (1 byte): p ng li yu cu thit b c h tr (p ng li cu lnh H20) Size (1 byte): S byte c truyn, bao gm lnh, kch thc, v checksum, l s lng d liu tp hp t s thit b c tnh, code thit b, v tn sn phm. Number of devices (1 byte): s loi thit b c h tr bi chng trnh boot. Number of characers (1 byte): s lng c tnh trong m thit b v tn ca chng trnh boot. Device code (n byte): M ASCII ca sn phn h tr Product name (n byte): tn loi chng trnh boot di dng m ASCII SUM (1 byte): kim tra tng (checksum)
523
Kim tra tng (checksum) c tnh m tng tt c cc gi tr t byte lnh n byte SUM l bng H00. (b) La chn thit b Chng trnh boot s thit lp thit b c h tr thnh m thit b c ch nh. Chng trnh s tr v m thit b c la chn p ng yu cu sau khi thit lp c thc hin.
Lnh, H10, (1 byte): La chn thit b Size (1 byte): s lng d liu m thit b N c c nh l 4 Device code (4 byte): M thit b (m ASCII) c tr v khi c yu cu thit b c h tr SUM (1 byte): Kim tra tng
p ng, H06, (1 byte): p ng cho cu lnh la chn thit b ACK s c tr v khi m thit b l trng khp
p ng li, H90, (1 byte): p li cho cu lnh la chn thit b ERROR:(1 byte) : m li H11: li kim tra tng H21: Li m thit b, c ngha l, m thit b khng trng khp.
(c) Yu cu ch clock Chng trnh boot s tr v cc ch clock c h tr p ng cho yu cu ch clock - Cu ln, H21, (1 byte): Yu cu v ch clock
- p ng, H31, (1 byte): p ng li yu cu ch clock - Size (1 byte): S lng d liu m tng trng cho s ch v ch - Number of clock modes (1 byte): s ch clock c h tr H00 l ch ch khng c clock hay thit b cho php c ch clock - Mode (1 byte): Gi tr ca ch clock c h tr (v d H01 ngha l ch clock 1)
524
- SUM (1 byte): kim tra tng (d) La chn ch clock Chng trnh boot s thit lp ch clock. Chng trnh s tr v thng tin ch clock c la chn sau khi vic thit lp ny c thc hin. Cu lnh la chn ch clock s c truyn sau cu lnh la chn thit b.
Cu lnh, H11, (1 byte): la chn ch clock Size (1 byte): s lng d liu m miu t cc ch Mode (1 byte): Mt ch clock tr v p ng cho yu cu ch clock c h tr. SUM (1 byte): Kim tra tng p ng, H06, (1 byte): p ng li cu lnh la chn ch clock ACK s c tr v khi ch clock l trng khp.
p ng li, H91, (1 byte): p ng li cu lnh la chn ch c clock khi c li ERROR: (1 byte) m li H11: li kim tra tng (checksum error) H22: Li ch clock, ngha l ch clock khng trng khp Thm ch nu ch s ch clock l H00 v H01 do mt yu cu ch clock, th ch clock phi c la chn s dng nhng gi tr tng ng ny.
(e) Yu cu t s nhn Chng trnh boot s tr v t s chia v nhn c h tr
Cu lnh, H22, (1 byte): yu cu t s nhn
p ng, H32, (1 byte): p ng li yu cu t s nhn. Size (1 byte): lng d liu m tng trng cho ngun clock v t s nhn.
525
Number of types (1 byte): S loi clock nhn c h tr. (ngha l khi c 2 loi clock nhn, m l clock chnh v clock cho ngoi vi, th s loi s l H02)
The number of multiplication ratios (1 byte): S t s nhn cho mi loi Multiplication ratio (1 byte) T s nhn: Gi tr ca t s nhn (ngha l khi tn s clock nhn vi 4 th t s nhn s l H04) T s chia: l mt gi tr ngc ca t s chia, ngha l gi tr b (v d khi clock b chi 2 th gi tr ca t s chia s l HFE. HFE= D-2)
SUM (1 byte): Kim tra tng.
(f) yu cu tn s clock hot ng Chng trnh boot s tr v s tn s clock hot ng, v gi tr ln nht v nh nht
Cu lnh, H23, (1 byte): yu cu v tn s clock hot ng
p ng, H33, (1 byte): p ng cho yu cu tn s clock hot ng Size (1 byte): S byte tng ng vi gi tr ln nht, nh nht, v s tn s Number of operating clock frequencies (1 byte): S loi tn s clock hot ng c h tr (v d khi c 2 loi tn s clock hot ng, l tn s clock chnh v clock ngoi vi, th s loi s l H02) Minimum value of operating clock frequencies (2 byte): gi tr nh nht ca tn s clock nhn v chia Gi tr ln nht v nh nht ca tn s hot ng c th hin theo MHz, ng n n 1 phn trm ca MHz, v c nhn 100 (v d khi gi tr l 17.00 Mhz, n s l 2000, m l H07D0).
Maximum value of operating clock frequencies (2 byte): Gi tr ln nht gia tn s clock nhn chia Cp gi tr ln nht v nh nht bng tn s hot ng. SUM (1 byte): kim tra tng
(g) yu cu thng tin vng User Boot MAT
526
Chng trnh boot s tr v s vng user boot MAT v a ch ca chng
Cu lnh, H24, (1 byte): yu cu thng tin vng user boot MAT
p ng, H34, (1 byte) p ng cho yu cu thng tin vng user boot MAT Size (1 byte): s byte m biu din s vng, a ch bt u vng, a ch kt thc vng Number of areas (1 byte): S vng user boot MAT lin tip Khi cc vng user boot MAT l lin tip, th gi tr tr v l H01. Area-start address (4 byte): a ch bt u ca vng Area-last address (4 byte): a ch kt thc ca vng S nhm d liu tng trng cho a ch ngun v ch l bng vi s vng. SUM (1 byte): kim tra tng Chng trnh boot s tr v s vng user MAT v a ch ca chng. Cu lnh, H25, (1 byte): yu cu thng tin vng user MAT
(h) yu cu thng tin ca vng user MAT
p ng, H35, (1 byte) p ng cho yu cu thng tin vng user MAT Size (1 byte): s byte m biu din s vng, a ch bt u vng, a ch kt thc vng Number of areas (1 byte): S vng user boot MAT lin tip Khi cc vng user boot MAT l lin tip, th gi tr tr v l H01. Start address area (4 byte): a ch bt u ca vng Last address area (4 byte): a ch kt thc ca vng S nhm d liu tng trng cho a ch ngun v ch l bng vi s vng. SUM (1 byte): kim tra tng
(i) Yu cu thng tin khi xa

527
Chng trnh khi ng s tr v s khi c xa v a ch ca chng.
Lnh, H26, (1 byte): Yu cu v thng tin khi xa
p ng, H36, (1 byte): p ng li yu cu s khi xa v a ch Size (3 byte): S byte m tng trng cho s khi, a ch bt u khi, a ch kt thc khi Number of blocks (1 byte): S khi c xa Block start address (4 byte): a ch bt u ca mt khi Block last address (4 byte): a ch kt thc ca mt khi SUM (1 byte): kim tra tng Chng trnh boot s tr v n v lp trnh c s dng cho d liu lp trnh Lnh, H27, (1 byte): Yu cu v n v lp trnh
(j) Yu cu n v lp trnh
p ng, H37, (1 byte): p ng yu cu n v lp trnh Size (1 byte): s byte m ch nh n v lp trnh, c c nh l 2 Programming unit (2 byte): Mt n v cho vic lp trnh y l n v cho hot ng nhn ca lp trnh SUM (1 byte): kim tra tng Chng trnh boot s thit lp mt tc bit mi v tr v tc bit mi
(k) La chn tc bit mi S la chn ny nn c truyn sau khi truyn cu lnh la chn ch clock
Cu lnh, H3F, (1 byte): La chn tc bit mi
528
Size (1 byte): S byte m tng trng cho tc bit, tn s nhp, s t s nhn v t s nhn Bit rate (2 byte): Tc bit mi Mt phn trm ca gi tr (v d khi gi tr l 19200 bps, th n s l 192, ngha l H00C0)
Input frequency (2 byte): tn s ca clock nhp cho chng trnh boot. N l ng n n 1 phn trm v c biu din theo MHz c nhn vi 100 (v d khi gi tr l 20.00 MHz, th n s l 2000, ngha l H07D0).
Number of multiplication ratios (1 byte) s t s nhn m c th thit lp cho thit b Multiplication ratio 1 (1 byte): gi tr ca t s nhn hay chia cho tn s hot ng chnh T s nhn (1 byte): gi tr ca t s nhn (v d khi tn s clock c nhn vi 4, th t s nhn s l H04) T s chia: Ngc li gi tr t s chia, ngha l s b (v dng khi tn s clock b chia 2 th, gi tr t s chia s l HFE. HFE= D-2)
Multiplication ratio 2 (1 byte): gi tr ca t s nhn hay chia cho tn s ca ngoi vi T s nhn (1 byte): Gi tr ca t s nhn (v d khi xung clock c nhn vi 4, th t s nhn s l H04) T s chia: Ngc li gi tr t s chia, ngha l s b (v dng khi tn s clock b chia 2 th, gi tr t s chia s l HFE. HFE= D-2)
SUM (1 byte): kim tra tng
p ng, H06, (1 byte): p ng li la chn tc bit Khi c th thit lp tc bit, th p ng s l ACK.
p ng li, HBF, (1 byte): p ng li cho la chn tc bit mi ERROR: (1 byte): m li H11: li kim tra tng H24: Li la chn tc bit Tc khng hp l H25: li tn s nhp Tn s nhp ny khng nm trong gii hn c ch nh H26: Li t s nhn
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T s khng trng khp vi t s hp l H27: Li tn s hot ng Tn s khng nm trong gii hn c ch nh (4) Kim tra d liu nhn Cc phng thc kim tra d liu nhn c lit k bn di 1. Tn s nhp Gi tr nhn ca tn s nhp c kim tra chc chn rng n nm trong gii hn t tn s nh nht n ln nht m khp vi ch clock hot ng ca thit b c ch nh. Khi gi tr nm ngoi gii hn ny, th mt ngt qung s c pht sinh. 2. T s nhn Gi tr nhn c ca t s nhn hay chia c kim tra chc chn rng n trng khp vi ch clock ca thit b c ch nh. Khi gi tr vt ra khi gii hn ny, th mt li tn s nhp s c pht sinh. 3. Li tn s hot ng Tn s hot ng c tnh ton t gi tr nhn c ca tn s nhp v t s nhn hay chia. Tn s nhp l tn hiu nhp vo thit b v thit b c hot ng theo tn s hot ng. Biu thc c cho di y: Tn s hot ng = tn s nhp x t s nhn Tn s hot ng = tn s nhp t s chia Tn s hot ng c tnh ton s c kim tra chc chn rng n nm trong gii hn gia tn s nh nht v ln nht m thch hp vi ch clock ca thit b c ch nh. Khi gi tr ny vt ra khi gii hn, th mt li tn s hot ng s c pht sinh. 4. Tc bit d dng cho vic kim tra li, th gi tr (n) ca clock la chn (CKS) trong thanh ghi ch tun t (SMR), v gi tr N trong thanh ghi tc bit (BRR), m c tm t tc clock hot ng ngoi vi (f) v tc bit (B), v s dng tnh ton t l li chc chn rng n nh hn 4%. Nu li l ln hn 4%, th mt li tc bit s c pht sinh. T l li c tnh ton s dng cng thc di y: hay
Khi tc bit mi c la chn, th tc s c thit lp trong thanh ghi sau khi gi ACK p ng li. Host (my tnh) s gi mt ACK vi tc bit mi xc nhn v chng trnh boot s p ng vi tc .
530
Xc nhn, H06, (1 byte): Xc nhn mt tc bit mi p ng, H06, (1 byte): p ng li xc nhn tc bit mi Chui la chn tc bit mi c trnh by trong hnh 16.24
Hnh 16.24 Chui la chn tc bit mi (5) Chuyn sang trng thi lp trnh/xa Chng trnh boot s chuyn chng trnh xa, v xa cc vng user MAT v user boot MAT. Khi kt thc vic xa ny, ACK s c tr v v s vo trng thi lp trnh/xa. Host (my tnh) nn la chn m thit b, ch clock, v tc bit mi vi thit b la chn, s la chn ch clock, v cc cu lnh la chn tc bit, v sau gi cu lnh chuyn sang trng thi lp trnh/xa. Tin trnh ny nn c thc hin trc vic gi cu lnh la chn lp trnh hay d liu lp trnh.
- Cu lnh, H40, (1 byte): Chuyn sang trng thi lp trnh/xa
p ng, H06, (1 byte): p ng cho vic chuyn sang trng thi lp trnh/xa
Chng trnh khi ng s gi ACK khi vng user MAT v user boot MAT c xa bi chng trnh xa.
p ng li, HC0, (1 byte): p ng li cho vic kim tra rng vng user boot MAT M li, H51, (1 byte): Li xa Mt li xy ra v vic xa s khng c hon thnh
(6) Li lnh
531
Li lnh s pht sinh khi c mt cu lnh khng xc nh, th t ca cu lnh khng ng, hay mt cu lnh khng th c chp nhn. V d, Vic pht ra mt cu lnh la chn ch trc khi mt cu lnh la chn thit b hay mt cu lnh yu cu sau khi cu ln chuyn sang trng thi lp trnh/xa.
p ng li, H80, (1 byte): li lnh Lnh, Hxx, (1 byte): lnh nhn c Th t ca cc lnh trong trng thi la chn yu cu c trnh by di y: 1. Mt yu cu thit b h tr nn c thc hin tm hiu v cc thit b c h tr 2. Thit b nn c la chn t gia cc thit b c c t bi thng tin tr v v thit lp vi cu lnh la chn thit b (H10) 3. Yu cu ch clock (H21) nn c thc hin tm hiu v cc ch clock c h tr 4. Ch clock nn c la chn t cc ch c c t t thng tin tr v v sau thit lp ch clock 5. Sau khi la chn thit b v ch clock, tm hiu v thng tin cn thit khc nn c thc hin, v dng nh yu cu t s nhn (H22) hay yu cu tn s hot ng (H23), cc yu cu cn thit cho vic la chn tc bit mi 6. Mt tc bit mi cn c la chn vi cu lnh la chn tc bit mi (H3F), thng qua thng tin tr v v cc t s nhn v cc tn s hot ng. 7. Sau khi la chn thit b v ch clock, thng tin v vng user boot MAT, v vng user MAT nn c thc hin yu cu v thng tin cc vng user boot MAT (H24), yu cu v thng tin cc vng user MAT (H25), yu cu thng tin khi c xa (H26), v yu cu n v lp trnh (H27). 8. Sau khi thc hin cc yu cu v la chn mt tc mi, th thc hin cu lnh chuyn sang trng thi lp trnh/xa (H40). Chng trnh boot sau s vo trng thi lp trnh/xa.
(7) Th t lnh
(8) Trng thi lp trnh xa Mt cu lnh la chn vic lp trnh lm cho chng trnh boot la chn phng thc lp trnh, cu lnh lp trnh 128-byte s thc hin vic lp trnh b nh vi d liu, v cu lnh la chn hot ng xa v cu lnh la chn khi xa s xa khi. Bng 16.16 Lit k cc cu lnh lp trnh/xa. Bng 16.16 Cc cu lnh lp trnh/xa Cu lnh Tn lnh c t
532
H'42 H'43 H'50 H'48 H'58 H'52 H'4A H'4B H'4C H'4D H'4C
La chn vic lp trnh vng user Chuyn sang chng trnh lp boot MAT trnh cho vng user boot MAT La chn vng lp trnh user MAT Lp trnh 128-byte La chn hot ng xa Xa khi c b nh Chuyn sang vng lp trnh user MAT. Lp trnh 128 byte d liu Chuyn chng trnh xa Xa mt khi d liu c ni dung ca b nh
Kim tra tng vng user boot MAT Kim tra tng ca vng user boot MAT Kim tra tng vng user MAT Kim tra tng vng user MAT Kim tra rng vng user boot MAT Kim tra d liu rng ca vng user boot MAT Kim tra rng vng user MAT Kim tra d liu rng ca vng user MAT
Kim tra rng vng user boot MAT Kim tra liu ni dung ca vng d liu user boot MAT l rng hay khng Kim tra rng vng user MAT Kim tra liu ni dung ca vng user MAT c rng hay khng
H'4D H'4F
Yu cu trng thi chng trnh Yu cu vo trng thi trng boot thi ca chng trnh boot
- Lp trnh Vic lp trnh c thc thi bi vic cu lnh la chn lp trnh v cu lnh lp trnh 128-byte u tin, host (my tnh) gi cu lnh la chn lp trnh v phng thc lp trnh v vng MAT lp trnh.C 2 la chn lp trnh, v vic la chn thng qua vng v phng thc lp trnh. 1. La chn vic lp trnh cho vng user boot MAT 2. La chn vic lp trnh cho vng user MAT Sau khi pht ra cu lnh la chn lp trnh, th host nn gi cu lnh lp trnh 128byte. Cu lnh lp trnh 128-byte m theo sau cu lnh la chn miu t d liu lp trnh thng qua phng thc c ch nh bi cu lnh la chn. Khi c nhiu hn 128-byte d liu c lp trnh, cc cu lnh 128-byte nn thc thi lp li. Vic gi mt cu lnh lp trnh 128-byte vi gi tr HFFFF FFFF l a ch s dng vic lp trnh. Khi kt thc vic lp trnh, chng trnh boot s ch vic la chn lp trnh hay xa.
533
Chui la chn lp trnh v cc cu lnh lp trnh 128-byte c trnh by trong hnh 16.25
Hnh 16.25 Chui lp trnh Xa Vic xa c thc thi bi cu lnh la chn xa v cu lnh xa khi. u tin hot ng xa c la chn bi cu lnh la chn xa v chng trnh boot sau xa khi c ch nh. Cu lnh s c thc thi lp li nu c 2 hay nhiu khi b xa. Vic gi mt cu lnh xa khi t host vi s khi l HFF s dng hot ng xa. Khi kt thc vic xa, chng trnh boot s ch cho vic la chn lp trnh hay xa Chui ca cc cu lnh la chn xa v cu lnh la chn khi xa c trnh by trong hnh 16.26
Hnh 16.26 Chui xa
534
(a) La chn lp trnh cho vng User Boot MAT Chng trnh boot s truyn mt chng trnh lp trnh. D liu c lp trnh cho cc vng user boot bi chng trnh lp trnh c truyn. Cu lnh, H42, (1 byte): La chn chng trnh lp trnh user boot
p ng, H06, (1 byte): p ng cho hot ng la chn chng trnh lp trnh user boot Khi chng trnh lp trnh c c truyn, th chng trnh khi ng s tr v ACK. p ng li: HC2 (1 byte): p ng li cho hot ng la chn lp trnh cho vng user boot MAT ERROR: (1 byte): M li H54: Li x l la chn (li truyn pht sinh v x l cha hon tt)
(b) La chn lp trnh vng user MAT Chng trnh boot s chuyn mt chng trnh la chn lp trnh user MAT. D liu c lp trnh cho cc vng user MAT bi chng trnh c truyn vo lp trnh. Cu lnh, H43, (1 byte): la chn lp trnh cho chng trnh-user
p ng, H06, (1 byte): p ng cho la chn lp trnh chng trnh-user Khi chng trnh lp trnh c truyn, th chng trnh boot s tr v ACK. p ng li: HC3 (1 byte): p ng li cho la chn lp trnh vng user boot MAT ERROR: (1 byte): M li H54: li x l vic la chn (li truyn pht sinh v vic x l cha hon tt)
(c) Lp trnh 128-byte Chng trnh boot s s dng chng trnh lp trnh c truyn vo bi hot ng la chn lp trnh lp trnh cho cc vng user boot MAT hay user MAT p ng li vic lp trnh 128-byte
535
Lnh, H50, (1 byte): Lp trnh 128-byte a ch lp trnh (4 byte): a ch bt u lp trnh Nhiu kch thc c ch nh p ng li yu cu n v lp trnh (ngha l: H00, H01, H00, H00: H00010000)
D liu lp trnh (128 byte): D liu c lp trnh Kch thc c ch nh p ng yu cu n v lp trnh. SUM (1 byte): Kim tra tng
p ng, H06, (1 byte): p ng lp trnh 128-byte. Khi kt thc lp trnh, th chng trnh khi ng s tr v ACK.
p ng li, HD0, (1 byte): p ng li cho lp trnh 128-byte ERROR: (1 byte): m li H11: Li kim tra tng H2A: Li a ch a ch c khng nm trong MAT H53: Li lp trnh Mt li lp trnh pht sinh v vic lp trnh khng th tip tc
a ch c ch nh nn trng khp vi n v ca d liu lp trnh. V d, khi lp trnh theo n v 128-byte, th 8 bit thp ca a ch nn l H00 hay H80. Khi c t hn 128 byte d liu c lp trnh, th host nn in thm cc d liu v ngha HFF ( c d liu 128-byte). Vic gi cu lnh 128-byte vi a ch HFFFF FFFF s dng hot ng lp trnh. Chng trnh boot s thng dch n nh l s kt thc lp trnh v ch s la chn lp trnh hay xa.
Cu lnh, H50, (1 byte): Lp trnh 128-byte a ch lp trnh (4 byte): m li l HFF, HFF, HFF, HFF SUM (1 byte): kim tra tng
536
p ng, H06, (1 byte): p ng vic lp trnh 128-byte Khi kt thc vic lp trnh, chng trnh khi ng s tr v ACK.
p ng li, HD0, (1 byte): p ng li cho vic lp trnh 128-byte ERROR: (1 byte): m li H11: Li kim tra tng H53: Li lp trnh Mt li pht sinh trong lc lp trnh v vic lp trnh khng th tip tc
(d) La chn xa Chng trnh khi ng s truyn chng trnh xa. D liu user MAT s b xa bi chng trnh xa c chuyn vo.
Lnh, H48, (1 byte): la chn xa
p ng, H06, (1 byte): p ng la chn xa Sau khi chng trnh xa c truyn, th chng trnh boot s tr v ACK. p ng li, HC8, (1 byte): p ng li cho la chn xa. ERROR: (1 byte): m li H54: li x l la chn (pht sinh li truyn v x l khng hon tt)
(e) Xa khi Chng trnh boot s xa ni dung ca khi c ch nh Lnh, H58, (1 byte): xa Kch thc (1 byte): s byte m tng trng cho ch s khi xa N c c nh l 1. Ch s khi (1 byte): Ch s ca khi b xa SUM (1 byte): kim tra tng
537
p ng, H06, (1 byte): p ng xa Sau khi hon tt qu trnh xa, chng trnh boot s tr v ACK p ng li, HD8, (1 byte): p ng li ERROR (1 byte): m li H11: li kim tra tng H29: li ch s khi Ch s khi khng ng H51: Li xa Mt li pht sinh trong qu trnh xa
Khi ch s khi nhn l HFF, th chng trnh boot s dng xa v ch cu lnh la chn
Cu lnh, H58, (1 byte): xa Size (1 byte): S byte m tng trng cho ch s khi c c nh l 1 Block number (1 byte): HFF M dng xa SUM (1 byte): kim tra tng
p ng, H06, (1 byte): p ng kt thc xa (ACK) Khi hot ng xa c thc thi sau khi ch s khi HFF c gi i, th tin trnh s c thc thi t cu lnh la chn xa
(f) c b nh Chng trnh boot s tr v d liu trn a ch c ch nh
Cu lnh: H52 (1 byte): c b nh Size (1 byte): s lng d liu m tng trng cho vng, a ch c, v kch thc c (c nh 9) Area (1 byte) H00: vng user boot MAT H01: vng user MAT
538
Mt li a ch xy ra khi vic thit lp vng khng ng Read address (4 byte): a ch bt u s c c Read size (4 byte): kch thc ca d liu c c SUM (1 byte): kim tra tng
p ng: H52 (1 byte): p ng c b nh Read size (4 byte): kch thc d liu c c Data (n byte): D liu cho kch thc c t a ch bt u SUM (1 byte): kim tra tng p ng li: HD2 (1 byte): p ng li c b nh ERROR: (1 byte): m li H11: li kim tra tng H2A: Li a ch a ch c khng nm trong vng MAT. H2B: Li kch thc Kch thc c vt qua vng MAT.
(g) Kim tra li chng trnh user-boot Chng trnh boot s tr v tng byte ca ni dung ca cc byte chng trnh user-boot, nh l mt d liu 4-byte. Lnh, H4A, (1 byte): kim tra tng cho chng trnh user-boot.
p ng, H5A, (1 byte): p ng kim tra tng ca chng trnh user-boot Size (1 byte): s byte m i din cho kim tra tng C nh l 4. Checksum of user boot program (4 byte): kim tra tng cc vng user boot MAT Ton b d liu c s dng n v byte. SUM (1 byte): kim tra tng cho d liu ang c truyn
(h) Kim tra tng user-program
539
Chng trnh boot s tr v tng byte ca ni dung ca cc byte chng trnh user.
Cu lnh, H4B, (1 byte): kim tra tng cho chng trnh user
p ng, H5B, (1 byte): p ng kim tra tng chng trnh user Size (1 byte): s byte m i din cho kim tra tng c c nh l 4. Checksum of user program (4 byte): kim tra tng cc vng user MAT. Ton b d liu c obtained theo n v byte SUM (1 byte): kim tra tng cho d liu ang c truyn
(i) Kim tra rng vng user boot MAT Chng trnh boot s c kim tra liu c hay khng ton b cc vng user boot MAT l rng v tr v kt qu
Lnh, H4C, (1 byte): kim tra rng cho vng user boot MAT p ng, H06, (1 byte): p ng kim tra rng vng user boot MAT
Nu ton b cc vng user MAT l rng (HFF), th chng trnh boot s tr v ACK.
p ng li, HCC, (1 byte): p ng kim tra rng cho vng user boot MAT M li, H52, (1 byte): hot ng xa cha hon thnh.
(j) Kim tra rng vng user MAT Chng trnh boot s kim tra liu c phi ton b cc vng user MAT l rng hay khng v tr v kt qu
Cu lnh, H4D, (1 byte): kim tra rng cc vng user MAT.
p ng, H06, (1 byte): p ng kim tra rng cho cc vng user MAT Nu ni dung ca tt c cc vng user MAT l rng (HFF), th chng trnh boot s tr v ACK
540
p ng li, HCD, (1 byte): p ng li cho kim tra rng ca cc vng user MAT M li, H52, (1 byte): Hot ng xa khng c hon thnh.
(k) yu cu trng thi chng trnh boot Chng trnh boot s tr v du hiu ca trng thi hin ti v iu kin li. Yu cu ny c th c thc hin trong trng thi yu cu/la chn hay trng thi lp trnh/xa.
Lnh, H4F, (1 byte): yu cu v trng thi chng trnh boot
p ng, H5F, (1 byte): p ng yu cu trng thi chng trnh boot Size (1 byte): s byte. c c nh l 2 Status (1 byte): trng thi ca chng trnh boot ERROR (1 byte): trng thi li ERROR = 0 : hot ng bnh thng ERROR = 1 : c li xy ra.
SUM (1 byte): kim tra tng Bng 16.17 M trng thi M c t Ch la chn thit b Ch la chn ch clock Ch la chn tc bit Ch chuyn sang trng thi lp trnh/xa ( hon tt vic la chn tc bit) Trng thi lp trnh xa Ch la chn vic lp trnh/xa (hot ng xa hon thnh) Ch nhn d liu lp trnh Ch c t khi xa (hot ng xa hon thnh) Bng 16.18 M li M c t Khng c li
H'11 H'12 H'13 H'1F H'31 H'3F H'4F H'5F
H'00
541
H'11 H'12 H'21 H'22 H'24 H'25 H'26 H'27 H'29 H'2A H'2B H'51 H'52 H'53 H'54 H'80 H'FF
Li kim tra tng Li kch thc lp trnh Li m thit b khng trng khp Li ch clock khng trng khp Li la chn tc bit Li tn s nhp Li t s nhn Li tn s hot ng Li ch s khi Li a ch Li chiu di d liu Li xa Li xa cha hon thnh Li lp trnh Li x l la chn Li lnh Li xc nhn iu chnh tc bit
16.14 Ch s dng
1. Trng thi khi ng ca sn phm khi mi sn xut l trng thi b xa. Vi sn phm sa li th vic xa ny l khng xc nh. 2. mch np PROM thch hp vi ch programmer trong vi iu khin ny v phin bn np, tham kho ti liu ca socket adapter. 3. Nu socket, adapter socket, hay ch s sn phn khng trng khp vi c t, sn phm c th b h 4. S dng PROM programmer h tr thit b vi 256-kbyte b nh flash on-chip v in th lp trnh 5.0V. Khng chn HN28F101 v in th lp trnh 3.3 V vi cc tham s programmer. Ch s dng socket adapter c ch nh. 5. Khng c di chuyn chip t PROM programmer hay nhp mt tn hiu reset trong khi lp trnh/xa. Nu thc hin nh vy th c th lm h hng b nh flash. Nu mt tn hiu reset bt ng xy ra, th tn hiu reset phi c gii phng sau chu k reset t nht l 100 s. 6. B nh flash khng c truy xut cho n khi FKEY c xa sau trng thi lp trnh/xa. Nu ch hot ng c thay i v thit b ny c khi ng li bi tn hiu reset ngay lp tc sau khi lp trnh/xa hon tt, th phi
542
m bo l chu k tn hiu nhp (RES = 0) t nht l 100 s. Hot ng chuyn sang trng thi reset trong khi lp trnh/xa l b cm. Nu mt reset bt ng xy ra, th tn hiu reset phi c gii phng sau chu k tn hiu reset t nht l 100 s. 7. Khi cung cp hay ngt ngun Vcc, C nh chn RES mc thp v thit lp b nh flash vo trng thi bo v phn cng. 8. Trong ch lp trnh on-board hay ch programmer, vic lp trnh khi c n v 128-byte phi c thc hin ch 1 ln. Thc hin vic lp trnh trong ch ni m khi n v lp trnh c xa hon ton 9. Khi chip c lp trnh li vi programmer sau khi thc thi vic lp trnh hay xa trong ch lp trnh on-board, vic lp trnh t ng c thc hin sau khi hot ng xa t ng 10. Chng trnh lp trnh m bao gm cc hm khi ng v chng trnh xa m bao gm chng trnh khi ng m mi chng trnh l 4kbyte hay nh hn. Do , khi tn s clock CPU l 33 MHz, vic download mi chng trnh mt ti a xp x khon 50 s. 11. Mt chng trnh lp trnh/xa b nh flash c s dng thng trong cc vi iu khin H8S, FZTAT H8 m khng h tr download chng trnh on-chip bi vic thit lp bit SCO trong thanh ghi FCCS khng th chy trong thit b ny. Phi chc chn rng vic download chng trnh on-chip thc thi vic xa/lp trnh b nh flash tn thit b vi iu khin H8SX F-ZTAT. 12. Khng ging vi vi iu khin FZTAT H8 hay H8SX, vic nh gi s h hng ca chng trnh s khng c thc hin bi WDT trong qu trnh xa/lp trnh. Ngi dng phi t nh gi khi cn. Mt ngt qung nh k s c WDT pht ra c th c s dng nh gi. Chu k pht ngt qung nn c a vo thi gian cn nhc download chng trnh lp trnh/xa v thi gian lp trnh/xa b nh flash. 13. Khi vic download chng trnh lp trnh/xa, khng xa bit SCO ngay lp tc sau khi thit lp ln 1. Nu khng, hot ng download s khng c thc thi bnh thng. Ngay sau khi thc thi cu lnh thit lp SCO ln 1, ta phi thc thi hot ng c gi FCCS hai ln.
543
Chng 17 B nh thi watchdog (WDT)

WDT l mt b nh thi 8-bit c th xut ra mt tn hiu reset ni nu h thng b trc trc lm ngn vic CPU ghi vo b m nh thi, dn ti vic n b trn. Khi khng cn chc nng ca Watchdog, WDT c th c s dng nh mt b nh thi ngt khong. Trong hot ng nh thi ngt khong, mt ngt qung nh thi ngt khong s c pht ra khi c trn b m. Hnh 17.1 cho thy mt s khi ca WDT.
17.1 c im
C th la chn t 8 clock m nhp C th chuyn i gia ch b nh thi watchdog v b nh thi ngt khong. Trong ch b nh thi watchdog Nu b m b trn, vi iu khin ny c th t khi to li. Trong ch b nh thi ngt khong Nu b m b trn, WDT s pht ra mt ngt qung nh thi ngt khong (WOVI).
Hnh 17.1: S khi ca WDT
17.2 c t thanh ghi
544
WDT c 3 thanh ghi sau. ngn vic ghi khng mong mun, TCSR, TCNT v RSTCSR u phi c ghi vi mt phng thc khc vi cc thanh ghi thng thng. bit thm chi tit, xem phn 17.5.1, Ch v vic Truy cp thanh ghi. B m nh thi (TCNT) Thanh ghi iu khin / trng thi b nh thi (TCSR) Thanh ghi iu khin / trng thi reset (RSTCSR) 17.2.1 B m nh thi (TCNT) TCNT l mt b m c th c/ghi 8-bit. TCNT c khi to t H00 khi bit TME trong TCSR c xa v 0.
17.2.2 Thanh ghi iu khin / trng thi b nh thi (TCSR) TCSR chn ngun xung clock lm ng nhp cho TCNT v ch nh thi.
Ch : * Ch ghi c 0 vo bit ny xa c. Bit Tn bit OVF Gi tr khi ng 0 R/W c t
R/(W) C trn * Ch ra rng TCNT b trn trong ch nh thi ngt khong. Ch c ghi 0 vo bit ny xa c. [iu kin set] Khi TCNT b trn trong ch nh thi ngt khong (Chuyn t HFF sang H00) Khi s pht sinh yu cu reset ni c chn trong ch nh thi watchdog, OVF c xa t g bi reset ni. [iu kin xa] Xa bi vic c TCSR khi OVF = 1, sau ghi 0 vo OVF.
WT/I T
R/W
Chn ch nh thi La chn ch nh thi watchdog hoc nh
545
thi ngt khong s dng. 0: Ch nh thi ngt khong Khi TCNT b trn, mt ngt qung nh thi ngt khong (WOVI) c yu cu. 1: Ch nh thi watchdog Khi TCNT trn lc RSTE = 1, vi iu khin s t khi to li. 5 TME 0 R/W Cho php nh thi Khi bit ny c lp ln 1, TCNT bt u m. Khi bit ny c xa, TCNT ngng m v quay tr v H00. 4 3 2 1 0 CKS2 CKS1 CKS0 --1 1 0 0 0 R R R/W R/W R/W Khng dng. y l cc bit ch c v khng th chnh sa. Chn clock Chn ngun xung clock cho TCNT. Chu k trn cho P = 20MHz c ch nh trong ngoc. 000: Clock P 001: Clock P/64 (chu k: 819.2 us) 010: Clock P/128 (chu k: 1.6 ms) 011: Clock P/512 (chu k: 6.6 ms) 100: Clock P/2048 (chu k: 26.2 ms) 101: Clock P/8192 (chu k: 104.9 ms) 110: Clock P/32768 (chu k: 419.4 ms) 111: Clock P/131072 (chu k: 1.68 s) Ch : * Ch ghi c 0 vo bit ny xa c. 17.2.3 Thanh ghi iu khin / trng thi reset (RSTCSR) RSTCSR iu khin vic pht ra cc tn hiu reset ni khi TCNT b trn, v chn kiu tn hiu pht ra. RSTCSR c khi to l H1F bi mt tn hiu reset t chn RES, ch khng phi tn hiu reset ni ca WDT khi WDT trn.
546
Ch : * Ch ghi c 0 vo bit ny xa c. Bit Tn bit WOV F Gi tr khi ng 0 R/W c t
R/(W) C trn b nh thi watchdog * Bit ny c lp khi TCNT trn trong ch nh thi watchdog. Bit ny khng th c lp trong ch nh thi ngt khong, v ch c th ghi 0 vo. [iu kin set] Khi TCNT b trn (chuyn t HFF sang H00) trong ch nh thi watchdog. [iu kin xa] c RSTCSR khi WOVF = 1, v sau ghi 0 vo WOVF.
RSTE
R/W
Cho php reset Ch ra khi no vi iu khin ny b reset ni khi TCNT b trn trong hot ng nh thi watchdog. 0: vi iu khin khng b reset khi TCNT b trn (mc d vi iu khin khng b reset, TCNT v TCSR trong WDT vn reset). 1: vi iu khin reset khi TCNT b trn.
---
R/W
Khng dng Bit ny lun c c l 0. Gi tr ghi vo cng nn lun l 0.
4 ti 0
---
Tt c 1 R
Khng dng. y l cc bit ch c v khng th chnh sa.
Ch : * Ch ghi c 0 vo bit ny xa c.
17.3 Hot ng
17.3.1 Ch nh thi watchdog
547
s dng ch nh thi watchdog ca WDT, lp c 2 bit WT/IT v TME trong TCSR ln 1. Khi TCNT trn trong ch nh thi watchdog, bit WOVF trong RSTCSR c lp ln 1. Khi ch nh thi watchdog c chn v bit RSTE trong RSTCSR c lp ln 1, nu TCNT trn t nhin (khng b ghi bi trc trc ca h thng hoc li no khc), vi iu khin ny s c khi to li. iu ny chc chn rng TCNT khng b trn khi h thng hot ng n nh. Phn mm phi ngn TCNT trn bng cch ghi li gi tr ca TCNT (thng ghi vo H00) trc khi vic trn xy ra. Nu mt reset c gy ra bi mt tn hiu t chn RES xy ra cng lc vi reset gy ra bi vic trn WDT (TCNT trn), reset ca chn RES s c u tin cao hn v bit WOVF trong RSTCSR c xa. Tn hiu reset ni c xut ra trong 519 chu k ca P. Khi RSTE = 1, mt tn hiu khi to vi iu khin s c pht ra. V tn hiu ny s khi to thanh ghi iu khin clock h thng (SCKCR), t l nhn ca clock P cng c khi to. Khi RSTE = 0, tn hiu s khng c xut, ngha l gi tr SCKCR v t l nhn ca clock P cng khng thay i.
Hnh 17.2 Hot ng trong ch nh thi watchdog 17.3.2 Ch nh thi ngt khong s dng WDT nh mt b nh thi ngt khong, xa bit WT/IT v lp bit TME ln 1 trong thanh ghi TCSR. Khi WDT c s dng nh mt b nh thi ngt khong, mt ngt qung nh thi ngt khong (WOVI) s c pht ra mi khi TCNT trn. V vy, mt ngt qung c th c pht ra trong mi khong thi gian. Khi c trn TCNT trong ch nh thi ngt khong, mt WOVI c yu cu cng lc vi vic lp bit OVF trong thanh ghi TCSR ln 1.
548
Hnh 17.3 Hot ng trong ch nh thi ngt khong
17.4 Ngun ngt qung

Trong sut hot ng nh thi ngt khong, mi ln trn s pht ra mt WOVI. Ngt qung nh thi ngt khong c yu cu ngay khi c OVF c lp ln 1 trong thanh ghi TCSR. C OVF phi c xa trong chng trnh x l ngt qung. Bng 17.1 Ngun ngt qung WDT Tn WOVI Ngun ngt qung Trn TCNT C ngt qung OVF Kch hot DMAC Khng th
17.5 Ch s dng
17.5.1 Ch v vic truy cp thanh ghi Cc thanh ghi ca WDT khc vi cc thanh ghi khc tc v ghi. Phng thc ghi v c d liu cc thanh ghi ny c trnh by bn di. Ghi vo TCNT, TCSR, v RSTCSR: TCNT v TCSR phi c ghi bi mt cu lnh truyn d liu word. Chng khng th c ghi bi mt cu lnh truyn d liu byte. ghi, TCNT v TCSR c truy cp cng 1 a ch. Theo , vic truyn d liu c th hin trong hnh 17.4. Cu lnh truyn d liu s ghi byte d liu thp vo TCNT hoc TCSR. ghi vo RSTCSR, ta phi thc thi mt cu lnh truyn d liu word cho a ch HFFA6. Mt cu lnh truyn d liu byte khng dng c trong trng hp ny. Phng thc ghi 0 vo bit WOVF trong RSTCSR khc vi ghi vo bit RSTE trong RSTCSR (xem hnh 17.4). Nh vic truyn d liu, cu lnh truyn d liu y s xa bit WOVF, nhng s khng nh hng ti bit RSTE. ghi vo bit RSTE, ta s dng phng php u tin trong hnh 17.4. Trong trng hp ny, cu lnh s ghi gi tr bit 6 trong byte d liu thp vo bit RSTE nhng s khng lm nh hng ti bit WOVF.
549
Hnh 17.4 Ghi vo TCNT, TCSR v RSTCSR c t TCNT, TCSR v RSTCSR: Nhng thanh ghi ny c th c bng cng cch vi cc thanh ghi khc. c, TCSR c gn gi tr l HFFA4, TCNT l HFFA5, v RSTCSR l HFFA7. 17.5.2 Xung t gia vic tng v ghi b m TCNT Nu xung clock TCNT c pht ra trong chu k T2 ca qu trnh ghi TCNT, vic ghi d liu s c u tin cao hn v b m nh thi s khng tng. Hnh 17.5 cho thy hot ng ny.
Hnh 17.5 Xung t gia vic tng v ghi b m TCNT 17.5.3 S thay i gi tr cc bit CKS2 ti CKS0 Nu cc bit CKS2 ti CKS0 trong thanh ghi TCSR c ghi trong qu trnh hot ng ca WDT, li c th xy ra trong khi tng b m. WDT phi c ngng (bng cch xa bit TME) trc khi thay i gi tr cc bit CKS2 ti CKS0. 17.5.4 Chuyn i gia cc ch nh thi Nu ch nh thi c chuyn i t nh thi watchdog sang nh thi ngt khong khi WDT ang chy, li c th xy ra trong qu trnh tng b m. WDT phi c dng (xa bit TME) trc khi chuyn ch . 17.5.5 Chuyn tip t ch nh thi watchdog ti ch standby phn mm
550
Khi WDT ang hot ng trong ch nh thi watchdog, n s khng b chuyn ti ch standby phn mm cho d cu lnh SLEEP c thc thi khi bit SSBY trong SBYCR c lp ln 1. Thay v vy, n s chuyn ti ch sleep. chuyn ti ch standby phn mm, cu lnh SLEEP cn phi c thc thi sau khi dng WDT (xa bit TME). Khi WDT hot ng trong ch nh thi ngt khong, vic chuyn ti ch standby phn mm s c to ra bng cch s dng lnh SLEEP khi bit SSBY trong SBYCR c lp ln 1.
551

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I HC QUC GIA TP.

HCM TRNG I HC BCH KHOA KHOA KHOA HC V K THUT MY TNH ------------------

TP.H CH MINH,THNG 12 - 2007

Chng 1 Tng quan

Hnh 1.1 S khi ca H8SX/1582

1.3 Chn ca H8SX/1582

112 113 114 115 116 117 118 119 120

MD0 PI0 PD0/SSO0 PI1 PD1/SSI0 PD2/SSCK0 PI2 PD3/SCS0 PD4/SSO1

iu khin ch hot ng iu khin h thng

88/18 81/13 78/11 73/10 61/9 60/8 59/7 58/5 57 56 55 54 53

IRQ 2 IRQ1 IRQ 0

TIOCC3 TIOCD3 TIOCA4 TIOCB4

60, 61 61 73, 78 73 I/O

16 17 20 22 14, 15 15 16, 17 17 19, 20 20

TIOCB9 TIOCC9 TIOCD9 TIOCA10 TIOCB10

27 29, 30 30 31, 32 32 I/O

B lp trnh to xung (PPG)

PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8

Port xut nhp

Cc chn xut nhp d liu

Port xut nhp

18 13 11 10 9 8 7 5 63 66 67 68 87 89 90 91 65 51 43 3 2 1 120 119 117 116

Cc chn xut nhp d liu

Chn nhp 1 bit Cc chn xut nhp d liu 6 bit

Cc chn xut nhp d liu 3 bit

Cc chn xut nhp d liu 8 bit

PK6 PK5 PK4 PK3 PK2 PK1 PK0

2.1 Cc tnh nng

2.2 Cc ch hot ng ca CPU

Hnh 2.7 Cu trc Stack (Ch ti a)

2.3 c lnh (Fetch)

2.4 Khng gian a ch

2.5 Cc thanh ghi

Bit Tn Gi tr R/W bit khi to 7 I 1 R/W Bit mt n ngt qung

C trn c thit lp l 1 khi mt c mt s trn s hc xy ra, v c xa xung 0 nu ngc li

Khng dng Cc bt ny lun c c vi gi tr 1

R/W R/W R/W

2.6 nh dng d liu

Hnh 2.13 nh dng d liu b nh

B B B*3 --L*5 ----L*5 B/W/L 10 9

2.7.1 Cc lnh v cc ch nh a ch Bng 2.2 S kt hp ca cc cu lnh v cc ch nh a ch (1)

POP, PUSH W/L LDM, STM L

MOVA*4 chuyn EEPMOV khi MOVMD MOVSD

Php ADD, CMP B tnh s B hc B B W/L SUB B B B B W/L ADDX, SUBX

B/W/L S B/W/L S B/W/L S

INC, DEC ADDS, SUBS

MULXS, DIVXS MULS, DIVS NEG

B/W W/L B W/L

SHAL, SHAR ROTL, ROTR ROTXL, ROTXR

Thao tc trn bit

Thao tc bit R nhnh

BFLD BFST BRA/BS, 8 BRA/BC*

Bng 2.3 K hiu cc php ton c t k hiu cc php ton

Ch : * khng cho php trong vi iu khin

Bng 2.5 Cc lnh chuyn khi d liu

Bng 2.6 Cc lnh v php ton s hc

ADDS SUBS DAA DAS

Rd 1 + Rd, Rd 2 + Rd, Rd 4 + Rd Cng hay tr 1, 2, hay 4 vo 1 thanh ghi a dng

Kch thc B/W

0 + MAC Xa MAC xung 0

Rs + MAC Ti gi tr t mt thanh ghi a dng vo MAC

MAC + Rd Lu gi tr t MAC vo mt thanh ghi a dng

Bng 2.7 Cc cu lnh php ton lun l

(EAd) + (EAd) Ly b 1 ca ni dung ca mt thanh ghi a dng hay mt v tr b nh

B B B3 --L5 ----L*5 B/W/L 10 9