Project2:UARTController

BusInterfaceLecture

SerialCommunications
SerialDatalinksconvertparalleldata(sidebysideonmultipledatalines)toserial data(oneafteranotherononedataline) Usedtoefficientlysenddataoverlongerdistanceswherechannelcostsarehigher Parallel Datain
d0 d1 d2 d3 d4 d5 d6 d7

Parallel Dataout SerialData

d7d6d5d4d3d2d1d0 d0 d1 d2 d3 d4 d5 d6 d7

CommonClockSignal?
SYNCHRONOUS sourceanddestinationsharethesameclocksignalEASY! ASYNCHRONOUS sourceanddestinationareonseparateclocks samefrequency,butEDGESARENOTALIGNED.HARDER! Thisprojectisaboutasynchronouslinks

UARTPinout

System Bus

Serial Interface

UARTBlockDiagram

SummaryofTransmitOperation

DataTransmissionstepsinsourceUART
(1) HostsystemwritesdatatoDATAOUTregisterofBusInterfaceof sourceUART (2a) UARTupdatesSTATUSregisterinbusinterfacetoindicatetransmissioninprogress (2b)ContentsofDATAOUTregisteristransferredtoshiftregisterinserialtransmitterblock (3) (optional ifconfigured)SerialTransmitteraddscontrolanderrorcheck(ifany)andshiftsdataontoTXoutput (4a)Afterallbitsaretransmitted,UARTholdstheoutputhigh forone(ortwoifconfigured)bittimes(theseare calledthe"STOP"bit(s) (4b) Afterstopbitsaretransmitted,UARTupdatesSTATUSregisterto clearTransmissioninprogressindicator.

SummaryofReceiveOperation

StepsforReceivingDatainDestinationUART
(1) Serialreceiverdetectsfirstbitofincomingmessage,usesthis bittosynchronizeclockingofreceivershiftregister (2) Serialreceivershiftsinthedatabits (3) (optional ifconfigured)Serialreceiverreceiveserrorcheckbitandverifiesincomingbyte (4a) receivedbyteistransferredtoDATAINregisterofbusinterface,DataavailablebitofSTATUSregisterset. (4b) (optional ifconfigured)InterruptRequestoutputbitofbusinterfaceis set. (5a) HostoperatingsystemdevicedriveraccessestheDATAINregistertoretreivethebyte,STATUSregisterupdatedto clearDataAvailablebit. (5b) (optional ifconfigured)InterruptRequestoutputbitiscleared}

Clock

BusinterfaceBlock
registers in the programmer interface System Bus R/W logic Internal UART access logic IRQ and Status control logic

Reset Addr

Bus Interface Block Programmer Interface

Transmit Hold Register (THR) Receive Buffer Register (RBR) Line Status Register (LSR) Line Control Register (LCR) Baud Rate Select Register (BSR) Interrupt Enable Register (IER)

Data_In

CS Write Read

IRQ

Interrupt Request (IRQ) logic

SomeFundamentals: DFFandRegister Timing

CLK= EN = 1 D = 1 Q= D CLK =falling EN = 1 D = 0 Q= No Change CLK = EN = 1 D = 0 Q= D

D-Flip Flop
EN D Q Q

D D D

EN

Q Q Q Q

clk

4-bit Register
CLK = EN = 0 D = 1 Q= No Change

clk

D Q

RegistersonaSharedBus
DataIn D EN Clock ReadOut MUX D EN Q CSandRead Q DataOut

D EN Address onehot Decoder

D EN

CSandWrite

TimingforUARTRegisterRead/Write

UARTProgrammerInterfaceRegisters
These registers appear in the system address space of a running program Device drivers in the operating system move data to/from the device by reading and writing to these registers

Registers at address offset 00

RX_data[7:0] TX_data[7:0]

RECEIVERBUFFERREGISTER(RBR) Holdsthedatabytemostrecently receivedbytheSerialReceiverBlock Width:8bits SystemBusAccess:READ InternalAddressOffset:002

TRANSMITHOLDREGISTER(THR) Holdsthedatabytecurrentlybeing sentbytheserialtransmitter Width:8bits SystemBusAccess:WRITE InternalAddressOffset:002

UARTRegisters
Each register is addressed by the system bus in two ways 1) the system bus logic decodes the higher order address bits to Chip Select (CS), and 2) Addr0 and Addr1 are decoded internally to select each internal address offset

Registers at address offset 01

Bit7 -Bit6 -Bit5 THE Bit4 -Bit3 FE Bit2 PE Bit1 OVE Bit0 DAV Bit7 -Bit6 -Bit5 IE Bit4 Bit3 PARIT Y Bit2 Bit1 DB Bit0 SB

LINESTATUSREGISTER(LSR) Bit0:DataAvailable(DAV) Bit1:OverrunError(OVR) Bit2:ParityError(PE) Bit3:FramingError(FE) Bit5:TransmitHoldRegisterEmpty(THE) Width:8bits SystemBusAccess:READ InternalAddressOffset:012

LINECONTROLREGISTER(LCR)
Bit0:StopBits(SB) Bit1:DataBits(DB) Bits24:ParityBitConfiguration Bit5:InterruptEnable(IE) Width:8bits SystemBusAccess:WRITE InternalAddressOffset:012

UARTRegisters
The IRQ line sends a special signal to the processor requesting immediate attention to a condition in the device. These conditions correspond to the status bits and can be selectively enabled and disabled

Registers at address offset 10

Bit7 -Bit6 -Bit5 -Bit4 PE Bit3 OVE Bit2 FE Bit1 THE Bit0 DAV

InterruptEnableRegister(IER)R/W
TheInterruptEnableRegisterallowstheprogrammertoindividuallyenableanddisable sourcesofinterrupts Bit0:DAVenableinterruptsondataavailableintheDHRregister(DAVstatusbit) Bit1:THEenableinterruptsontransmitholdingregister(THR)emptystatusbit Bit2:FEenableinterruptsduetoframingerrors Bit3:OVEenableinterruptsduetobufferoverrunerrors Bit4:PEenableinterruptsduetoparityerrors Width:8bits SystemBusAccess:READ/WRITE InternalAddressOffset:102

UARTRegisters
The Baud Rate is the rate at which bits are shifted on to the serial link. This rate is configurable in the programmer interface and both the transmitting and receiving UART must agree

Registers at address offset 11

BAUDRATECODE[15:0]

BAUDRATECONFIGURATIONREGISTER(RBR)R/W Holdsa16bitencodedvaluethatsetsthetransmitandreceiveBaudRate(codesfor standardratesdependoninputclockfrequency,youwillbegive theselater) Width:16bits SystemBusAccess:READ/WRITE InternalAddressOffset:112

Interrupts
An interrupt is an asynchronous (to the running program) signal indicating the need for attention InyourdesignUART,InterruptRequest (IRQ)canbegeneratedby:
TransmitHoldRegisterEmpty DataAvailable FramingError OverrunError ParityError

UARTinterruptscanindividuallybe enabled/disabledviaabitmaskintheIER register Interruptsarehandledwhenaread/write ismadetotheappropriateregister

InterruptLogic
TransmitBufferEmpty DAV_Mask DataAvailable DAV_Mask

OverrunError Ovr_Mask

RST Memory Element

IRQ

ParityError P_Mask

FramingError FE_Mask

IEN

TimingForHandlingIRQ