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    Agam Pandey
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    The document discusses an electronics engineering interview that contained questions on various topics including combinational logic circuits, multiplexers, latches, flip-flops, BJTs, setup and hold times, and CMOS circuits. It provides examples of some of the questions asked such as using K-maps to simplify a combinational circuit and drawing a D latch. There were a total of fifteen questions in the two hour interview.

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    The document discusses an electronics engineering interview that contained questions on various topics including combinational logic circuits, multiplexers, latches, flip-flops, BJTs, setup and hold times, and CMOS circuits. It provides examples of some of the questions asked such as using K-maps to simplify a combinational circuit and drawing a D latch. There were a total of fifteen questions in the two hour interview.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    11 views3 pages

    Free Scale

    Uploaded by

    Agam Pandey
    The document discusses an electronics engineering interview that contained questions on various topics including combinational logic circuits, multiplexers, latches, flip-flops, BJTs, setup and hold times, and CMOS circuits. It provides examples of some of the questions asked such as using K-maps to simplify a combinational circuit and drawing a D latch. There were a total of fifteen questions in the two hour interview.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    of 3

    1. 2. 3. 4.

    Simplify a combinational circuit using k-maps. ans: a+b+c Using 2:1 mux draw a XOR gate,Dlatch,D-flipflop. One question on VLSI , manufacturing process. Which I didnt attempt. One question of BJT
    V(be)sat=.3volts V(ce)sat=.1volts Find out the voltage

    5.

    5. 6. 7.

    how to identify D pin and CLK pin of a D flip flop. Given a clock pulse, make the frequency half using a D latch. Predict the output waveform. ans : ckt was Schmitt Trigger.using opamp

    8.

    (a)Place inputs A<B<C such that A is the most critical signal. (b)Place inputs such that A is the strongest signal.

    11. Draw the state diagram to recognize the following pattern. 12. Predict the o/p waveform .

    13. one question on setup time violation and hold time violation. THERE WERE TOTAL OF FIFTEEN QUESTIONS 2 QUESTIONS WERE ON A CMOS CIRCUIT AND ITS FUNCTIONALITY WAS TO BE DETERMINED THAT I DO NOT REMEMBER INTERVIEW WAS FOR 2 HOURS , THEY ASKED CMOS , DIGITAL DESIGN, AND CROSS EXAMINED THE PAPER. ALL THE BEST

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