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  • Rajeev Institute of Technology, Hassan Dept - of E&C Engineering 1 Semester M.Tech 2 Internal Assessment

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    The document contains the questions for a digital system design exam using Verilog. It includes 7 questions related to topics like Gumnut assembly language, designing dual-port SRAM in Verilog, designing composite memories using multiple memory components, error correction codes, programmable logic devices like PALs, CPLDs and FPGAs, differences between microprocessors and microcontrollers and different types of FPGAs, designing a 4-digit decimal counter with 7-segment displays, and briefly explaining different memory types. The questions range from 4 to 8 marks each and students are asked to answer any 5 full questions out of the 7 given.

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    E&C lab

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    E&C

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    The document contains the questions for a digital system design exam using Verilog. It includes 7 questions related to topics like Gumnut assembly language, designing dual-port SRAM in Verilog, designing composite memories using multiple memory components, error correction codes, programmable logic devices like PALs, CPLDs and FPGAs, differences between microprocessors and microcontrollers and different types of FPGAs, designing a 4-digit decimal counter with 7-segment displays, and briefly explaining different memory types. The questions range from 4 to 8 marks each and students are asked to answer any 5 full questions out of the 7 given.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as doc, pdf, or txt
    46 views1 page

    Rajeev Institute of Technology, Hassan Dept - of E&C Engineering 1 Semester M.Tech 2 Internal Assessment

    Uploaded by

    ningegowda
    The document contains the questions for a digital system design exam using Verilog. It includes 7 questions related to topics like Gumnut assembly language, designing dual-port SRAM in Verilog, designing composite memories using multiple memory components, error correction codes, programmable logic devices like PALs, CPLDs and FPGAs, differences between microprocessors and microcontrollers and different types of FPGAs, designing a 4-digit decimal counter with 7-segment displays, and briefly explaining different memory types. The questions range from 4 to 8 marks each and students are asked to answer any 5 full questions out of the 7 given.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
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    Download as doc, pdf, or txt
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    RAJEEV INSTITUTE OF TECHNOLOGY, HASSAN DEPT.OF E&C ENGINEERING st 1 Semester M.

    Tech 2nd Internal Assessment Digital System Design using Verilog


    Date: 09:01:2013 Time duration: 1.30 Hour Note: Answer any five full questions 1) Write a Gumnut assembly language program to find the greater of two values. 8M Max.Marks:40

    2) Develop a Verilog model of a dual-port, 4K _ 16-bit flow through SSRAM. One port allows data to be written and read, while the other port only allows data to be read. 8M 3) a) Design a 64K X 8-bit composite memory using four 16K X 8-bit components. 4M b) Design a 1G X 8-bit composite memory using four 256M X 8-bit components. 4M 4) a) Determine whether there is an error in the ECC word 000111000100, and if so, correct it. 4M b) Differentiate between soft errors and hard errors. 4M 5) Explain the following with block diagrams a) PAL b) CPLD c) FPGAs 6) a) Differentiate the following: i) Microprocessor and micro controller ii) platform FPGA and simple FPGA

    8M 4M

    b) Use the following components to design a 4-digit decimal counter with a 7-segment LED display: two 74LS390 dual decade counters, four 74LS47 BCD to 7-segment decoders, four 7-segment displays, plus any additional gates required. 4M 7) Briefly explain the memory types 8M

    *******************ALL THE BEST***********************

    Signature of the staff (Ravi L.S)

    Signature of the HOD (Ambika.K)

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