OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Cp Ep Lm CE Li Ei La Ea Su Eu Lb Lo

T1 T2 T3 T4 T5 T6

U24:A
VCC 1 3 2 CLR ADR3 ADR2 ADR1 ADR0 D7 D6 D5 D4 D3 D2 D1 D0

VCC

SW5
Clear/Start

START

? ? ? ? ? ?

W7 W6 W5 W4 W3 W2 W1 W0

? ? ? ? ? ? ? ? ? ? ? ?

U24:B
CLEAR 4 6 VCC
? ? ? ? ? ? ? ?

5 7400

CLR

ADR3 ADR2 ADR1 ADR0

D7 D6 D5 D4 D3 D2 D1 D0

U24:C
VCC

SW1
OFF

SW3
ON

5 6 7 8

8 7 6 5 4 3 2 1

VCC

9 8 10

OFF

ON

Address Switch

OPCode / Data Switches

SW4
Write Memory

WEram Single Step

SW6

LOW

4 3 2 1

9 10 11 12 13 14 15 16

U24:D
HIGH 12 11 VCC 13 HLT 7400 1 2 13

U25:A
12

Note: The RAM has inverting outputs so this switch has also been inverted to enter the correct data. UP = Logic 0 input = Logic 1 Output from RAM DOWN = Logic 1 input = Logic 0 output from RAM (Observe W-Bus indicators for correct value)

U26:A
VCC 1 3 2 ENpc 13 11 12 1 2 3 4 CLK

U26:D

SW2
VCC ENmar Ep

SW8 SW7
Manual/Auto Manual Program/Run

U27:A

U27:B

CE ENram Program/Run Note: This extra switch was added to isolate the output of the Program Counter from the W-bus when entering data, otherwise a logic contention will occur. VCC

U26:B
Auto 4 6 5 HLT 3 4 5

U27:C U25:B
6 5 6 CLK

U25:B(C) INIT=LOW START=0 COUNT=-1 CLOCK=1

Note: The 555 timer circuit has been substituted with a virtual clock source to speed up the simulation.

W7 W6 W5 W4 W3 W2 W1 W0

Cp

U1:A
74LS107 3 Q J CLK R 2 Q K 1 12 5

U1:B
74LS107 Q J CLK R 6 Q K 8 9 3

U2:A
74LS107 Q J CLK R 2 Q K 1 12 5

U2:B
74LS107 Q J CLK R 6 Q K 8 9 11 CLK

11

13

10

13

10

CLR 12 2 5 9

U3:A
1

U3:B
4

U3:C
10

U3:D
13 7 1 2 9 10 15 14 13 12 11 CLK La CLK La

11

74LS126 ENpc

CLK OE1 OE2 E1 E2 MR

74LS173 Accumulator Q0 Q1 Q2 Q3

CLK OE1 OE2 E1 E2 MR

D0 D1 D2 D3

D0 D1 D2 D3

U11

7 1 2 9 10 15

14 13 12 11

U10
74LS173 Accumulator

3 4 5 6

Q0 Q1 Q2 Q3

CLK Lm 1 Ea 1 Ea

15 10 9 2 1 7

11 12 13 14

MR E2 E1 OE2 OE1 CLK

D3 D2 D1 D0

U4
74LS173 Memory Address Register 4 4

Q3 Q2 Q1 Q0

6 5 4 3

10

ENmar 11 15 1 13 14 10 11 6 5 3 2 12 11 12

13

E A/B

4B 4A 3B 3A 2B 2A 1B 1A

U5
74LS157 2-1 Multiplexer

U13:D
74LS126 Accumulator Output

U12:D
74LS126 Accumulator Output

4Y

3Y

2Y

ENram WEram 3 2 13 14 15 1 12 10 6 4

D7 D6 D5 D4

12

1Y

ENram WEram 3 2 13 14 15 1 12 10 6 4

D3 D2 D1 D0 10 12 13 1 2 4 5 9

13

ADR0 ADR1 ADR2 ADR3

10

Su 10 12

3 4 5 6

Su 13 1 2 4 5 9

WE ME A3 A2 A1 A0 D4 D3 D2 D1

WE ME A3 A2 A1 A0 D4 D3 D2 D1

U6
74LS89 16 X 4-bit RAM

U7
74LS89 16 X 4-bit RAM

U15:D
74LS86

U14:D
74LS86

Q4 Q3 Q2 Q1

11 9 7 5

11 9 7 5

Q4 Q3 Q2 Q1

11

Su 5 3 14 12 6 2 15 11 5 3 14 12 7 6 2 15 11 7

Carry

A0 A1 A2 A3

B0 B1 B2 B3

A0 A1 A2 A3

C0

B0 B1 B2 B3

74LS283 Full Adder (LSB) C4 C4 S0 S1 S2 S3 S0 S1 S2 S3

C0

U17

U16
74LS283 Full Adder (MSB)

4 1 13 10

4 1 13 10

CLK Li CLR

CLK Ei Li

Carry

15 10 9 2 1 7

15 10 9 2 1 7

11 12 13 14

11 12 13 14

U19:D
12 2 5 9 2 5

11

U18:D
12 10 8 11 1 3 6 4 9 74LS126 13

74LS126 13

MR E2 E1 OE2 OE1 CLK

MR E2 E1 OE2 OE1 CLK

D3 D2 D1 D0

D3 D2 D1 D0

U8
74LS173 Instruction Register (OPCode)

U9
74LS173 Instruction Register (Address) 3

1 6

4 8

10 11

Q3 Q2 Q1 Q0

Q3 Q2 Q1 Q0

Eu

6 5 4 3

I7 I6 I5 I4

6 5 4 3

CLK Lb

CLK Lb

14 13 12 11

7 1 2 9 10 15

14 13 12 11

D0 D1 D2 D3

CLK OE1 OE2 E1 E2 MR

D0 D1 D2 D3

74LS173 B Register (LSB) Q0 Q1 Q2 Q3

CLK OE1 OE2 E1 E2 MR

U21

7 1 2 9 10 15

U20
74LS173 B Register (MSB)

3 4 5 6

Q0 Q1 Q2 Q3

CLK Lo CLR

3 4 5 6

CLK Lo CLR

7 1 2 9 10 15

CLK OE1 OE2 E1 E2 MR

74LS173 Output Register Q0 Q1 Q2 Q3

CLK OE1 OE2 E1 E2 MR 8 9 11 10

D0 D1 D2 D3

D0 D1 D2 D3

U23

7 1 2 9 10 15

14 13 12 11

14 13 12 11

U22
74LS173 Output Register

3 4 5 6

Q0 Q1 Q2 Q3

VCC OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 Note: These pull-up resistors are necessary because the outputs of the 74LS89 (substitute for the 74LS189) are open collector.

I7

I6

I5

I4

U31:A
2 1

Ring Counter
CLK

U31:B
4 3 3

U36:A
74LS107 Q J CLK 1 12 5

U36:B
74LS107 Q J CLK R 6 Q K 8 9 3

U37:A
74LS107 Q J CLK R 2 Q K 1 12 5

U37:B
74LS107 Q J CLK R 6 Q K 8 9 3

U38:A
74LS107 Q J CLK R 2 Q K 1 12 5

U38:B
74LS107 Q J CLK R 10 6 Q K

U31:C
6 5

13

11

11

10

13

10

13

3 4 5 6

U31:D
12 13 T6 T5 T4 T3 T2 T1 11 13

CLR

U35:E

U35:D

Instruction Decoder
1 2 4 5

Control Matrix

10

U32:A
6 1

U35:A
2 LDA ADD SUB

9 10 12 13

U32:B
8 3

U35:B
4

OUT

10

12 12

13

10

12

13

10

12

13

12

13

U39:D
1 2 4 5 3 6 8 3 6 8

U40:D

U41:D

U42:D

10

U43:C

U33:A
6 5

U35:C
6 3 6 8 3 6 8 3 6 11 11 11 11 8 Lo

9 10

12 13

1 2 13

9 10 12 13

U33:B
8 9

U35:F
1 2 4 5 3 4 5 1 2 4 8

U44:A U34:A
6 6 8

U44:B

U45:A

U45:B

U46:A

U46:B

1 2 4 5

12

11

13

U47:A
2 4

U47:B
6

U47:C
8

U47:F
10

U47:E U47:D
2 12

HLT

U48:B U48:A
4 Eu Lb

Cp Ep

Lm

CE

Li

Ei

La

Ea

Su