Experiment No.

-2
AIM: Design,synthesis and stimulate the full adder circuit using Xilinx Software.
1. 2. 3. 4. Data flow modeling Structural flow modeling Behavioral modeling Mixed modeling

Software used: Xilinx 5.2i. Activity-1: Write VHDL code using Data Flow Modeling
RTL Schematic:

Simulation Result:

Synthesis Result: Number of Slices: Delay: Device Family: 1 out of 192 0%

8.234ns (Levels of Logic = 3) Spatan2

Activity 2: Write VHDL code using Behavioral Modeling.

RTL Schematic:

Simulation Result:

7 Utkarsh Mishra/ A5

Synthesis Result:
Number of Slices: Delay: Device Family: 1 out of 192 0%

8.234ns (Levels of Logic = 3) Spatan2

Activity 3: Write VHDL code using Structural Modeling

RTL Schematic:

Simulation Result:

Synthesis Result:
Number of Slices: Delay: Device Family: 1 out of 192 0%

8.234ns (Levels of Logic = 3) Spatan2

Activity 4: Write VHDL code using Mixed Modeling

8 Utkarsh Mishra/ A5

RTL Schematic:

Simulation Result:

Synthesis Result:
Number of Slices: 192 0% Delay: (Levels of Logic = 3) Device Family: 1 out of 8.234ns Spatan2

Conclusion:
Simulation result waveform are shown. All the modelling is having equal number of slices i.e. 1 out of 192. All the modelling is having equal amount of Delay i.e. 8.234ns.

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