VLSI DESIGN & TECHNOLOGY TITLE: TUTORIAL-7 BATCH : Cx/C2 ROLL NO : 41 REG NO : 1030309053

TUTORIAL -7 DATE: 02/03/2012

AIM: 1) HALF ADDER:

VHDL PROGRAM: library ieee; use ieee.std_logic_1164.all; entity ecd is port(a0,a1,a2,a3,a4,a5,a6,a7,cs:in bit;x,y,z:out bit); end ecd; architecture test of ecd is begin x<=(a0 or a1 or a2 or a3) and (not cs); y<=(a0 or a1 or a4 or a5) and (not cs); z<=(a2 or a4 or a6 or a0) and (not cs); end test; COMPILATION REPORT:

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VLSI DESIGN & TECHNOLOGY

TUTORIAL -7

VECTOR WAVEFORM:

2) HALF SUBTRACTOR:
VHDL PROGRAM:

library ieee; use ieee.std_logic_1164.all; entity dcd is port(a0,a1,a2,a3,a4,a5,a6,a7:out bit;x,y,z,cs:in bit); end dcd; architecture test of dcd is begin a0<=((not x) and (not y) and (not z)) and (not cs); a1<=((not x) and (not y) and z) and (not cs); a2<=((not x) and (y) and (not z)) and (not cs); a3<=((not x) and (y) and z) and (not cs); a4<=((x) and (not y) and (not z)) and (not cs); a5<=((x) and (not y) and (z)) and (not cs); a6<=((x) and (y) and (not z)) and (not cs); a7<=((x) and (y) and (z)) and (not cs); end test;

COMPILATION REPORT:

ATMIYA INSTITUTE OF TECHNOLOGY & SCIENCE

VLSI DESIGN & TECHNOLOGY

TUTORIAL -7

VECTOR WAVEFORM:

Conclusion:

Grade

Lab-In-Charge

H.O.D.

ATMIYA INSTITUTE OF TECHNOLOGY & SCIENCE