VLSI TECHNOLOGY

TITLE: Modeling of Basic Gates BATCH : Cx/C2 ROLL NO : 31 REG NO : 1030309142 DATE: /

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/2012

AIM: Modeling of Basic Gates and Verify on ESDK kit 1) AND GATE:
VHDL PROGRAM: library ieee; use ieee.std_logic_1164.all; entity and1 is port (a,b : in std_logic ; c : out std_logic); end and1; architecture and11 of and1 is begin c <= a and b; end and11; COMPILATION REPORT:

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VECTOR WAVEFORM:

2) OR GATE:
VHDL PROGRAM: library ieee; use ieee.std_logic_1164.all; entity or21 is port(a,b:in std_logic;c:out std_logic); end or21; architecture mustak of or21 is begin c<=a or b; end mustak; COMPILATION REPORT:

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VECTOR WAVEFORM:

3) NOT GATE:
VHDL PROGRAM: library ieee; use ieee.std_logic_1164.all; entity not11 is port(a:in std_logic;b:out std_logic); end not11; architecture mustak of not11 is begin b<=not a; end mustak; COMPILATION REPORT:

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VECTOR WAVEFORM:

4) NAND GATE:
VHDL PROGRAM: llibrary ieee; use ieee.std_logic_1164.all; entity nand21 is port(a,b:in std_logic;c:out std_logic); end nand21; architecture mustak of nand21 is begin c<=a nand b; end mustak; COMPILATION REPORT:

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VECTOR WAVEFORM:

5) NOR GATE:
VHDL PROGRAM: library ieee; use ieee.std_logic_1164.all; entity nor21 is port(a,b:in std_logic;c:out std_logic); end nor21; architecture mustak of nor21 is begin c<=a nor b; end mustak; COMPILATION REPORT:

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VECTOR WAVEFORM:

6) XOR GATE:
VHDL PROGRAM: library ieee; use ieee.std_logic_1164.all; entity xor21 is port(a,b:in std_logic;c:out std_logic); end xor21; architecture mustak of xor21 is begin c<=a xor b; end mustak; COMPILATION REPORT:

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VECTOR WAVEFORM:

7) XNOR GATE:
VHDL PROGRAM: library ieee; use ieee.std_logic_1164.all; entity xnor21 is port(a,b:in std_logic;c:out std_logic); end xnor21; architecture mustak of xnor21 is begin c<=a xnor b; end mustak; COMPILATION REPORT:

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VECTOR WAVEFORM:

Conclusion:

Grade

Lab-In-Charge
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H.O.D.