VLSI DESIGN & TECHNOLOGY TITLE: TUTORIAL-6 BATCH : Cx/C2 ROLL NO : 31 REG NO : 1030309142

TUTORIAL -6 DATE:03/02/2012

AIM: DESIGN MULTIPLEXER AND DEMULTIPLEXER USING

DIFFERENT STYLE

1) 2 x 1 MUX:
VHDL PROGRAM: library ieee; use ieee.std_logic_1164.all; entity mux is port(s0,a,b:in bit;z:out bit); end mux; architecture test of mux is begin z<=(s0 and a)or((not s0)and b); end test; COMPILATION REPORT:

VECTOR WAVEFORM:

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2) 2 x 1 DEMUX:
VHDL PROGRAM: library ieee; use ieee.std_logic_1164.all; entity demux is port(z,s0:in bit;a,b:out bit); end demux; architecture test of demux is begin a<=(not s0)and z; b<=s0 and z; end test; COMPILATION REPORT:

VECTOR WAVEFORM:

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3) 4 X 1 MUX:
VHDL PROGRAM:

library ieee; use ieee.std_logic_1164.all; entity mux4x1 is port(a,b,c,d,s0,s1:in bit;z:out bit); end mux4x1; architecture test of mux4x1 is component and31 is port(e,f,g:in bit;x:out bit); end component; component or41 is port(h,i,j,k:in bit;y:out bit); end component; signal t1,t2,t3,t4:bit; begin a1:and31 port map(not s1,not s0,a,t1); a2:and31 port map(not s1,s0,b,t2); a3:and31 port map(s1,not s0,c,t3); a4:and31 port map(s1,s0,d,t4); o1:or41 port map(t1,t2,t3,t4,z); end test; library ieee; use ieee.std_logic_1164.all; entity and31 is port(e,f,g:in bit;x:out bit); end and31; architecture test1 of and31 is begin x<= e and f and g; end test1; library ieee; use ieee.std_logic_1164.all; entity or41 is port(h,i,j,k:in bit;y:out bit);
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end or41; architecture test2 of or41 is begin y<=h or i or j or k; end test2;

COMPILATION REPORT:

VECTOR WAVEFORM:

4) 4 X 1 DEMUX:
VHDL PROGRAM: library ieee; use ieee.std_logic_1164.all; entity demux1x4 is port(s1,s0,z:in bit;a,b,c,d:out bit); end demux1x4; architecture test of demux1x4 is component and31 is port(p,q,r:in bit;s:out bit);
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end component; begin a1:and31 port map((not s1),(not s0),z,a); a2:and31 port map((not s1),s0,z,b); a3:and31 port map(s1,(not s0),z,c); a4:and31 port map(s1,s0,z,d); end test; library ieee; use ieee.std_logic_1164.all; entity and31 is port(p,q,r:in bit;s:out bit); end and31; architecture test1 of and31 is begin s<=p and q and r; end test1; COMPILATION REPORT:

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VECTORWAVEFORM:

5) 8 X 1 MUX:
VHDL PROGRAM: library ieee; use ieee.std_logic_1164.all; entity mux8x1 is port(a,b,c,d,e,f,g,h,s0,s1,s2:in bit;z:out bit); end mux8x1; architecture test of mux8x1 is begin process(a,b,c,d,e,f,g,h,s0,s1,s2) variable t1,t2,t3,t4,t5,t6,t7,t8:bit; begin t1:=(not s2)and(not s1)and(not s0)and(a); t2:=(not s2)and(not s1)and(s0)and(b); t3:=(not s2)and(s1)and(not s0)and(c); t4:=(not s2)and(s1)and(s0)and(d); t5:=(s2)and(not s1)and(not s0)and(e); t6:=(s2)and(not s1)and(s0)and(f); t7:=(s2)and(s1)and(not s0)and(g); t8:=(s2)and(s1)and(s0)and(h); z<=t1 or t2 or t3 or t4 or t5 or t6 or t7 or t8; end process; end test;
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COMPILATION REPORT:

VECTOR WAVEFORM:

6) 8 X 1 DEMUX:
VHDL PROGRAM: library ieee; use ieee.std_logic_1164.all; entity demux1x8 is port(s2,s1,s0,z:in bit;a,b,c,d,e,f,g,h:out bit); end demux1x8; architecture test of demux1x8 is begin process(s2,s1,s0,z) begin a<=(not s2)and(not s1)and(not s0)and z; b<=(not s2)and(not s1)and s0 and z; c<=(not s2)and s1 and(not s0)and z; d<=(not s2)and s1 and s0 and z;
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e<=s2 and(not s1)and(not s0)and z; f<=s2 and(not s1)and s0 and z; g<=s2 and s1 and(not s0) and z; h<=s2 and s1 and s0 and z; end process; end test; COMPILATION REPORT:

VECTOR WAVEFORM:

Conclusion:

Grade

Lab-In-Charge

H.O.D.

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