The document summarizes modeling a mod6 counter in VHDL. It contains the VHDL code for a mod6 counter that uses a process to increment a counter from 0 to 5 on each clock edge unless a reset signal is applied, in which case it resets to 0. The VHDL code is then compiled and a waveform simulation is run to verify the counter functions properly, incrementing from 0 to 5 before resetting. The conclusion is that the mod6 counter was successfully modeled and verified in VHDL simulation.
The document summarizes modeling a mod6 counter in VHDL. It contains the VHDL code for a mod6 counter that uses a process to increment a counter from 0 to 5 on each clock edge unless a reset signal is applied, in which case it resets to 0. The VHDL code is then compiled and a waveform simulation is run to verify the counter functions properly, incrementing from 0 to 5 before resetting. The conclusion is that the mod6 counter was successfully modeled and verified in VHDL simulation.
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The document summarizes modeling a mod6 counter in VHDL. It contains the VHDL code for a mod6 counter that uses a process to increment a counter from 0 to 5 on each clock edge unless a reset signal is applied, in which case it resets to 0. The VHDL code is then compiled and a waveform simulation is run to verify the counter functions properly, incrementing from 0 to 5 before resetting. The conclusion is that the mod6 counter was successfully modeled and verified in VHDL simulation.
Copyright:
Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online from Scribd
VLSI TECHNOLOGY TITLE: BATCH : Cy/C4 ROLL NO : 13 REG NO : 1030309058 DATE:
TUTORIAL -9 29-03-2012
Modeling of mod6 Counter
AIM: Modeling of mod6 Counter and Verify on ESDK kit
MOD6 COUNTER:VHDL PROGRAM:
Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity mod6_counter is Port (rst, clk: in bit; count: buffer integer range 0 to 5); End mod6_counter; Architecture test of mod6_counter is Begin Process Begin Wait until clk event and clk = '1'; If (rst = '1' or count >= 5) then Count <=0; Else Count <= count + 1; End if; End process; End test;