HP Dv4000 - Quanta Ct3

5
Model
MODEL
REV
CT3/5 MB
1A
31CT3MB0015
31CT3MB0031
CHANGE LIST
Page
PAGE 2 --- Enable CLK48M from clokc generator for the PLL circuit of 7411, and disable the
ocsillator circuit of PCI7411 PLL.
PAGE 3 --- Remove H/W shutdown circuit that supported ADM1032.
PAGE 4 --- Use X7R type to replace Y5V type for CPU Decoupling/Bypass capacitor.
PAGE 10 --- Add a terminal resistor R706 for -CODE_RST# to improve signal quality.
PAGE 11 --- 1. Add a 10K pull-up resistor on MCH_SYNC# for booting.
2. Change the power plane of PCIE_WAKE# from 3VSUS to 3V_S5 to solve system can't
turn off issue.
3. Change the power plane of ICH_THRM# and SCI_# from 3VSUS to +3V to reduce
leakage.
PAGE 12 --- We can also use 5VSUS to instead of 5V_S5 to save cost of MOSFET(A06402).
PAGE 15 --- Add a level-shift cicuit for EDID interface.
PAGE 17 --- 1. Add a off-page and a EMI solution for CLK48M.
2. Remove the reserve resistors (R693~R695) of parallel interface for PCI1510.
PAGE 18 --- Remove R696, connect controller and power switch directly .
PAGE 19 --- Change R682&R683 value from 56 ohms to 0 ohm cause of BOM error at A-test.
PAGE 22 --- 1. Change MC3 type from Y5V to X7R to improve singal quality.
2. Connect H1/H3 to AGND via a 0 ohm resistor by Conexant's comment.
PAGE 23 --- 1. Add a terminal resistor R707 for RTL8100/8110 id selection.
2. Add a 0.1uF to make Q40 turn on slowly to aviod 3VPCU drop issue.
PAGE 24 --- Modified transformer circuit cause of CT can't connect each other on 10/100M application.
PAGE 26 --- Add a flashrom as PLCC32 type for BIOS debugging.
PAGE 27 --- 1. Change R352 value from 120K ohms to 20M ohms.
2. Add a LPC debug port for software team to debug convenient.
PAGE 30 --- Add GMT fan controller for B-test to costdown.
PAGE 31 --- 1. Add ESD protection circuit for S-VIDEO signal to Docking.
2. Add R713 to enable the mux in the Tampa-2 cable
B
PAGE 33 --- Change PR143 value from 100K to 10K to solve display abnormal issue.
PAGE 35 --- 1. Move 5V_S5 circuit to Page 36.
2. De-popuplate PQ129 and PR182.
3. Change PR178 value from 22 ohm to 47 ohm.
PAGE 36 --- Remove PC170 and PQ127 but reserve 5V_S5 power circuit.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
CT3/5 MB BOARD
FROM
TO
1A
1A
1A
1A
2A
2A
2A
1A
1A
1A
1A
1A
1A
1A
1A
2A
2A
2A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
36
37
38
1A
1A
1A
39
1A
1
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
A
2A
2A
Model
MODEL
REV
CT3/5 MB
CHANGE LIST
Page
1
2
3
2A
PAGE 2 --- 1. Add C1048 for CLK48M to get better EMI performance.
31CT3MB0015
31CT3MB0031
PAGE 3 --- 1. Add R733 as pull-up resistor for PREQ#.

PAGE 11 --- 1. Add RF_OFF# and BT_OFF#
circuit.
PAGE 17 --- 1. Populate R704 and C1046 to get better EMI performance.
2.
PAGE 18 --- 1.
2.
3.
4.
5.
6.
7.
Remove R701 & R702 for unused PCI1510RVGF circuit.

Disconnect SM_PHYS_WP on controller side.
Tie SM_EL_WP with SM_PHYS_WP on conn side to allow for normal operation of SD and SM.
Add a discharge circuit for media card power.
Add R718 to solve cross-talk issue of MS-Pro card.
Add R717 to solve SM card can't write protect issue.
Add R719~R736 as terminal on all multi-function pins.
Add pull-up circuit.
4
5
6
7
8
9
10
11
12
13
14
PAGE 27 --- 1. Reserve 0R for RF_OFF# and BT_OFF# circuit.

2. Modify LPC pin name.
C
PAGE 28 --- 1. Change HDD and ODD select definition.
15
16
PAGE 30 --- Adjust Capacitors and Bead to improve CRT timing issue.
1. Change L66, L67, L68 from BK1608HM470 to 0R.
2. Remove C931, C932, C933.
3. Change C934, C935, C936 from 22P to 5.6P.
4. Change C6, C14, C350 from 10P to 5.6P.
5. Change L1, L26, L27 from BK1608HM470 to BLM18BA750SN1T.
PAGE 31 --- 1. Change L5,L6,L7,C57,C58,C64,C77,C113,C121 value to improve S-video quality.
2. Reserve S-video impedance match circuit.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
5
CT3/5 MB BOARD
FROM
TO
1A
2A
2A
2A
1A
1A
1A
3A
3A
1A
1A
2A
2A
1A
1A
1A
2A
1A
2A
2A
2A
1A
1A
2A
2A
2A
1A
2A
2A
1A
1A
2A
2A
1A
2A
2A
2A
2A
2A
2A
2A
1
3A
3A
2A
2A
CT3 BLOCK DIAGRAM
PCB STACK UP
LAYER 1 : TOP
LAYER 2 : GND
A
LAYER 4 : IN2
MAX6657 / GMT-781
PAGE: 3
+3V
LAYER 5 : VCC
LAYER 6 : BOT
PENTIUM-M / ALVISO / ICH6-M
Processor
Intel Pentium-M
Intel Celeron-M
CPU THERMAL
SENSOR
LAYER 3 : IN1
VCC_CORE
VCCP
VCCA
HCLK_CPU
HCLK_CPU#
HCLK_MCH
HCLK_MCH#
SRC_MCH
SRC_MCH#
SRC_ICH
SRC_ICH#
DREFSSCLK
DREFSSCLK#
DOT96
DOT96#
478 Pins (micro FC-PGA)
R.G,B
CRT port PAGE: 30
PAGE: 3, 4
Alviso-GM
LCD PanelPAGE: 15
VCCP
2.5VSUS
+1.5V
+2.5V
+3V
S-VIDEO
MINI-DIN PAGE: 32
82875GM/GME
1257 PCBGA
100MHZ
CLOCK GEN
PCLK_591
33MHZ
PCLK_7411
33MHZ
PCLK_ICH
100MHZ
ICS954206A
33MHZ
100MHZ
PCLK_MINI
33MHZ
100MHZ
CY28411ZXC
PCLK_LAN
48MHZ
CLK48_USB
14MHZ
14M_ICH
96MHZ
+3V
PAGE: 2
CPU CORE MAX1907

POWER 1.356V PAGE: 33
SYSTEM POWER MAX1999
POWER(3V/5V/15V)
PAGE: 36
VCCP
PAGE: 37
DDR-SODIMM1
2.5VSUS
NS L2996
VTT_DDR
SMDDR_VTERM
DDR-SODIMM2
PAGE: 39
B
PAGE: 13
PAGE: 5, 6, 7
DMI interface
33MHZ
100MHZ
DDR I/F 2.5V

333MHz
Single Channel
GMCH
LVDS

2.5VSUS/1.5V_S5 PAGE: 38
14.318MHz
FSB
400/533 MHZ
PCB THICKNESS: 1.2mm
BATT CHARGER
MAX1772
PAGE: 34
32.768KHz
100MHZ 4X
DISCHARGE
PAGE: 35
USB 2.0
USB PORT 0, 1
33MHZ, 3.3V PCI
ICH6-M
PAGE: 19
ATA 66/100
1st IDE - HDD

PAGE: 28
ATA 66/100
2nd IDE - CDROM

PAGE: 28
+5V
5VSUS
+3V
3V_S5
3VSUS
+2.5V
+1.5V
1.5V_S5
VCCRTC
GMCH_VTT
AC97
82801FBM
24.576MHz
PAGE: 8, 9, 10
LAN
AC97
PWRCLKP
PWRCLKN
DIB_DATAN
DIB_DATAP
CX20468-31
MBAMC20493-010
PAGE: 20
32.768KHz
48MHz
Realtek
8100CL
LANVCC
PAGE: 23
MINI-PCI
CARDBUS / IEEE 1394

CONTROLLER/CF
+3V
+5V
LANVCC
TI 7411
3VSUS
PAGE: 14
PAGE: 16, 17, 18, 19
3.3V LPC, 33MHz
Daughter Board
TV, USB, BLUE
TOOTH
PAGE: 31
PAGE: 32
SMARTDAA
MODEM,
MDC
PC97551
AV BOARD
24.576MHz
609 BGA
CABLE DOCK
25MHz
Power Board
3VPCU
+3V
VCCRTC
PAGE: 32
PAGE: 32
TPA0312
PAGE: 21
PAGE: 22
TQFP 176
5 IN 1
AMP
PAGE: 27
RJ45
JACK
PAGE: 24
WIRE
CARDBUS
SLOT X1
CARD
READER
SD/MMC,
SM, MS,
XD
PAGE: 18
Intel WLAN
W2200
802.11b/g
1394
CONN
PAGE: 16
PAGE: 19
PCI DEVICES IRQ ROUTING

DEVICE
D
IDSEL # REQ/GNT #
PCI_INT
GBIT ETHERNET AD16
FAN
AD22
C,D
PAGE: 30
CardBus/1394 AD25
E,F,G
MINIPCI SLOT
Touchpad
Keyboard
PAGE: 32
PAGE: 32
FLASH
PAGE: 26
RJ11
JACK
JACK
HEADPHONE,
2ND HEADPHONE,
MIC
PAGE: 21
PAGE: 24
PROJECT : CT3
Quanta Computer Inc.

Size
Document Number
Custom
BLOCK
Date:
1
Monday, December 27, 2004

7
Rev
1A
DIAGRAM
Sheet
of
8
39
L51
CLKVDD
C640
C641
0.1U
0.1U
0.1U
0.1U
0.1U
2.2R
CLK_VDDA
C644
C645
0.1U
4.7U/10V
C642
SI stage:
Enable CLK48M from CKG. by
R705 for the PLL circuit of 7411,
and disable the ocsillator circuit
at PCI7411 side.
Sting 10/12/2004
CLK_VDDA
XIN
33P
R437
CL=20pF
Y9
14.318MHZ
*2M
C643
XOUT
U34
50
XTAL_IN
49
XTAL_OUT
10
55
54
33
CLK_EN#
11
STP_PCI#
11,33 STP_CPU#
0.01U_0402
CLKVDD1
ACB2012L-120
120 ohms@100Mhz
C1032
C648
C649
0.1U
0.1U
4.7U/10V
17
CLK48M
11
CLK48_USB
R705
22R
CLK48_USB R444
22R
CG_BSEL2 R447
4.7K
SMBCK
SMBDT
CG_BSEL0
CG_BSEL1
U18_FSC
CLK_VDDREF
CLKVDD
R450
2.2R
CLK_VDD48
CLKVDD1
C650
C651
0.1U
4.7U/10V
CLKVDD
CLK_VDD48
R457
1R
R458
Iref=2.32mA,
Ioh=4*Iref
CLK_VDDREF
IREF
475/F
SCLK
SDATA
12
16
53
FSA/USB_48
FSB/TEST_MODE
FSC/TEST_SEL
48
42
VDD_REF
VDD_CPU
1
7
5
5
21
28
34
VDD_SRC0
VDD_SRC1
VDD_SRC2
11
VDD_48
39
DOT96
DOT96#
DOT96
DOT96#
1
3
2
4
R_DOT96
R_DOT96#
14
15
DOT96
DOT96#
100
100
33
DOTHAN FSB 400
133
100
33
DOTHAN FSB 533
166
100
33
200
100
33
266
100
33
333
100
33
400
100
33
RESERVED
Q44
2N7002E
11
PDAT_SMB
R464
10K
PCI
T131
T132
SRC6
SRC6#
33
32
RSRC_ICH
RSRC_ICH#
SRC5
SRC5#
31
30
RSRC_MCH
RSRC_MCH#
SRC4
SRC4#
26
27
T297
T298
SRC3
SRC3#
24
25
T133
T134
SRC2
SRC2#
22
23
T135
T136
SRC1
SRC1#
19
20
SRC0
SRC0#
17
18
PCI5
PCI4
PCI3
PCI2
PCIF1
PCIF0/ITP_EN
5
4
3
56
9
8
T137
T138
RDREFSSCLK
RDREFSSCLK#
SMBDT
SMBDT
12.1/F
14M_ICH 11
2
4
33X2
2
4
33X2
RP13
1
3
33X2
2
4
1
3
RP14
2
4
33X2
RP15
3
1
R_PCLK_591
R_PCLK_7411
R_PCLK_ICH
R_PCLK_MINI
R_PCLK_LAN
ITP_EN
HCLK_CPU 3
HCLK_CPU# 3
SRC_ICH 11
SRC_ICH# 11
SRC_MCH 6
SRC_MCH# 6
4
2
33X2
33R
33R
33R
33R
33R
R459
R460
R461
R462
R463
HCLK_MCH 5
HCLK_MCH# 5
DREFSSCLK 5
DREFSSCLK# 5
B
PCLK_591 27
PCLK_7411 17
PCLK_ICH 10
PCLK_MINI 14
PCLK_LAN 23
R440
10K
R465
10K
R_PCLK_LAN
ITP_EN
0: SRCCLK=96MHZ
0: SRC_7 Pair
1: SRCCLK=100MHZ 1: CPU_2 ITP Pair
13
EMI
+3V
To ICH6-M
Q45
2N7002E
* Frequence select by CPU auto sense.

11
PCLK_SMB
To DDR-SODIMM
+3V
48MHZ
36
35
250mA ( MAX. )
SMbus address D4
ICS954206A
+3V
CPU2_ITP/SRC7
CPU2#_ITP/SRC7#
R439
RP11
1
3
RP12
RHCLK_MCH
1
RHCLK_MCH#
3
13
51
2
6
29
45
CK-410M
CPU1
CPU1#
41
40
IREF
33X2
RHCLK_CPU
RHCLK_CPU#
VDD_PCI_1
VDD_PCI_2
GND_48
GND_REF
GND_PCI_1
GND_PCI_2
GND_SRC
GND_CPU
0.1U
SRC
44
43
CK-410M
46
47
RP16
CPU
14M_REF
CPU0
CPU0#
VTT_PWRGD#/PD
PCI_STOP#
CPU_STOP#
C652
FSC FSB FSA
REF
52
33P
C646
L52
+3V
Place these termination to close CK410M.
38
C639
37
C638
VSSA
R438
C637
VDDA
120 ohms@100Mhz
ACB2012L-120
+3V
C1038 *10P
CLK48_USB
SMBCK
SMBCK
13
R_PCLK_LAN
R441
10K
HCLK_CPU
HCLK_CPU#
R442
R443
49.9/F
49.9/F
HCLK_MCH
HCLK_MCH#
R445
R446
49.9/F
49.9/F
SRC_MCH
SRC_MCH#
R448
R449
49.9/F
49.9/F
C1041 *10P
SRC_ICH
SRC_ICH#
R451
R452
49.9/F
49.9/F
C1042 *10P
DREFSSCLK
DREFSSCLK#
R453
R454
49.9/F
49.9/F
C1043 *10P
DOT96
DOT96#
R455
R456
49.9/F
49.9/F
C1048 10P
CLK48M
+3V
VCCP
33MHZ
VCCP
C1039 *10P
PCLK_591
R466
10K
R469
3 SELPSB1_CLK
R471
3 SELPSB0_CLK
R467
*1K
0R
R468
*1K
C1040 *10P
PCLK_7411
CG_BSEL0
PCLK_ICH
CG_BSEL1
CG_BSEL2
0R
R470
R472
1K
1K
PV stage:
Add C1048 for CLK48M to get better EMI
performance.
Sting 11/29/2004
MCH_BSEL1 5
PCLK_MINI
PCLK_LAN
MCH_BSEL2 5
14.318MHZ
D
R473
*10K
R474
*0R
R475
*0R
C1044 *10P
14M_ICH
PROJECT : CT3
R469,R471
Dothan-A can remove so that the FSB frequency will be selected by
hardware setting(R474,R475,R467,R468).
Dothan-B should be populated.

Size
Document Number
Custom
Date:

7
Rev
3A
CLOCK GENERATOR
Sheet
of
8
39
10
10
10
10
A20M#
FERR#
IGNNE#
STPCLK#
INTR
NMI
SMI#
BR0#
N4
HBREQ0#
IERR#
INIT#
A4
B5
IERR#
CPUINIT#
LOCK#
J2
HLOCK#
B11
H1
K1
L2
M3
CPURST#
RS#0
RS#1
RS#2
HTRDY#
K3
K4
HIT#
HITM#
BPM#0
BPM#1
BPM#2
BPM#3
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
C8
B8
A9
C9
A10
B10
A13
C12
A12
C11
B13
A7
BPM#0
BPM#1
BPM#2
BPM#3
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
PROCHOT#
THERMDA
THERMDC
B17
B18
A18
CPU_PROCHOT#
THERMDA
THERMDC
THERMTRIP#
C17
THRMTRIP#
ITP_CLK1
ITP_CLK0
BCLK1
BCLK0
A15
A16
B14
B15
HCLK_CPU#
HCLK_CPU
RESET#
RS0#
RS1#
RS2#
TRDY#
HIT#
HITM#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
ADSTB#1
A20M#
FERR#
IGNNE#
C2
D3
A3
A20M#
FERR#
IGNNE#
STPCLK#
INTR
NMI
C6
D1
D4
B4
STPCLK#
LINT0
LINT1
SMI#
Dothan_478P
5
5
5
VCCP
DEFER# 5
DRDY#
5
DBSY#
5
HD#[0..63]
HD#[0..63]
R476
56R
HBREQ0# 5
CPUINIT# 10
HLOCK# 5
CPURST# 5
RS#0
5
RS#1
5
RS#2
5
HTRDY# 5
HIT#
HITM#
5
5
5
5
5
T141
T142
T143
T144
T145
T146
HDSTBN0#
HDSTBP0#
HDSTBN0#
HDSTBP0#
DINV#0
HD#[0..63]
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
VCCP
R477
DBR#
56R
11
THRMTRIP# 5,10
T148
T149
HCLK_CPU# 2
HCLK_CPU 2
5
5
5
HDSTBN1#
HDSTBP1#
DINV#1
2
2
SELPSB0_CLK
SELPSB1_CLK
HDSTBN1#
HDSTBP1#
T147
PM_PSI#
SELPSB0_CLK
SELPSB1_CLK
T150
T151
T152
T153
T154
VCCP
R483
1K/F
HD#[0..63]
U36B
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
H_GTLREF
A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
C23
C22
D25
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
K24
L24
J26
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#
E1
PSI#
C16
C14
BSEL0
BSEL1
B2
C3
AF7
AC1
E26
RSVD
RSVD
RSVD
RSVD
RSVD
AD26
DATA GRP 0
DEFER#
DRDY#
DBSY#
ADS#
BNR#
BPRI#
DATA GRP 3
HADSTB1#
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
AE5
L4
H2
M2
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
ADDR GROUP 1
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HADSTB1#
10
10
10
DATA GRP 1
HA#[3..31]
R2
P3
T2
P1
T1
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
CONTROL
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
N2
L1
J3
ADS#
BNR#
BPRI#
XTP/ITP SIGNALS
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB#0
THERM
HADSTB0#
DATA GRP 2
P4
U4
V3
R3
V2
W1
T4
W2
Y4
Y1
U1
AA3
Y3
AA2
U3
ADDR GROUP 0
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HADSTB0#
5
5
5
5
5
U36A
HA#[3..31]
HA#[3..31]
H CLK
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
W25
W24
T24
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
AE24
AE25
AD20
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
COMP0
COMP1
COMP2
COMP3
MISC
RSVD/DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
GTLREF
TEST1
TEST2
Layout note: 0.5" max length.
+3V
P25
P26
AB2
AB1
HDSTBN2#
HDSTBP2#
HDSTBN3#
HDSTBP3#
COMP0
COMP1
COMP2
COMP3
R478
R479
R480
R481
HDSTBN3# 5
HDSTBP3# 5
DINV#3
5
27.4/F
54.9R
27.4/F
54.9R
G1
B7
C19 DPWR#
CPUPWRGD
E4
A6
C5
F23
HDSTBN2# 5
HDSTBP2# 5
DINV#2
5
HD#[0..63]
VCCP
H_DPRSTP# 10
H_DPSLP# 10
DPWR#
5
R482
200/F
CPUPWRGD 10
H_CPUSLP# 5,10
H_TEST1
H_TEST2
Dothan_478P
R484
2K/F
VCCP
H_GTLREF = 2/3 * VCCP +-2%

Can't shared with GMCH
R485
R486
*1K
*1K
R487
1K
R488
56R
THRM_EC 27
THRMTRIP#
Q46
2
330R
MMBT3904
1
R489
THRM_EC
To EC --> Send FANSIG to control fan.
+3V +3V
SI stage:
Remove H/W shutdown circuit
(R613&Q54)that supported
ADM1032.
+3V
+3V
R494
Q47
27,34
MBDATA
2N7002E 10K
1
R495
R496
10K
100R
MBCLK
H/W MONITOR
C660
6657VCC
2N7002E
1
R490
R491
R492
R493
R733
150/F
39.2R
*54.9R
54.9R
56R
TCK
TRST#
R497
R498
27.4/F
680R
U37
0.1U/0402
2
27,34
Q48
3
Sting 10/12/2004
TDI
TMS
TDO
CPURST#
PREQ#
THCLK_SMB
THERMDA
C661
2200P
THERMDC
VCC
SMCLK
THCLK_SMB
SMDATA
THDAT_SMB
DXP
DXN
-ALT
-OVT
GND
36
ICH_THRM# 11
PROJECT : CT3
ICH_THRM#
To SB --> System throttling
MAX6657/GMT-781
1999_RST#
H/W Shutdown
A
PV stage:
Add R733 as pull-up resistor for PREQ#.
Sting 11/29/2004
THDAT_SMB
+3V
1
VCCP
Size
Custom
Document Number
Date:
Rev
3A
Dothan CPU (Host Bus)

Sheet
E
of
39
U36D
120mA
CPU_VCCA
CPU_CORE
CPU_CORE
C662
U36C
AA11
AA13
AA15
AA17
AA19
AA21
AA5
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC9
AD10
AD12
AD14
AD16
AD18
AD8
AE11
AE13
AE15
AE17
AE19
AE9
AF10
AF12
AF14
AF16
AF18
AF8
D18
D20
D22
D6
D8
E17
E19
E21
E5
E7
E9
F18
F20
F22
F6
F8
G21
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
R499
VCCA0
VCCA1/RSVD
VCCA2/RSVD
VCCA3/RSVD
G5
H22
H6
J21
J5
K22
U5
V22
V6
W21
W5
Y22
Y6
F26
B1
N1
AC26
VCCP0
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L21
L5
M22
M6
N21
N5
P22
P6
R21
R5
T22
T6
U21
VCCQ0
VCCQ1
P23
W4
VID0
VID1
VID2
VID3
VID4
VID5
E2
F2
F3
G3
G4
H4
CPU_VCCA
C663
C664
0.01U_0402
10U/10V/0805
TP_VCCA1
TP_VCCA2
TP_VCCA3
T155
T156
T157
SI stage:
Use X7R type to replace Y5V type
for Decoupling/Bypass capacitor.
Sting 10/12/2004
VCCP
VCCP
+ C665
VCCP
C666
C667
C668
C669
C670
C671
C672
C673
C674
C675
150U/6.3V_7
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
C688
C689
CPU_CORE
C680
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
VCCSENSE
AE7 TP_VCCSENSE
VSSSENSE
AF6 TP_VSSSENSE
33
33
33
33
33
33
C682
C683
C684
C685
C691
C692
C687
CPU_CORE
C693
C694
C695
C696
C697
C698
C699
R502
*54.9R
10U/10V/0805
10U/10V/0805
10U/10V/0805
10U/10V/0805 10U/10V/0805
*54.9R
10U/10V/0805
10U/10V/0805
10U/10V/0805
10U/10V/0805
10U/10V/0805
CPU_CORE
C700
C701
C702
CPU_CORE
C703
C704
10U/10V/0805
10U/10V/0805
10U/10V/0805
10U/10V/0805
10U/10V/0805
CPU de-coupling
capacitor
CPU_CORE
C686
10U/10V/0805
10U/10V/0805
10U/10V/0805
10U/10V/0805
10U/10V/0805
CPU_CORE
C690
R501
C681
CPU_CORE
10U/10V/0805
10U/10V/0805
10U/10V/0805
10U/10V/0805
10U/10V/0805
Dothan_478P
2
+1.5V
Remove +1.8V optional cause of the

VCCA is powered by +1.5V in Intel
specification.
Sting 08/05/2004
0.1U
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
0R
CPU_CORE
C705
C706
C707
C708
C709
10U/10V/0805
10U/10V/0805
10U/10V/0805
10U/10V/0805
10U/10V/0805
CPU_CORE
C710
C711
C712
C713
C714
C715
C716
C717
C718
C719
C720
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
10U/10V/0805
10U/10V/0805
10U/10V/0805
10U/10V/0805
10U/10V/0805
C721
C722
C723
C724
A2
A5
A8
A11
A14
A17
A20
A23
A26
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24
B3
B6
B9
B12
B16
B19
B22
B25
C1
C4
C7
C10
C13
C15
C18
C21
C24
D2
D5
D7
D9
D11
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
Dothan_478P
CPU_CORE
CPU_CORE
PROJECT : CT3
C725
C726
C727
C728
C729
C730
C731
C732
C733
C734
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
CPU Bypass
capacitor
C
Size
Custom
Document Number
Date:
Rev
2A
CPU POWER / GND

Sheet
E
of
39
HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING
C1
C2
D1
T1
L1
P1
HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING
This group should be

routed as 10:20
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HADSTB0#
HADSTB1#
HVREF
HBNR#
HBPRI#
BREQ0#
HCPURST#
F8
B9
E13
J11
A5
D5
E7
H10
ADS#
HADSTB0#
HADSTB1#
HVREF
BNR#
BPRI#
HBREQ0#
CPURST#
HCLKINN
HCLKINP
AB1
AB2
HCLK_MCH#
HCLK_MCH
HDBSY#
HDEFER#
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDPWR#
HDRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
HEDRDY#
HHIT#
HHITM#
HLOCK#
HPCREQ#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HRS0#
HRS1#
HRS2#
HCPUSLP#
HTRDY#
C6
E6
H8
K3
T7
U5
G6
F7
G4
K1
R3
V3
G5
K2
R2
W4
F6
D4
D6
B3
A11
A7
D7
B8
C7
A8
A4
C5
B4
G8
B5
DBSY#
DEFER#
DINV#0
DINV#1
DINV#2
DINV#3
DPWR#
DRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
U38C
11
11
11
11
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
RS#0
RS#1
RS#2
HCPUSLP#
HTRDY#
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
11
11
11
11
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
11
11
11
11
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
11
11
11
11
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
AA31
AB35
AC31
AD35
DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
Y31
AA35
AB31
AC35
DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
AA33
AB37
AC33
AD37
DMITXN0
DMITXN1
DMITXN2
DMITXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
Y33
AA37
AB33
AC37
DMITXP0
DMITXP1
DMITXP2
DMITXP3
VCCP
13 CLK_SDRAM0
13 CLK_SDRAM1
T165
13 CLK_SDRAM3
13 CLK_SDRAM4
T166
R504
HIT#
HITM#
HLOCK#
HA#[3..31] 3
ADS#
3
HADSTB0# 3
HADSTB1# 3
BNR#
BPRI#
HBREQ0#
CPURST#
3
3
3
3
100/F
R507
C735
200/F
0.1U
13 CLK_SDRAM0#
13 CLK_SDRAM1#
T167
13 CLK_SDRAM3#
13 CLK_SDRAM4#
T168
7,13
7,13
7,13
7,13
HCLK_MCH# 2
HCLK_MCH 2
DBSY#
3
DEFER# 3
DINV#0
3
DINV#1
3
DINV#2
3
DINV#3
3
DPWR#
3
DRDY#
3
HDSTBN0# 3
HDSTBN1# 3
HDSTBN2# 3
HDSTBN3# 3
HDSTBP0# 3
HDSTBP1# 3
HDSTBP2# 3
HDSTBP3# 3
CKE0
CKE1
CKE2
CKE3
7,13
7,13
7,13
7,13
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
3
3
3
3
3
3
3
3
HTRDY#
SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#
CKE0
CKE1
CKE2
CKE3
AP21
AM21
AH21
AK21
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
AN16
AM14
AH15
AG16
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
M_RCOMPN
M_RCOMPP
SMXSLEW
SMYSLEW
T181
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
RS#0
RS#1
RS#2
AN33
AK1
AE10
AJ33
AF5
AD10
SMDDR_VREF
3
3
3
0R
SM_OCDCOMP0
SM_OCDCOMP1
AP14
AL15
AM11
AN10
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
AK10
AK11
AF37
AD1
AE27
AE28
AF9
AF10
SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT
It's point to point, 55ohm trace,

keep as short as possible.
R510
SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5
CLK_SDRAM0#
CLK_SDRAM1#
CLK_SDRAM2#
CLK_SDRAM3#
CLK_SDRAM4#
CLK_SDRAM5#
M_OCDCOMP0 AF22
M_OCDCOMP1 AF16
T178
HIT#
HITM#
HLOCK#
CLK_SDRAM0 AM33
CLK_SDRAM1
AL1
CLK_SDRAM2 AE11
CLK_SDRAM3 AJ34
CLK_SDRAM4
AF6
CLK_SDRAM5 AC10
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
CFG/RSVD
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
CFG0
R503
1K
G16
VCCP
H13 MCH_BSEL1
MCH_BSEL1 2
G14 MCH_BSEL2
MCH_BSEL2 2
CFG3
F16
CFG3
CFG4
F15
T158
CFG5
G15
CFG5
CFG6
E16
CFG6
CFG7
D17
CFG7
CFG8
J16
T159
CFG9
D15
CFG9
CFG10
E15
T160
CFG11
D14
CFG11
CFG12
E14
CFG12
CFG13
H12
CFG13
CFG14
C14
T161
CFG15
H15
T162
CFG16
J15
CFG16
CFG17
H14
T163
CFG18
G22
CFG18
CFG19
G23
CFG19
CFG20
D23
T164
G25
G24
J17
A31
A30
D26
+2.5V
D25
R505
BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PWROK
RSTIN#
DREF_CLKN
DREF_CLKP
DREF_SSCLKN
DREF_SSCLKP
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
J23
J21
H22
F5
AD30
AE29
6
6
6
6
6
6
6
PM_BMBUSY# 11
THRMTRIP# 3,10
IMVPOK 11,33
PLTRST# 10,11,28
100R
A24
A23
C37
D37
AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37
6
6
6
10K
PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
R508
0R
R509
R506
10K
PM
HA#[3..31]
G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13
LCK
E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2
NC
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
DMI
U38A
HD#[0..63]
HD#[0..63]
HOST
DDR MUXING
DOT96# 2
DOT96
2
DREFSSCLK# 2
DREFSSCLK 2
TP_NC1
TP_NC2
TP_NC3
TP_NC4
TP_NC5
TP_NC6
TP_NC7
TP_NC8
TP_NC9
TP_NC10
TP_NC11
T169
T170
T171
T172
T173
T174
T175
T176
T177
T179
T180
C
ALVISO
H_CPUSLP# 3,10
ALVISO
2.5VSUS
VCCP
VCCP
R513
R514
221/F
221/F
VCCP
R512
54.9R
HXSCOMP
R515
24.9/F
HXRCOMP
M_OCDCOMP0
M_OCDCOMP1
R511
80.6/F
D
M_RCOMPN
HXSWING
HYSWING
R516
*40.2/F
VCCP
R519
C736
R520
C737
100/F
0.1U
100/F
0.1U
R521
54.9R
HYSCOMP
R522
24.9/F
HYRCOMP
R517
*40.2/F
M_RCOMPP
R518
80.6/F
PROJECT : CT3
Route as short
as possible.
Size
Document Number
Custom
ALVISO-Host
Date:

7
Rev
1A
Sheet
of
8
39
U38F
S-CVBS1
S-YD1
S-CD1
R532
R533
R534
150/F
150/F
150/F
Place near chip
DDCCLK
DDCDAT
CRT_B
30
CRT_G
BKLON
R538
R539
100K
100K
R541
R542
2.2K
2.2K
LBKLT_CTRL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
EDIDCLK
EDIDDATA
DISP_ON
R546
T299
T300
B30
B29
C25
C24
LACLKN
LACLKP
LBCLKN
LBCLKP
T216
T217
1.5K/F
TXLCLKOUTTXLCLKOUT+
15
15
15
TXLOUT0TXLOUT1TXLOUT2-
B34
B33
B32
LADATAN0
LADATAN1
LADATAN2
15
15
15
TXLOUT0+
TXLOUT1+
TXLOUT2+
A34
A33
B31
LADATAP0
LADATAP1
LADATAP2
T301
T302
T303
C29
D28
C27
LBDATAN0
LBDATAN1
LBDATAN2
T305
T304
T306
C28
D27
C26
LBDATAP0
LBDATAP1
LBDATAP2
LVDS
15
15
T223
T225
T227
E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27
CRT_R
VSYNC_NB
39R
39R
HSYNC_NB
255/F REFSET
+2.5V
15
15
15
DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET
VGA
30
30
30
R535
R536
R537
VSYNC
HSYNC
15
E24
E23
E21
D21
C20
B20
A19
B19
H21
G21
J20
4.99K/F
150/F
150/F
150/F
30
30
30
TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC
R528
R529
R530
R531
CRT_B
CRT_G
CRT_R
A15
C16
A17
J18
B15
B16
B17
SRC_MCH#
SRC_MCH
PCI-EXPRESS GRAPHICS
31
31
31
SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP
TV
2
2
H24
H25
AB29
AC29
MISC
T182
T183
SRC_MCH#
SRC_MCH
EXP_COMP R523
EXP_COMPI
EXP_ICOMPO
D36
D34
EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34
T184
T185
T186
T187
T188
T189
T190
T191
T192
T193
T194
T195
T196
T197
T198
T199
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34
T200
T201
T202
T203
T204
T205
T206
T207
T208
T209
T210
T211
T212
T213
T214
T215
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36
T218
T219
T220
T221
T222
T224
T226
T228
T229
T230
T231
T232
T233
T234
T235
T236
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36
T237
T238
T239
T240
T241
T242
T243
T244
T245
T246
T247
T248
T249
T250
T251
T252
24.9/F
VCC3G_PCIE
+1.5v
These pins can't leave as NC

if we didn't use PCI-E on
system cause it also used for
DMI compensation.
A
ALVISO
Strapping
5
CFG5
CFG9
5
5
CFG9
R547
*2.2K
CFG12
CFG13
CFG12
CFG13
CFG6
CFG16
R548
R549
R550
R551
R552
CFG[2:0]
001=533MT/S FSB
101=400MT/S FSB
*2.2K
*2.2K
*2.2K
*2.2K
2.2K
CFG[3:17] have internal pullup.
CFG6
CFG16
CFG[18:19] have internal pulldown.

Low=DMIx2
High=DMIx4
CFG7
Low=PCIE Reverse Lanes

High=PCIE Normal Operation
(Default)
Low=DDR II
High=DDR
00 : Reserved
01 : XOR Mode Enabled
10 : All Z Mode Enabled
11 : Normal Operation (Default)
(Default)
(Default)
Low=FSB Dynamic ODT Disabled

High=FSB Dynamic ODT Enabled
+2.5V
CFG7
(Default)
+2.5V
5
CFG11
CFG11
CFG3
CFG3
R553
R554
R555
R556
*1K
*2.2K
*2.2K
R557
*2.2K
CFG18
Low=DT/Transportable CPU
High=Mobile CPU (Default)
1
CFG18
Low=CPU core VCC 1.05V

High=CPU core VCC 1.5V
2
Low=FSB533
(Default)
3
Low=DDR533
CFG19
CFG19
Low=CPU VTT 1.05V
High=CPU VTT 1.2V
PROJECT : CT3
*1K
5
(Default)
Size
Document Number
Custom
ALVISO
Date:

7
Rev
1A
DMI
Sheet
of
8
39
U38B
MD31
MD26
MD30
MD27
1
3
3
1
2
4
4
2
R_MD31
R_MD26
R_MD30
R_MD27
RN65
4P2R-S-10
RN66
4P2R-S-10
MD25
MD24
MD28
MD29
3
1
1
3
4
2
2
4
R_MD25
R_MD24
R_MD28
R_MD29
MD19
MD18
MD22
MD23
RN67
4P2R-S-10
RN68
4P2R-S-10
1
3
1
3
2
4
2
4
R_MD0
R_MD1
R_MD2
R_MD3
R_MD4
R_MD5
R_MD6
R_MD7
R_MD8
R_MD9
R_MD10
R_MD11
R_MD12
R_MD13
R_MD14
R_MD15
R_MD16
R_MD17
R_MD18
R_MD19
R_MD20
R_MD21
R_MD22
R_MD23
R_MD24
R_MD25
R_MD26
R_MD27
R_MD28
R_MD29
R_MD30
R_MD31
R_MD32
R_MD33
R_MD34
R_MD35
R_MD36
R_MD37
R_MD38
R_MD39
R_MD40
R_MD41
R_MD42
R_MD43
R_MD44
R_MD45
R_MD46
R_MD47
R_MD48
R_MD49
R_MD50
R_MD51
R_MD52
R_MD53
R_MD54
R_MD55
R_MD56
R_MD57
R_MD58
R_MD59
R_MD60
R_MD61
R_MD62
R_MD63
R_MD19
R_MD18
R_MD22
R_MD23
RN69
4P2R-S-10
RN70
4P2R-S-10
MD21
MD20
MD16
MD17
3
1
3
1
4
2
4
2
R_MD21
R_MD20
R_MD16
R_MD17
RN71
4P2R-S-10
RN72
4P2R-S-10
MD35
MD34
MD39
MD38
1
3
1
3
2
4
2
4
R_MD35
R_MD34
R_MD39
R_MD38
MD36
MD37
MD33
MD32
RN73
4P2R-S-10
RN74
4P2R-S-10
MD59
MD58
MD62
MD63
RN75
4P2R-S-10
RN76
4P2R-S-10
3
1
1
3
4
2
2
4
4
2
2
4
R_MD36
R_MD37
R_MD33
R_MD32
R_MD59
R_MD58
R_MD62
R_MD63
RN77
4P2R-S-10
RN78
4P2R-S-10
MD56
MD60
MD61
MD57
3
1
1
3
4
2
2
4
R_MD56
R_MD60
R_MD61
R_MD57
RN79
4P2R-S-10
RN80
4P2R-S-10
MD51
MD50
MD55
MD54
1
3
3
1
2
4
4
2
R_MD51
R_MD50
R_MD55
R_MD54
RN81
4P2R-S-10
RN82
4P2R-S-10
MD48
MD53
MD49
MD52
3
1
3
1
4
2
4
2
R_MD48
R_MD53
R_MD49
R_MD52
RN83
4P2R-S-10
RN84
4P2R-S-10
MD47
MD46
MD42
MD43
1
3
1
3
2
4
2
4
R_MD47
R_MD46
R_MD42
R_MD43
RN85
4P2R-S-10
RN86
4P2R-S-10
MD44
MD45
MD40
MD41
3
1
3
1
4
2
4
2
R_MD44
R_MD45
R_MD40
R_MD41
RN87
4P2R-S-10
RN90
4P2R-S-10
MD10
MD11
MD15
MD14
1
3
1
3
2
4
2
4
R_MD10
R_MD11
R_MD15
R_MD14
MD13
MD8
MD9
MD12
RN95
4P2R-S-10
RN100
4P2R-S-10
RN105
4P2R-S-10
RN110
4P2R-S-10
3
1
1
3
MD6
MD3
MD2
MD7
MD1
MD0
MD4
MD5
RN115
4P2R-S-10
RN120
4P2R-S-10
1
3
1
3
3
1
1
3
1
3
1
3
2
4
2
4
4
2
2
4
2
4
2
4
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
M_A_BA0
M_A_BA1
SA_BS0#
SA_BS1#
SA_BS2#
AK15
AK16
AL21
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
AJ37
AP35
AL29
AP24
AP9
AP4
AJ2
AD3
R_SDM0
R_SDM1
R_SDM2
R_SDM3
R_SDM4
R_SDM5
R_SDM6
R_SDM7
AK36
AP33
AN29
AP23
AM8
AM4
AJ1
AE5
R_SM_DQS0
R_SM_DQS1
R_SM_DQS2
R_SM_DQS3
R_SM_DQS4
R_SM_DQS5
R_SM_DQS6
R_SM_DQS7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
AK35
AP34
AN30
AN23
AN8
AM5
AH1
AE4
AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5
M_A_MA[0..13]
AL17
AP17
AP18
AM17
AN18
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15
M_A_MA0
M_A_MA1
M_A_MA2
M_A_MA3
M_A_MA4
M_A_MA5
M_A_MA6
M_A_MA7
M_A_MA8
M_A_MA9
M_A_MA10
M_A_MA11
M_A_MA12
M_A_MA13
AN15
AP16
AF29
AF28
AP15
M_A_SCASA#
M_A_SRASA#
SA_RCVENIN#
SA_RCVENOUT#
M_A_BMWEA#
T77
T80
SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
SB_BS0#
SB_BS1#
SB_BS2#
AJ15
AG17
AG21
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
AF32
AK34
AK27
AK24
AJ10
AK5
AE7
AB7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#
M_B_BA0
M_B_BA1
R_SDM0
1
R640
1
R641
1
R642
1
R643
1
R644
1
R645
1
R646
1
R647
R_SM_DQS0 1
R648
R_SM_DQS1 1
R649
R_SM_DQS2 1
R650
R_SM_DQS3 1
R651
R_SM_DQS4 1
R652
R_SM_DQS5 1
R653
R_SM_DQS6 1
R654
R_SM_DQS7 1
R655
R_SDM1
R_SDM2
R_SDM3
R_SDM4
AF34
AK32
AJ28
AK23
AM10
AH6
AF8
AB4
R_SDM5
R_SDM6
R_SDM7
AF35
AK33
AK28
AJ23
AL10
AH7
AF7
AB5
M_B_MA[0..13]
AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15
M_B_MA0
M_B_MA1
M_B_MA2
M_B_MA3
M_B_MA4
M_B_MA5
M_B_MA6
M_B_MA7
M_B_MA8
M_B_MA9
M_B_MA10
M_B_MA11
M_B_MA12
M_B_MA13
AH14
AK14
AF15
AF14
AH16
M_B_SCASA#
M_B_SRASA#
SB_RCVENIN#
SB_RCVENOUT#
M_B_BMWEA#
SDM0
10R
SDM1
2
10R
SDM2
2
10R
SDM3
2
10R
SDM4
2
10R
SDM5
2
10R
SDM6
10R
SDM7
2
10R
SM_DQS0
10R
SM_DQS1
10R
SM_DQS2
2
10R
SM_DQS3
2
10R
SM_DQS4
2
10R
SM_DQS5
2
10R
SM_DQS6
2
10R
SM_DQS7
2
10R
T75
T76
ALVISO
ALVISO
SMDDR_VTERM
R_MD13
R_MD8
R_MD9
R_MD12
R_MD6
R_MD3
R_MD2
R_MD7
RN88
4P2R-S-56
RN91
4P2R-S-56
MD58
MD59
MD60
MD56
1
3
1
3
2
4
2
4
1
3
1
3
2
4
2
4
MD62
MD63
MD57
MD61
RN89
4P2R-S-56
RN92
4P2R-S-56
RN98
4P2R-S-56
RN101
4P2R-S-56
MD48
MD53
MD47
MD46
1
3
1
3
2
4
2
4
1
3
3
1
2
4
4
2
MD54
MD55
MD51
MD50
RN99
4P2R-S-56
MD40
MD41
MD35
MD34
RN108
4P2R-S-56
RN111
4P2R-S-56
R_MD1
R_MD0
R_MD4
R_MD5
MD26
MD31
MD27
MD30
RN118
4P2R-S-56
RN121
4P2R-S-56
1
3
1
3
2
4
2
4
1
3
3
1
2
4
4
2
RN127
4P2R-S-56
RN129
4P2R-S-56
MD25
MD24
MD19
MD18
RN135
4P2R-S-56
RN137
4P2R-S-56
MD17
MD16
MD11
MD10
1
3
1
3
2
4
2
4
RN141
4P2R-S-56
RN143
4P2R-S-56
MD9
MD12
MD8
MD13
1
3
1
3
RN147
4P2R-S-56
RN149
4P2R-S-56
MD2
MD7
MD0
MD1
1
3
1
3
1
3
1
3
1
3
3
1
2
4
4
2
1
3
1
3
2
4
2
4
MD33
MD32
MD45
MD44
MD39
MD38
MD37
MD36
RN109
4P2R-S-56
4P2R-S-56
RN112
RN113
4P2R-S-56
RN116
4P2R-S-56
RN119
4P2R-S-56
RN122
4P2R-S-56
MD29
MD28
MD23
MD22
RN128
4P2R-S-56
RN130
4P2R-S-56
1
3
1
3
2
4
2
4
MD3
MD6
MD5
MD4
RN136
4P2R-S-56
RN138
4P2R-S-56
2
4
2
4
3
1
1
3
4
2
2
4
MD20
MD21
MD14
MD15
RN142
4P2R-S-56
RN144
4P2R-S-56
2
4
2
4
1
3
1
3
2
4
2
4
MD43
MD42
MD49
MD52
RN148
4P2R-S-56
RN150
4P2R-S-56
1
3
1
3
RN103
4P2R-S-56
RN106
4P2R-S-56
M_B_SRASA#
M_B_BMWEA#
M_B_BA0
1
3
1
3
2
4
2
4
1
3
1
3
2
4
2
4
SM_CS3#
M_B_SCASA#
M_B_MA4
M_B_MA2
RN94
4P2R-S-56
RN97
4P2R-S-56
M_B_MA12
CKE3
M_B_MA8
M_B_MA6
1
3
1
3
2
4
2
4
1
3
1
3
2
4
2
4
M_B_BA1
M_B_MA0
M_B_MA9
M_B_MA7
RN104
4P2R-S-56
RN107
4P2R-S-56
SMDDR_VTERM
4P2R-S-56
RN102
2
4
2
4
2
4
2
4
SMDDR_VTERM
RN93
4P2R-S-56
RN96
4P2R-S-56
M_B_MA10
M_B_MA1
M_B_MA3
M_B_MA5
1
3
1
3
2
4
2
4
1
3
1
3
2
4
2
4
SM_CS1#
M_A_SCASA#
M_A_MA1
M_A_MA10
RN123
4P2R-S-56
RN125
4P2R-S-56
M_A_BA1
M_A_SRASA#
M_A_BA0
M_A_BMWEA#
1
3
3
1
2
4
4
2
1
3
1
3
2
4
2
4
M_A_MA0
M_A_MA4
M_A_MA2
RN131
4P2R-S-56
RN133
4P2R-S-56
CKE1
M_A_MA12
M_A_MA5
M_A_MA3
3
1
1
3
4
2
2
4
1
3
1
3
2
4
2
4
M_A_MA8
M_A_MA6
M_A_MA9
M_A_MA7
RN114
4P2R-S-56
RN117
4P2R-S-56
RN124
4P2R-S-56
RN126
4P2R-S-56
RN132
4P2R-S-56
RN134
4P2R-S-56
RN139
4P2R-S-56
M_A_MA11
CKE0
1
3
2
4
1
3
2
4
SM_CS0#
M_A_MA13
RN140
4P2R-S-56
RN145
4P2R-S-56
CKE2
M_B_MA11
1
3
2
4
1
3
2
4
SM_CS2#
M_B_MA13
RN146
4P2R-S-56
M_A_MA[0..13]
M_A_BA0
M_A_BA1
M_A_SRASA#
M_A_SCASA#
M_A_BMWEA#
For terminal R-pack.
SMDDR_VTERM
AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5
DDR SYSTEM MEMORY A
RN63
4P2R-S-10
RN64
4P2R-S-10
U38G
DDR SYSTEM MEMORY B
C994
C995
C996
C997
C998
C999
C1000
C1001
C1002
C1003
C1004
C1005
C1006
C1007
C1008
C1009
C1010
C1011
C1012
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
CKE[0..3]
SDM0
R656
1
56R
2
R657
1
56R
2
SDM4
SDM1
R658
1
56R
2
R659
1
56R
2
SDM5
SDM2
R660
1
56R
2
R661
1
56R
2
SDM6
SDM3
R662
1
56R
2
R663
1
56R
2
SDM7
R664
SM_DQS0 1
56R
2
R665
1
56R
2
SM_DQS4
R666
SM_DQS1 1
56R
2
R667
1
56R
2
SM_DQS5
R668
SM_DQS2 1
56R
2
R669
1
56R
2
SM_DQS6
R670
SM_DQS3 1
56R
2
R671
1
56R
2
SM_DQS7
M_A_MA[0..13] 13
M_A_BA0 13
M_A_BA1 13
M_A_SRASA# 13
M_A_SCASA# 13
M_A_BMWEA# 13
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
5,13
5,13
5,13
5,13
CKE[0..3]
5,13
M_B_MA[0..13]
M_B_BA0
M_B_BA1
M_B_SRASA#
M_B_SCASA#
M_B_BMWEA#
M_B_MA[0..13]
M_B_BA0 13
M_B_BA1 13
M_B_SRASA#
M_B_SCASA#
M_B_BMWEA#
MD[0..63]
SM_DQS[0..7]
SDM[0..7]
13
13
13
13
MD[0..63] 13
SM_DQS[0..7] 13
SDM[0..7] 13
SMDDR_VTERM
C1013
C1014
C1015
C1016
C1017
C1018
C1019
C1020
C1021
C1022
C1023
C1024
C1025
C1026
C1027
C1028
C1029
C1030
C1031
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
PROJECT : CT3

Size
Document Number
Custom
ALVISO
Date:
Rev
1A
DDR
Sheet
7
8
of
39
+2.5V
C792
0.1U
0.1U
10U/10V/0805
C801
C802
0.1U
4.7U/10V
+1.5V
V2.5_DDR_CAP6
V2.5_DDR_CAP3
V2.5_DDR_CAP4
1.05A
C793
C794
C795
0.1U
0.1U
0.1U
L59
VCC_DDRDLL
C817
+ C796
60mA
+2.5V
C797
10U/10V/0805
330U/6.3V/ESR-25
Note: All VCCSM pins

shorted internally.
125mA
BLM11A121S
+ C812
C813
100U
0.1U
1A
C818
+ C816 BLM11A121S
220U
10U/10V/0805 10U/10V/0805
C798
10U/10V/0805
Note: All VCCSM pins

shorted internally.
C803
0.1U
+1.5V
C819
0.1U
C804
0.1U
+2.5V
2mA
C820
10U/10V/0805
C821
10uH
2.5VSUS
C799
0.022U
C806
0.022U
L60
BLM11A121S
+1.5V
C808
0.022U
C814
0.022U
C809
0.1U
L61
+2.5V
+1.5V
C822
0.1U
0.01U_0402
C823
C824
0.1U
10U/10V/0805
+1.5V
C781
0.1U
L57
VCCA_TVDACC1
VCCA_TVDACC0
VCCA_TVDACB1
VCCA_TVDACB0
VCCA_TVDACA1
VCCA_TVDACA0
40mA
VSSA_TVBG
VCCA_TVBG
E18
F18
C18
D18
E17
F17
150mA
10uH
VCCDQ_TVDAC
VCCD_TVDAC
2mA
L56
G18
H18
C777
0.1U
H17
D19
D21
RB751V-40
40mA
VCCD_LVDS2
VCCD_LVDS1
VCCD_LVDS0
U38H
C769
0.1U
1uH
VCCA_LVDS
L55
60mA
VCC3G_PCIE
C767
0.022U
A25
B25
B26
640mA
+ C764
470U
A35
C765
0.1U
1uH
VCCHV2
VCCHV1
VCCHV0
L53
A21
B21
B22
10U/10V/0805
K17
K18
T18
V18
W18
K19
U19
V19
K20
T20
U20
W20
K21
K22
K23
K24
J25
K25
H26
K26
H27
J27
K27
L27
M27
N27
P27
R27
T27
U27
V27
G28
H28
J28
K28
L28
M28
N28
P28
R28
T28
U28
V28
J29
K29
M29
N29
R29
T29
C779
VCC48
VCC47
VCC46
VCC45
VCC44
VCC43
VCC42
VCC41
VCC40
VCC39
VCC38
VCC37
VCC36
VCC35
VCC34
VCC33
VCC32
VCC31
VCC30
VCC29
VCC28
VCC27
VCC26
VCC25
VCC24
VCC23
VCC22
VCC21
VCC20
VCC19
VCC18
VCC17
VCC16
VCC15
VCC14
VCC13
VCC12
VCC11
VCC10
VCC9
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
VCC0
+2.5V
0.1U/0402
AA2
AA1
C35
B23
AC1
AC2
C778
VCCA_MPLL
VCCA_HPLL
VCCA_DPLLB
VCCA_DPLLA
VCCH_MPLL0
VCCH_MPLL1
VCCP
C766
0.1U
VVSSA_CRTDAC
VCCA_CRTDAC1
VCCA_CRTDAC0
4.7U/10V
1
R558
10R
H20
C771
2.2U
BLM11A121S
G19
E19
F19
C770
L54
VCC_SYNC
+2.5V
10mA
VCCSM64
VCCSM63
VCCSM62
VCCSM61
VCCSM60
VCCSM59
VCCSM58
VCCSM57
VCCSM56
VCCSM55
VCCSM54
VCCSM53
VCCSM52
VCCSM51
VCCSM50
VCCSM49
VCCSM48
VCCSM47
VCCSM46
VCCSM45
VCCSM44
VCCSM43
VCCSM42
VCCSM41
VCCSM40
VCCSM39
VCCSM38
VCCSM37
VCCSM36
VCCSM35
VCCSM34
VCCSM33
VCCSM32
VCCSM31
VCCSM30
VCCSM29
VCCSM28
VCCSM27
VCCSM26
VCCSM25
VCCSM24
VCCSM23
VCCSM22
VCCSM21
VCCSM20
VCCSM19
VCCSM18
VCCSM17
VCCSM16
VCCSM15
VCCSM14
VCCSM13
VCCSM12
VCCSM11
VCCSM10
VCCSM9
VCCSM8
VCCSM7
VCCSM6
VCCSM5
VCCSM4
VCCSM3
VCCSM2
VCCSM1
VCCSM0
VCCP
4
V2.5_DDR_CAP1
C811
V2.5_DDR_CAP2
C810
0.5/F
AE1
AM1
AP8
AB9
AB10
AB11
AC11
AD11
AE12
AF12
AG12
AH12
AJ12
AK12
AL12
AM12
AN12
AP12
AE13
AF13
AG13
AH13
AJ13
AK13
AL13
AM13
AN13
AP13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AF25
AG25
AH25
AJ25
AK25
AL25
AM25
AN25
AP25
AE26
AF26
AG26
AH26
AJ26
AK26
AL26
AM26
AN26
AP26
AC27
AD27
AD28
AP29
AH37
AM37
V2.5_DDR_CAP5
R561
VCCTX_LVDS2
VCCTX_LVDS1
VCCTX_LVDS0
0.47U
A27
A28
B28
C775
0.47U
VCCA_SM3
VCCA_SM2
VCCA_SM1
VCCA_SM0
VCC3G6
VCC3G5
VCC3G4
VCC3G3
VCC3G2
VCC3G1
VCC3G0
C774
0.22U
AF18
AF19
AP19
AF20
J37
L37
N37
R37
U37
W37
AE37
VCCA_3GPLL2
VCCA_3GPLL1
VCCA_3GPLL0
VSSA_3GBG
VCCA_3GBG
C773
VCC_DDRDLL
500mA
VCC3G_PCIE
VCCA_3GPLL
VCCA_3GPLL
Y27
Y28
Y29
G37
F37
C772
VCCP_GMCH_CAP1
G1
M1
N1
V1
B2
M2
N2
M3
N3
M4
N4
M5
N5
A6
M6
N6
M7
N7
M8
N8
J9
L9
M9
N9
P9
R9
U9
W9
Y9
J10
K10
M10
N10
P10
R10
T10
U10
V10
W10
K11
L11
M11
N11
P11
R11
T11
U11
V11
W11
K12
J13
K13
0.22U
VCCP_GMCH_CAP2
VCCP_GMCH_CAP3
VCCP_GMCH_CAP4
VTT51
VTT50
VTT49
VTT48
VTT47
VTT46
VTT45
VTT44
VTT43
VTT42
VTT41
VTT40
VTT39
VTT38
VTT37
VTT36
VTT35
VTT34
VTT33
VTT32
VTT31
VTT30
VTT29
VTT28
VTT27
VTT26
VTT25
VTT24
VTT23
VTT22
VTT21
VTT20
VTT19
VTT18
VTT17
VTT16
VTT15
VTT14
VTT13
VTT12
VTT11
VTT10
VTT9
VTT8
VTT7
VTT6
VTT5
VTT4
VTT3
VTT2
VTT1
VTT0
+1.5V
6
7
POWER
C788
0.022U
C790
0.022U
C805
0.1U
L58
BLM11A121S
Date:
7
45mA
70mA
+ C768
470U
+1.5V
+ C776
470U
+1.5V
VCCP
+ C780
470U
+1.5V
3.7A
VCCP
C782
C783
C784
C785
0.1U
0.1U
0.1U
10U/10V/0805
10U/10V/0805
10U/10V/0805
+1.5V
+3V
D22
RB751V-40
R559
10R
C786
Size
Document Number
Custom
ALVISO
C787
120mA
R560
0R
C789
0.1U
C791
0.1U
C
C800
0.1U
C807
0.1U
BLM11A121S
+1.5V
24mA
C815
0.1U
+1.5V
VCC3G_PCIE
L62
D
PROJECT : CT3
POWER
Sheet
8
8
of
39
Rev
1A
1
2
3
U38D
L12
M12
N12
P12
R12
T12
U12
V12
W12
L13
M13
N13
P13
R13
T13
U13
V13
W13
Y12
AA12
Y13
AA13
L14
M14
N14
P14
R14
T14
U14
V14
W14
Y14
AA14
AB14
L15
M15
N15
P15
R15
T15
U15
V15
W15
Y15
AA15
AB15
L16
M16
N16
P16
R16
T16
U16
V16
W16
Y16
AA16
AB16
R17
Y17
AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20
R21
Y21
AA21
AB21
Y22
AA22
AB22
Y23
AA23
AB23
Y24
AA24
AB24
Y25
AA25
AB25
Y26
AA26
AB26
VSS271
VSS270
VSS269
VSS268
VSS267
VSS266
VSS265
VSS264
VSS263
VSS262
VSS261
VSS260
VSS259
VSS258
VSS257
VSS256
VSS255
VSS254
VSS253
VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSSALVDS
U38E
Y1
D2
G2
J2
AL24
AN24
A26
E26
G26
J26
B27
L2
P2
T2
V2
AD2
AE2
AH2
AL2
AN2
A3
C3
AA3
AB3
AC3
AJ3
C4
H4
L4
P4
U4
Y4
AF4
AN4
E5
W5
AL5
AP5
B6
J6
L6
P6
T6
AA6
AC6
AE6
AJ6
G7
V7
AA7
AG7
AK7
AN7
C8
E8
L8
P8
Y8
AL8
A9
H9
K9
T9
V9
AA9
AC9
AE9
AH9
AN9
D10
L10
Y10
AA10
F11
H11
Y11
AA11
AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23
B36
VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0
VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0
3
5
VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10
VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0
VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70
VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11
VCC_NCTF10
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0
AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26
L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25
V25
W25
L26
M26
N26
P26
R26
T26
U26
V26
W26
B24
D24
F24
J24
AG24
AJ24
E27
G27
W27
AA27
AB27
AF27
AG27
AJ27
AL27
AN27
E28
W28
AA28
AB28
AC28
A29
D29
E29
F29
G29
H29
L29
P29
U29
V29
W29
AA29
AD29
AG29
AJ29
AM29
C30
Y30
AA30
AB30
AC30
AE30
AP30
D31
E31
F31
G31
H31
J31
K31
L31
M31
N31
P31
R31
T31
U31
V31
W31
AD31
AG31
AL31
A32
C32
Y32
AA32
AB32
AC32
AD32
AJ32
AN32
D33
E33
F33
G33
H33
J33
K33
L33
M33
N33
P33
R33
T33
U33
V33
W33
AD33
AF33
AL33
C34
AA34
AB34
AC34
AD34
AH34
AN34
B35
D35
E35
F35
G35
H35
J35
K35
L35
M35
N35
P35
R35
T35
U35
V35
W35
Y35
AE35
C36
AA36
AB36
AC36
AD36
AE36
AF36
AJ36
AL36
AN36
E37
H37
K37
M37
P37
T37
V37
Y37
AG37
1
6
VCCP
Date:
7
A
A
VSS
B
B
VCCP
NCTF
2.5VSUS
D
PROJECT : CT3
Size
Document Number
Custom
ALVISO VSS/NCTF
Rev
1A
Sheet
9
8
of
39
VCCP
56R
RCIN#
R565
10K
GATEA20R566
10K
PIORDY R567
R564
10M
Y10
+3V
+3V
4.7K
+3V
C826
15P
32.768KHZ
R569
VCCRTC
3
3
3
3
3
3
27
27
RTC
1M
SM_INTRUDER#
NMI
A20M#
FERR# R571
IGNNE#
INTR
CPUINIT#
RCIN#
GATEA20
NMI
A20M#
FERR#
IGNNE#
INTR
CPUINIT#
RCIN#
GATEA20
14,17,23 AD[0..31]
VCCRTC
VCCRTC
C827
1U/16V
RB500V-40
R577
20K
RTCRST#
2
C828
1U/16V
RB500V-40
B
G1
D24
5VPCU
3VRTC
BT1
RTC-BAT
RTC_N01 R578
*SHORT_ PAD1
3K
Q49
MMBT3904
R579
4.7K
C829
1000P
RTC_N02
R580
15K
PCLK_ICH
R676
*22R
14,17,23 PCI_PME#
2
PCLK_ICH
C1033
*22P
PCLK_ICH
PCI_RST#
PLTRST#_1
R581
+3V
2
PLTRST#
4
1
PLTRST#_1
7SZ32
28
28
28
28
28
28
28
28
28
28
28
28
+3V
C831
INTRUDER#
INTVRMEN
AF25
AF23
AF24
AG26
AG24
AF27
AD23
AF22
NMI
A20M#
FERR#
IGNNE#
INTR
INIT#
RCIN#
A20GATE
PDD[0..15]
PDCS1#
PDCS3#
PDA0
PDA1
PDA2
PDIOR#
PDIOW#
PIORDY
IRQ14
PDDREQ
PDDACK#
E2
E5
C2
F5
F3
E9
F2
D6
E6
D3
A2
D2
D5
H3
B4
J5
K2
K5
D4
L6
G3
H4
H2
H5
B3
M6
B2
K6
K3
A5
L1
K4
R583
PCIRST#
2
3
PCI_RST#
47R
CPU
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LPC_DRQ0#
GPI41
27
27
27
27
27
LFRAME#/FWH4
AG25 CPUPWRGD
CPUPWRGD
AE22
T257
R572
AE23 THERMTRIP#_ICH
R573
0R
AG27
STPCLK#
AE26
R574
*0R
AE27
R575
0R
AD27
R576
0R
AE24
P6
G6
R2
R5
AF19
PME#
PCICLK
PCIRST#
PLTRST#
CLKRUN#/GPIO32
AD14
AF15
AF14
AD12
AE14
AC11
AD11
AB11
AE13
AF13
AB12
AB13
AC13
AE15
AG15
AD13
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
J6
H6
G4
G2
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
SERR#
PERR#
PLOCK#
J3
A3
J2
C3
J1
E1
G5
E3
C5
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#/GPI40
REQ5#/GPI1
REQ6#/GPI0
L5
B5
M5
B8
F7
E8
B7
GNT0#
GNT1#
GNT2#
GNT3#
GNT4#/GPO48
GNT5#/GPO17
GNT6#/GPO16
C1
B6
F1
C8
E7
F6
D8
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPI2
PIRQF#/GPI3
PIRQG#/GPI4
PIRQH#/GPI5
N2
L2
M1
L3
D9
C7
C6
M3
AD16
AE17
AC16
AB17
AC17
AE16
AC14
AF16
AB16
AB14
AB15
DCS1#
DCS3#
DA0
DA1
DA2
DIOR#
DIOW#
IORDY
IDEIRQ
DDREQ
DDACK#
SATALED#
ICH6-M_14
14,17,23,27
C/BE0#
C/BE1#
C/BE2#
C/BE3#
PCI
1
4
P2
N3
N5
N4
N6
P4
P3
R574
R576
For Doathan A-X step
56
*0
For Doathan B-X step & later
*0
Description
VCCP
27
R570
75R
CPUPWRGD/GPO49
INIT3_3V#
THRMTRIP#
SMI#
STPCLK#
CPUSLP#
DPSLP#/TP[2]
DPRSLP#/TP[4]
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
0.1U
PDD[0..15]
PDCS1#
PDCS3#
PDA0
PDA1
PDA2
PDIOR#
PDIOW#
PIORDY
IRQ14
PDDREQ
PDDACK#
AA3
AA5
IDE
U41
1 0.047U
C830 2
RTCRST#
LAD0
LAD1/FB1
LAD2/FB2
LAD3/FB3
LDRQ0#
LDRQ1#/GPI41
LFRAME#
PCI Pullups
56R
THRMTRIP# 3,5
SMI#
3
STPCLK# 3
H_CPUSLP# 3,5
H_DPSLP# 3
H_DPRSTP# 3
+3V
RP51
REQ2#
STOP#
REQ0#
INTB#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
SERR#
PERR#
PLOCK#
REQ0#
REQ1#
REQ2#
REQ3#
GPI40
LBAYID0
LBAYID1
C/BE0#
C/BE1#
C/BE2#
C/BE3#
14,17,23
14,17,23
14,17,23
14,17,23
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
SERR#
PERR#
PLOCK#
14,17,23
14,17,23
14,17,23
14,17,23
14,17,23
14,17,23
14,17,23
14,17,23
17
REQ0#
REQ1#
REQ2#
17
14
23
INTB#
INTH#
8.2KX8
RP52
11,14,17,27 SERIRQ
REQ3#
SERIRQ
+3V
AE3
AD3
AG2
AF2
T292
T293
SATA2_RXN
SATA2_RXP
SATA2_TXN
SATA2_TXP
AD7
AC7
AF6
AG6
T294
T295
SATA_CLKN
SATA_CLKP
AC2
AC1
SATARBIAS#
SATARBIAS
AG11
AF11
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
ACZ_SDO
F11
F10
B10
C9
6
7
8
9
10
5
4
3
2
1
FRAME#
TRDY#
IRQ14
CRT_SENSE#
CRT_SENSE# 11,30
8.2KX8
+3V
RP53
IRDY#
DEVSEL#
REQ1#
PLOCK#
17
14
23
6
7
8
9
10
INTA#
23
INTC#
INTD#
INTE#
INTF#
INTG#
14
14
17
17
17
These signals
have internal
pull-up
5
4
3
2
1
LBAYID1
PERR#
SERR#
LBAYID0
+3V
RP54
INTG#
INTF#
INTE#
INTH#
PIRQA#: RTL8100CL
PIRQB#: NC
PIRQC#: MINI PCI
PIRQD#: MINI PCI
PIRQE#: 7411
PIRQF#: 7411
PIRQG#: 7411
PIRQH#: Internal USB
Connect to GND if
S-ATA didn't use on
platform
7
5
3
1
8
6
4
2
8P4R-8.2K
T307
C10
B9
A10 R706
INTA#
INTD#
INTC#
8.2KX8
GNT0#
GNT1#
GNT2#
T260
T261
T262
T263
AC19
5
4
3
2
1
+3V
+3V
SATA0_RXN
SATA0_RXP
SATA0_TXN
SATA0_TXP
ACZ_BIT_CLK
ACZ_SYNC
ACZ_RST#
6
7
8
9
10
+3V
8.2K
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
3VSUS
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
14,17,23 CLKRUN#
5,11,28 PLTRST#
56R
RTCX1
RTCX2
AA2
AD[0..31]
D23
3VPCU
Y1
Y2
RTCRST#
C825
15P
Internal already pull-up
U40A
CLK_32KX1
CLK_32KX2
RTC
*56R
LPC
H_DPSLP# R563
SATA
R562
AC-97/
AZALIA
FERR#
GPI40
R749
8.2K
GPI41
R750
8.2K
PV stage:
GPI40 & GPI41 for bios request.
Griffey 12/23/2004
SI stage:
Intel suggested us to add a terminal resistor R706 for
-CODEC_RST to improve signal quality.
Sting 10/12/2004
33R
AC_SDIN2
BITCLK
14,20,22
SYNC1
14,20,22
-CODEC_RST 14,20,22
SDINA
SDINB
T269
SDOUT1
20,22
14
0-AC97
1-MODEM
14,20,22
U42
TC7SH08FU
PROJECT : CT3
R584
*0R
Size
Document Number
Custom
ICH6-M
Date:
1

7
Rev
2A
(CPU/PCI/IDE)
Sheet
10
8
of
39
U40B
CLK48_USB
14M_ICH
R677
22R
R678
*22R
C1034
5.6P
C1035
*22P
19
19
USBP0+
USBP0-
32
32
USBP2+
USBP2-
31
31
USBP4+
USBP4-
CLK48_USB
5
5
5
5
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
5
5
5
5
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
2
2
SRC_ICH#
SRC_ICH
2
2
10K
*10K
DASP_ON
SUSB#
R624
R588
R590
*10K
10K
10K
PLTRST#
PWROK
RSMRST#
27
27
3VSUS
D25
1
SCI#
SWI#
8
6
4
2
SUS_STAT#
BATLOW#
DBR#
RI#
14,27
27,32
RF_OFF#
BT_OFF#
8P4R-10K
2
R738
R739
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
V25
V24
U27
U26
DMI1_RXN
DMI1_RXP
DMI1_TXN
DMI1_TXP
DMI3_RXN
DMI3_RXP
DMI3_TXN
DMI3_TXP
SRC_ICH#
SRC_ICH
AD25
AC25
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
F24
F23
HSIN2
HSIP2
HSON2
HSOP2
M25
M24
L27
L26
HSIN3
HSIP3
HSON3
HSOP3
P24
P23
N27
N26
15
DMI0_RXN
DMI0_RXP
DMI0_TXN
DMI0_TXP
SMBCLK
SMBDATA
SMBALERT#/GPI11
RI#
ICH_THRM#
PWROK
DPRSLPVR
BATLOW#
DNBSWON#
RSMRST#
IMVPOK
PM_BMBUSY#
SUS_STAT#
SUSCLK
T2
AC20
AA1
AE20
V2
U1
Y3
AF21
AD19
W3
V6
14M_ICH
SPK
CRT_SENSE#
KBSMI#
SCI_#
SWI_#
E10
F8
AE19
R1
M2
R6
AB21
AD20
AD21
V3
SB_RF_OFF#
SB_BT_OFF#
8
6
4
2
SWI_#
LCDID0
SMLINK1
SMLINK0
8P4R-10K
PV stage:
1. Add RF_OFF# and BT_OFF#
circuit.
Griffey 12/10/2004
RI#
THRM#
PWROK
DPRSLPVR/TP1
BATLOW#/TP0
PWRBTN#
RSMRST#
VRMPWRGD
BM_BUSY#/GPIO6
SUS_STAT#/LPCPD#
SUSCLK
CLK14
SPKR
GPI7
GPI8
GPI12
GPI13
GPO19
GPO21
GPO23
GPIO24
AC5
AD5
AF4
AG4
AC9
R591
*10K
3V_S5
+3V
3VSUS
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
5
5
5
5
24.9/F
+1.5V
Place within 500mils of ICH-6
T279
T281
T283
T285
SM_EN#
SATA0GP
FPBACK#
LCDID1
SATA1GP
SATA2GP
SATA3GP
AF20
AC18
DASP_ON
LCDID2
PLTRST#
DBR#
PCIE_WAKE#
MCH_SYNC#
+3V
RP56
SATA1GP
SATA2GP
SATA3GP
SATA0GP
2
4
6
8
1
3
5
7
8P4R-10K
SUSB#
27
SUSC#
27
T286
PLTRST# 5,10,28
DBR#
3
These signals should be

pulled-up to +3V via a 8.2K~10K
if didn't used as S-ATA interlock
switch or GPI signals.
LAN_RST# should be connected to

PLTRST# if internal LAN didn't use.
STP_PCI# 2
STP_CPU# 2,33
SERIRQ 10,14,17,27
T288
FPBACK# 15
LCDID1
15
DASP_ON 28
LCDID2
15
MCH_SYNC#
E12
E11
C13
C12
C11
E13
R589
10K
+3V
F12
B11
AD9
AF8
AG8
U3
SI stage:
R589 should be populated, because
MCH_SYNC# is internally ANDed with
PWROK.System will not booting
without this pulled-up resistor.
3V_S5
Sting 09/24/2004
Enable Cable ID
1
10K ICH_THRM#
10K SCI_#
3V_S5
R593
OC0#
OC3#
OC2#
OC1#
SUSC#
R594
*10K
R710
R711
5
5
5
5
T271
T273
T275
T277
P5
AF17
R3
T3
AE18
AF18
AG18
RSVD6
RSVD7
RSVD8
RSVD9
5
4
3
2
1
22.6/F
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
R586
STP_PCI#
STP_CPU#
SERIRQ
RESERVED
6
7
8
9
10
10KX8
ICH6-M_14
3V_S5
8P4R-10K
680R
C832
*0.1U
8
6
4
2
PDAT_SMB
PCLK_SMB
SMBALERT#
SMB_LINK_ALERT#
DMI_ZCOMP
AC21
AD22
AB20
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
32
32
RP55
OC5#
OC6#
OC7#
OC4#
Place within 500mils of ICH-6
STP_PCI#/GPO18
STP_CPU#/GPO20
SERIRQ
LAN
USBP5+
USBP5-
R585
T4
T5
T6
V5
U2
U5
AG21
GPIO33
GPIO34
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
USBRBIAS
SLP_S3#
SLP_S4#
SLP_S5#
LAN_RST#
SYS_RESET#
WAKE#
MCH_SYNC#
MISC&GPIO
19
19
OC7#
SUSB#
SUSC#
PM
USBP1+
USBP1-
3VSUS
SMLINK0
SMLINK1
SMB_LINK_ALERT#
GPIO25
SATA0GP/GPIO26
GPIO27
GPIO28
SATA1GP/GPIO29
SATA2GP/GPIO30
SATA3GP/GPIO31
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
OC3#
USBP5+
USBP5OC5#
W4
U6
Y5
SMLINK0
SMLINK1
LINKALERET#
LAN_CLK
LAN_RSTSYNC
RP59
7
5
3
1
PCI-EXPRESS
SM&SMI
D12
B12
D11
F13
LCDID0
DMI2_RXN
DMI2_RXP
DMI2_TXN
DMI2_TXP
DMI
Y4
W5
W6
PCLK_SMB
PDAT_SMB
SMBALERT#
HSIN0
HSIP0
HSON0
HSOP0
RP58
7
5
3
1
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
T25
T24
R27
R26
RP57
7
5
3
1
AB24
AB23
AA27
AA26
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
CLK48
HSIN1
HSIP1
HSON1
HSOP1
1SS355
2
1
2
D26
1SS355
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
A27
T278
T280
T282
T284
2
14M_ICH
20
SPK
10,30 CRT_SENSE#
27
KBSMI#
Y25
Y24
W27
W26
CLK48_USB
USBP1P
USBP1N
OC1#
USBP3P
USBP3N
OC3#
USBP5P
USBP5N
OC5#/GPI10
USBP7P
USBP7N
OC7#/GPI15
USBRBIAS
USBRBIAS#
USB
K25
K24
J27
J26
T296
USBP1+
USBP1OC1#
OC6#
USBP0P
USBP0N
OC0#
USBP2P
USBP2N
OC2#
USBP4P
USBP4N
OC4#/GPI9
USBP6P
USBP6N
OC6#/GPI14
H25
H24
G27
G26
PCLK_SMB
PDAT_SMB
B20
A20
B27
B18
A18
C26
A16
B16
D23
B14
A14
C24
B22
A22
D21
C21
C27
C19
D19
B26
D17
E17
C23
D15
C15
C25
T270
T272
T274
T276
17
RI#
3
ICH_THRM#
27
PWROK
33
DPRSLPVR
27
BATLOW#
27
DNBSWON#
27
RSMRST#
5,33
IMVPOK
5 PM_BMBUSY#
+3V
R587
R595
USBP0+
USBP0OC0#
USBP2+
USBP2OC2#
USBP4+
USBP4OC4#
R596
*1K
U44A
6
RN151
3
*NC7WZ14P6X
+3V
U44B
4
RSMRST#
LCDID0
LCDID1
LCDID2
*NC7WZ14P6X
R598
*0R
1
3
5
7
2
4
6
8
8P4R-10K
PCIE_WAKE#
1. Change the power plane of PCIE_WAKE#

from 3VSUS to 3V_S5 to solve system can't
turn off issue.
2. Change the power plane of ICH_THRM#
and SCI_# from 3VSUS to +3V to solve
leakage issue.
Sting 10/06/2004
A
PROJECT : CT3

Size
Document Number
Custom
ICH6-M
Date:
C
Rev
2A
(USB/HUB/LPC)
Sheet
E
11
of
39
U40C
L63
1
+1.5V
600mA
+1.5V_PCIE
+ C833
BLM41P600SPG
220U/4V
C834
C835
C836
0.1U
0.1U
0.1U
+5V
R599
+3V
10R
D27
V5REF
1
RB751V-40
C844
C845
1U/16V
0.1U
PV stage:
The root cause that is 3V_S5 leakage
current to 5VSUS by R712 on S4/S5 stage.
SI stage:
Griffey 12/13/2004
We can also use 5VSUS to instead of 5V_S5
to save cost if 5V_S5 isn't implemetation on
Sting 10/12/2004
system.
R600
5V_S5
10R
*10R
R712
5VSUS
D28
2
3V_S5
V5REF_SUS
RB751V-40
C853
C854
1U/16V
0.1U
+1.5V
+1.5V
C856
C861
C862
C863
0.1U
0.1U
0.1U
0.1U
C857
0.1U
+1.5V
R601
L64
2
1R
BLM11A121S
C867
C868
10U/10V/0805
0.01U_0402
C858
0.1U
AA22
AA23
AA24
AA25
AB25
AB26
AB27
F25
F26
F27
G22
G23
G24
G25
H21
H22
J21
J22
K21
K22
L21
L22
M21
M22
N21
N22
N23
N24
N25
P21
P25
P26
P27
R21
R22
T21
T22
U21
U22
V21
V22
W21
W22
Y21
Y22
AA6
AB4
AB5
AB6
AC4
AD4
AE4
AE5
AF5
AG5
AA7
AA8
AA9
AB8
AC8
AD8
AE8
AE9
AF9
AG9
AC27
E26
+3V
C870
AE1
AG10
+1.5V
0.1U
C871
+3V
C872
0.1U
0.1U
A11
U4
V1
V7
W2
Y7
3V_S5
C875
C876
0.1U
0.1U
A13
F14
G13
G14
3V_S5
C878
C879
0.1U
0.1U
A17
B17
C17
F18
G17
G18
U40D
VCC1_5_1
VCC1_5_2
VCC1_5_3
VCC1_5_4
VCC1_5_5
VCC1_5_6
VCC1_5_7
VCC1_5_8
VCC1_5_9
VCC1_5_10
VCC1_5_11
VCC1_5_12
VCC1_5_13
VCC1_5_14
VCC1_5_15
VCC1_5_16
VCC1_5_17
VCC1_5_18
VCC1_5_19
VCC1_5_20
VCC1_5_21
VCC1_5_22
VCC1_5_23
VCC1_5_24
VCC1_5_25
VCC1_5_26
VCC1_5_27
VCC1_5_28
VCC1_5_29
VCC1_5_30
VCC1_5_31
VCC1_5_32
VCC1_5_33
VCC1_5_34
VCC1_5_35
VCC1_5_36
VCC1_5_37
VCC1_5_38
VCC1_5_39
VCC1_5_40
VCC1_5_41
VCC1_5_42
VCC1_5_43
VCC1_5_44
VCC1_5_45
VCC
VCC1_5_79
VCC1_5_80
VCC1_5_81
VCC1_5_82
VCC1_5_83
VCC1_5_84
VCC1_5_85
VCC1_5_86
VCC1_5_87
VCC1_5_88
VCC1_5_89
VCC1_5_90
VCC1_5_91
VCC1_5_92
VCC1_5_93
VCC1_5_94
VCC1_5_95
VCC1_5_96
VCC1_5_97
VCC1_5_98
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
VCC3_3_7
VCC3_3_8
VCC3_3_9
VCC3_3_10
VCC3_3_11
VCC3_3_12
VCC3_3_13
VCC3_3_14
VCC3_3_15
VCC3_3_16
VCC3_3_17
VCC3_3_18
VCC3_3_19
VCC3_3_20
VCC3_3_21
VCCSUS1_5_1
VCC1_5_46
VCC1_5_47
VCC1_5_48
VCC1_5_49
VCC1_5_50
VCC1_5_51
VCC1_5_52
VCC1_5_53
VCC1_5_54
VCC1_5_55
VCCSUS1_5_2
VCCSUS1_5_3
VCC1_5_67
VCC1_5_68
VCC1_5_69
VCC1_5_70
VCC1_5_71
VCC1_5_72
VCC1_5_73
VCC1_5_74
VCC1_5_75
VCC1_5_76
VCC1_5_77
VCC1_5_78
VCC1_5_56
VCC1_5_57
VCC1_5_58
VCC1_5_59
VCC1_5_60
VCC1_5_61
VCC1_5_62
VCC1_5_63
VCC1_5_64
VCC1_5_65
VCC2_5_2
VCC2_5_4
V5REF1
V5REF2
VCCDMIPLL
VCC3_3_1
V5REF_SUS
VCCSATAPLL
VCC3_3_22
VCCUSBPLL
VCCSUS3_3_20
VCCLAN3_3/VCCSUS3_3_1
VCCRTC
VCCSUS3_3_1
VCCSUS3_3_2
VCCSUS3_3_3
V_CPU_IO1
VCCSUS3_3_4
V_CPU_IO2
VCCSUS3_3_5
V_CPU_IO3
VCCSUS3_3_6
VCCSUS3_3_13
VCCSUS3_3_7
VCCSUS3_3_14
VCCSUS3_3_8
VCCSUS3_3_15
VCCSUS3_3_9
VCCSUS3_3_16
VCCSUS3_3_10
VCCSUS3_3_17
VCCSUS3_3_11
VCCSUS3_3_18
VCCSUS3_3_12
VCCSUS3_3_19
AA19
AA20
AA21
L11
L12
L14
L16
L17
M11
M17
P11
P17
T11
T17
U11
U12
U14
U16
U17
F9
A1
A12
A15
A19
A21
A23
A26
A4
A7
A9
AA11
AA13
AA16
AA4
AB1
AB10
AB19
AB2
AB7
AB9
AC10
AC12
AC22
AC23
AC24
AC26
AC3
AC6
AD1
AD10
AD15
AD18
AD2
AD24
AD6
AE10
AE11
AE12
AE2
AE21
AE25
AE6
AE7
AF1
AF10
AF12
AF26
AF3
AF7
AG1
AG12
AG14
AG17
AG20
AG22
AG3
AG7
B13
B15
B19
B21
B23
B24
B25
C14
C18
C20
C22
C4
D1
D10
D13
D14
D18
D20
D22
D7
E14
E15
E18
E19
E25
F17
F19
F22
F4
+1.5V
C837
C838
C839
C840
C841
C842
C843
0.1U
0.1U
0.1U
0.1U
0.01U_0402 10U/10V/0805
10U/10V/0805
+3V
A6
B1
E4
H1
H7
J7
L4
L7
M7
P1
AA12
AA14
AA15
AA17
AC15
AD17
AG13
AG16
AG19
AA10
C846
C847
C848
C849
0.1U
0.1U
0.1U
1U/16V
C850
C851
C852
0.1U
0.1U
1U/16V
+3V
1.5V_S5
C855
0.1U
G19
R7
U7
G8
1.5V_S5
C859
C860
0.1U
0.1U
C864
C865
C866
1U/16V
0.1U
0.1U
+1.5V
D24
D25
D26
D27
E20
E21
E22
E23
E24
F20
G20
+1.5V
P7
AB18
+2.5V
C869
A8
AA18
V5REF
F21
V5REF_SUS
0.1U
A25
A24
+1.5V
3V_S5
AB3
VCCRTC
G10
G11
1.5V_S5
C873
C874
0.01U_0402
0.1U
AB22
AD26
AG23
VCCP
C877
C16
D16
E16
F15
F16
G15
G16
VSS001
VSS002
VSS003
VSS004
VSS005
VSS006
VSS007
VSS008
VSS009
VSS010
VSS011
VSS012
VSS013
VSS014
VSS015
VSS016
VSS017
VSS018
VSS019
VSS020
VSS021
VSS022
VSS023
VSS024
VSS025
VSS026
VSS027
VSS028
VSS029
VSS030
VSS031
VSS032
VSS033
VSS034
VSS035
VSS036
VSS037
VSS038
VSS039
VSS040
VSS041
VSS042
VSS043
VSS044
VSS045
VSS046
VSS047
VSS048
VSS049
VSS050
VSS051
VSS052
VSS053
VSS054
VSS055
VSS056
VSS057
VSS058
VSS059
VSS060
VSS061
VSS062
VSS063
VSS064
VSS065
VSS066
VSS067
VSS068
VSS069
VSS070
VSS071
VSS072
VSS073
VSS074
VSS075
VSS076
VSS077
VSS078
VSS079
VSS080
VSS081
VSS082
VSS083
VSS084
VSS085
VSS086
GND
VSS087
VSS088
VSS089
VSS090
VSS091
VSS092
VSS093
VSS094
VSS095
VSS096
VSS097
VSS098
VSS099
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
G1
G12
G21
G7
G9
H23
H26
H27
J23
J24
J25
J4
K1
K23
K26
K27
K7
L13
L15
L23
L24
L25
M12
M13
M14
M15
M16
M23
M26
M27
M4
N1
N11
N12
N13
N14
N15
N16
N17
N7
P12
P13
P14
P15
P16
P22
R11
R12
R13
R14
R15
R16
R17
R23
R24
R25
R4
T1
T12
T13
T14
T15
T16
T23
T26
T27
T7
U13
U15
U23
U24
U25
V23
V26
V27
V4
W1
W23
W24
W25
W7
Y23
Y26
Y27
Y6
E27
0.1U
ICH6-M_14
VCCRTC
ICH6-M_14
3V_S5
C882
C883
C884
C885
0.1U
0.1U
0.1U
0.1U
C880
C881
0.1U
0.1U
PROJECT : CT3

Size
Document Number
Custom
ICH6-M
Date:
5
Rev
2A
(POWER)
Sheet
1
12
of
39
2.5VSUS
2.5VSUS
2.5VSUS
SMDDR_VREF
2.5VSUS
SMDDR_VREF
SODIMM0
CN14
MD1
MD0
SM_DQS0
MD7
MD2
MD8
MD13
SM_DQS1
MD11
MD10
CLK_SDRAM0
CLK_SDRAM0#
5 CLK_SDRAM0
5 CLK_SDRAM0#
MD16
MD17
SM_DQS2
MD19
MD18
MD24
MD25
SM_DQS3
B
MD26
MD31
2.5VSUS
R634
R636
200R
200R
CKE1
M_A_MA12
M_A_MA9
M_A_MA7
M_A_MA5
M_A_MA3
M_A_MA1
M_A_MA10
M_A_BA0
M_A_BMWEA#
SM_CS0#
M_A_MA13
MD33
MD32
SM_DQS4
MD34
MD35
MD40
MD41
SM_DQS5
MD46
MD47
MD53
MD48
SM_DQS6
MD50
MD51
MD56
MD60
SM_DQS7
MD59
MD58
SMBDT
SMBCK
+3V
R638
*10K
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0
VSS
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VDD
VDD
DQS2
DM2
DQ18
DQ22
VSS
VSS
DQ19
DQ23
DQ24
DQ28
VDD
VDD
DQ25
DQ29
DQS3
DM3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VDD
VDD
CB0
CB4
CB1
CB5
VSS
VSS
DQS8
DM8
CB2
CB6
VDD
VDD
CB3
CB7
DU
DU/RESET
VSS
VSS
CK2
VSS
CK2
VDD
VDD
VDD
CKE1
CKE0
DU
DU/BA2
A12
A11
A9
A8
VSS
VSS
A7
A6
A5
A4
A3
A2
A1
A0
VDD
VDD
A10/AP
BA1
BA0
RAS
WE
CAS
S0
S1
DU(A13)
DU
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VDD
VDD
DQS4
DM4
DQ34
DQ38
VSS
VSS
DQ35
DQ39
DQ40
DQ44
VDD
VDD
DQ41
DQ45
DQS5
DM5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VDD
VDD
VDD
CK1
VSS
CK1
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VDD
VDD
DQS6
DM6
DQ50
DQ54
VSS
VSS
DQ51
DQ55
DQ56
DQ60
VDD
VDD
DQ57
DQ61
DQS7
DM7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VDD
VDD
SDA
SA0
SCL
SA1
VDD(SPD)
SA2
VDD(ID)
DU
PC2100 DDR SDRAM SO-DIMM (200P)
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
SMDDR_VREF
SODIMM1
CN13
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
MD5
MD4
MD1
MD0
SDM0
MD6
SM_DQS0
MD7
MD3
MD9
MD2
MD8
MD12
SDM1
MD13
SM_DQS1
MD14
MD15
MD11
MD10
5 CLK_SDRAM3
5 CLK_SDRAM3#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
CLK_SDRAM3
CLK_SDRAM3#
MD20
MD21
MD16
MD17
SDM2
MD23
SM_DQS2
MD19
MD22
MD28
MD18
MD24
MD29
SDM3
MD25
SM_DQS3
MD30
MD27
MD26
MD31
2.5VSUS
R635
R637
200R
200R
CKE0
CKE3
M_A_MA11
M_A_MA8
M_B_MA12
M_B_MA9
M_A_MA6
M_A_MA4
M_A_MA2
M_A_MA0
M_B_MA7
M_B_MA5
M_B_MA3
M_B_MA1
M_A_BA1
M_A_SRASA#
M_A_SCASA#
SM_CS1#
M_B_MA10
M_B_BA0
M_B_BMWEA#
SM_CS2#
M_B_MA13
MD37
MD36
MD33
MD32
SDM4
MD38
SM_DQS4
MD34
MD39
MD45
MD35
MD40
MD44
SDM5
MD41
SM_DQS5
MD43
MD42
MD46
MD47
CLK_SDRAM1#
CLK_SDRAM1
CLK_SDRAM1# 5
CLK_SDRAM1 5
MD49
MD52
MD53
MD48
SDM6
MD54
SM_DQS6
MD50
MD55
MD61
MD51
MD56
MD57
SDM7
MD60
SM_DQS7
MD62
MD63
MD59
MD58
2
2
SMbus address A0
SMBDT
SMBCK
+3V
SMBDT
SMBCK
R639
*10K
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0
VSS
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VDD
VDD
DQS2
DM2
DQ18
DQ22
VSS
VSS
DQ19
DQ23
DQ24
DQ28
VDD
VDD
DQ25
DQ29
DQS3
DM3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VDD
VDD
CB0
CB4
CB1
CB5
VSS
VSS
DQS8
DM8
CB2
CB6
VDD
VDD
CB3
CB7
DU
DU/RESET
VSS
VSS
CK2
VSS
CK2
VDD
VDD
VDD
CKE1
CKE0
DU
DU/BA2
A12
A11
A9
A8
VSS
VSS
A7
A6
A5
A4
A3
A2
A1
A0
VDD
VDD
A10/AP
BA1
BA0
RAS
WE
CAS
S0
S1
DU(A13)
DU
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VDD
VDD
DQS4
DM4
DQ34
DQ38
VSS
VSS
DQ35
DQ39
DQ40
DQ44
VDD
VDD
DQ41
DQ45
DQS5
DM5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VDD
VDD
VDD
CK1
VSS
CK1
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VDD
VDD
DQS6
DM6
DQ50
DQ54
VSS
VSS
DQ51
DQ55
DQ56
DQ60
VDD
VDD
DQ57
DQ61
DQS7
DM7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VDD
VDD
SDA
SA0
SCL
SA1
VDD(SPD)
SA2
VDD(ID)
DU
PC2100 DDR SDRAM SO-DIMM (200P)
SMDDR_VREF
2.5VSUS
C992
AMP_DDR_SODIMM_H5.2
C993
AMP_DDR_SODIMM_H9.2
0.1U
CLOCK 0,1
0.1U
CLOCK 3,4
CKE 0,1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
C937
C938
C939
C940
C941
C942
C943
C944
C945
C946
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
2.5VSUS
MD5
MD4
SDM0
MD6
MD3
MD9
MD12
SDM1
MD14
MD15
C947
C948
C949
C950
C951
C952
C953
C954
C955
C956
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
C957
C958
C959
C960
C961
C962
C963
C964
C965
C966
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
2.5VSUS
2.5VSUS
MD20
MD21
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
SDM2
MD23
C967
C968
C969
C970
C971
C972
C973
C974
C975
C976
MD22
MD28
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
MD29
SDM3
2.5VSUS
C977
C978
C979
C980
C981
C982
C983
C984
C985
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
MD30
MD27
SMDDR_VTERM
2.5VSUS
C986
C987
C988
C989
C990
C991
0.1U
0.1U
0.1U
0.1U
150U/6.3V_7
150U/6.3V_7
CKE2
M_B_MA11
M_B_MA8
M_B_MA6
M_B_MA4
M_B_MA2
M_B_MA0
M_B_BA1
M_B_SRASA#
M_B_SCASA#
SM_CS3#
MD37
MD36
M_A_MA[0..13]
M_A_BA0
M_A_BA1
M_A_SRASA#
M_A_SCASA#
M_A_BMWEA#
SDM4
MD38
MD39
MD45
M_B_MA[0..13]
M_B_BA0
M_B_BA1
M_B_SRASA#
M_B_SCASA#
M_B_BMWEA#
MD44
SDM5
MD43
MD42
CLK_SDRAM4#
CLK_SDRAM4
CLK_SDRAM4# 5
CLK_SDRAM4 5
MD[0..63]
SM_DQS[0..7]
SDM[0..7]
MD49
MD52
MD55
MD61
CKE0
CKE1
CKE2
CKE3
MD57
SDM7
7
7
7
M_B_MA[0..13]
M_B_BA0 7
M_B_BA1 7
M_B_SRASA#
M_B_SCASA#
M_B_BMWEA#
7
7
7
MD[0..63] 7
SM_DQS[0..7]
SDM[0..7] 7
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SDM6
MD54
M_A_MA[0..13]
M_A_BA0 7
M_A_BA1 7
M_A_SRASA#
M_A_SCASA#
M_A_BMWEA#
MD62
MD63
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
5,7
5,7
5,7
5,7
CKE0
CKE1
CKE2
CKE3
5,7
5,7
5,7
5,7
+3V
PROJECT : CT3
SMbus address A1
CKE 2,3
Size
Document Number
Rev
1A
DDR1 DIMM
Date:
1

7
Sheet
of
13
8
39
+3V
CN21
21SS355
1
10
PCLK_MINI
INTD#
10
R402
10,17,23
10,17,23
AD31
AD29
10,17,23
10,17,23
AD27
AD25
10,17,23
10,17,23
C/BE3#
AD23
10,17,23
10,17,23
AD21
AD19
10,17,23
10,17,23
10,17,23
AD17
C/BE2#
IRDY#
33R
REQ1#
C581
18P
32
R149
1K
BC0EX1
10,17,23 CLKRUN#
10,17,23
SERR#
+3V
10,17,23
10,17,23
10,17,23
PERR#
C/BE1#
AD14
10,17,23
10,17,23
AD12
AD10
10,17,23
10,17,23
AD8
AD7
10,17,23
AD5
10,17,23
AD3
10,17,23
AD1
+5V
R145
*10K
10,20,22 SYNC1
10
SDINB
R148
33R SDIN1
10,20,22 BITCLK
C335
R146
*10K
SDIN1
*22P
GND
+5V
R147
125
10K
B
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
+3V
MINI PCI TYPE III SLOT

D
+5V
INTC#
10
PCIRST#
10,17,23,27
GNT1#
10
BC0EX2
AD30
32
10,17,23
AD28
AD26
AD24
10,17,23
10,17,23
10,17,23
AD22
AD20
PAR
AD18
AD16
10,17,23
10,17,23
10,17,23
10,17,23
10,17,23
FRAME#
TRDY#
STOP#
10,17,23
10,17,23
10,17,23
LANVCC
R140
R139
MINIPCI_PME#
1K
100R AD22
3VSUS
R609
10K
MINIPCI_PME#
AD22
D3
RING
LAN2
LAN4
LAN6
LAN8
LED_YP
LED_YN
NC2
+5V
-INTA
R(IRQ4)
+3VAUX
-RST
+3V
-GNT
GND
-PME
(V)
AD30
+3V
AD28
AD26
AD24
IDSEL
GND
AD22
AD20
PAR
AD18
AD16
GND
-FRAME
-TRDY
-STOP
+3V
-DEVSEL
GND
AD15
AD13
AD11
GND
AD9
-CBE0
+3V
AD6
AD4
AD2
AD0
(V)
SERIRQ
GND
M66EN
SDOUT
SDIN1
-RESET
-MPCICACK
AGND
+SPK
-SPK
AGND
NC4
+3VAUX
PCI_PME# 10,17,23
Q51
2N7002E
DEVSEL# 10,17,23
AD15
AD13
AD11
10,17,23
10,17,23
10,17,23
AD9
C/BE0#
10,17,23
10,17,23
AD6
AD4
AD2
AD0
10,17,23
10,17,23
10,17,23
10,17,23
SERIRQ
10,11,17,27
SDOUT1
10,20,22
+3V
R142
*10K
-CODEC_RST 10,20,22
R141
1K
R393 2
1 10K
LANVCC
GND
32
RF_LINK
11,27 RF_OFF#
TIP
LAN1
LAN3
LAN5
LAN7
LED_GP
LED_GN
NC1
-INTB
+3V
R(IRQ3)
GND
PCICLK
GND
-REQ
+3V
AD31
AD29
GND
AD27
AD25
(V)
-CBE3
AD23
GND
AD21
AD19
GND
AD17
-CBE2
-IRDY
+3V
-CLKRUN
-SERR
GND
-PERR
-CBE1
AD14
GND
AD12
AD10
GND
AD8
AD7
+3V
AD5
(V)
AD3
+5V
AD1
GND
SYNC
SDIN0
BITCLK
-AC_PRIMARY
BEEP
AGND
+MIC
-MIC
AGND
-RI
+5VA
126
R150
10K
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
MINIPCI_TYPE_III
LANVCC
+3V
+5V
+5V
+5V
C918
0.1U/0402
C582
0.1U/0402
C583
0.1U/0402
C584
0.1U/0402
C920
0.1U/0402
C921
0.1U/0402
C922
0.1U/0402
C923
0.1U/0402
C924
0.1U/0402
C925
0.1U/0402
C926
0.1U/0402
C919
0.1U/0402
C927
0.1U/0402
PROJECT : CT3

Size
Document Number
Custom
Date:
5
Rev
1A
MINIPCI_TYPE_III
Sheet
1
14
of
39
VADJ_R
BLON
+3V
VIN
D
C344
CN1
0.1U_0603_25V
27
LCDID2
LCDID1
LCDID0
0.1U/0402
10U/25V
Q17
+3V
L25
PBY201209T-4A
EDIDDATA_1
EDIDCLK_1
BLON
C348
0.1U/0402
LCDVCC
RF_LED# 25,32
DTA124EUA
SI stage:
Add a level-shift circuit for EDID interface.
Sting 10/04/2004
11
11
11
TXLOUT0+ 6
TXLOUT0- 6
6
Q54
1
EDIDCLK
R708 2.2K
TXLOUT2+ 6
TXLOUT2- 6
R709 2.2K
2N7002E
3
EDIDCLK_1
TXLOUT1+ 6
TXLOUT1- 6
TXLCLKOUT+ 6
TXLCLKOUT- 6
EDIDDATA
+3V
VADJ
VIN
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
31
32
33
34
1K
C343
C345
+5V
R425
VADJ_R
C346
0.1U/0402
Q55
2N7002E
EDIDDATA_1
LCD_CON30
3VPCU
R156
+3V
10K
Q18
SI3443DV
R3
33K
BKLON
R154
1K
BLON
R155
D4
10K
LID_EC#
27
6
1SS355
DISP_ON
+3V
2
1
D
D
D
D
5
6
LCDVCC
24mil
450mA
Q19
3
4
DTC144EUA
C349
C347
10U/10V/0805
0.1U
LID
SW6
1
2
FPBACK#
Q16
DTC144EUA
11
PROJECT : CT3

Size
Document Number
Custom
Date:
5
Rev
2A
LCD CONN
Sheet
1
15
of
39
CardBus Connector
C553
4.7U/10V
0.1U_0603_25V
C483
0.01U_0402
0.01U_0402
C482
0.1U_0603_25V 1000P
C557
4.7U/10V
CARDBUS POWER SWITCH
C465
C481
1
C559
C554
A_VCC
C501
10U/10V/0805
5VSUS
3VSUS
For PCI7411
TPS_CLOCK
0.1U_0603_25V
R373
A_VCC
VCCB
VCCB
D19
K19
VCCA
VCCA
A5
A11
B_CAD31/B_D10
B_CAD30/B_D9
B_CAD29/B_D1
B_CAD28/B_D8
B_CAD27/B_D0
B_CAD26/B_A0
B_CAD25/B_A1
B_CAD24/B_A2
B_CAD23/B_A3
B_CAD22/B_A4
B_CAD21/B_A5
B_CAD20/B_A6
B_CAD19/B_A25
B_CAD18/B_A7
B_CAD17/B_A24
B_CAD16/B_A17
B_CAD15/B_IOWR
B_CAD14/B_A9
B_CAD13/B_IORD
B_CAD12/B_A11
B_CAD11/B_OE
B_CAD10/B_CE2
B_CAD9/B_A10
B_CAD8/B_D15
B_CAD7/B_D7
B_CAD6/B_D13
B_CAD5/B_D6
B_CAD4/B_D12
B_CAD3/B_D5
B_CAD2/B_D11
B_CAD1/B_D4
B_CAD0/B_D3
B15
A16
B16
A17
C16
D17
C19
D18
E17
E19
G15
F18
H14
H15
G17
K17
L13
K18
L15
L17
L18
L19
M17
M14
M15
N19
N18
N15
M13
P18
P17
P19
A_CAD31/A_D10
A_CAD30/A_D9
A_CAD29/A_D1
A_CAD28/A_D8
A_CAD27/A_D0
A_CAD26/A_A0
A_CAD25/A_A1
A_CAD24/A_A2
A_CAD23/A_A3
A_CAD22/A_A4
A_CAD21/A_A5
A_CAD20/A_A6
A_CAD19/A_A25
A_CAD18/A_A7
A_CAD17/A_A24
A_CAD16/A_A17
A_CAD15/A_IOWR
A_CAD14/A_A9
A_CAD13/A_IORD
A_CAD12/A_A11
A_CAD11/A_OE
A_CAD10/A_CE2
A_CAD9/A_A10
A_CAD8/A_D15
A_CAD7/A_D7
A_CAD6/A_D13
A_CAD5/A_D6
A_CAD4/A_D12
A_CAD3/A_D5
A_CAD2/A_D11
A_CAD1/A_D4
A_CAD0/A_D3
D1
C1
D3
C2
B1
B4
A4
E6
B5
C6
B6
G9
C7
B7
A7
A10
E11
G11
C11
B11
C12
B12
A12
E12
C13
F12
A13
C14
E13
A14
B14
E14
A_D10
A_D9
A_D1
A_D8
A_D0
A_A0
A_A1
A_A2
A_A3
A_A4
A_A5
A_A6
A_A25
A_A7
A_A24
A_A17
A_IOWR#
A_A9
A_IORD#
A_A11
A_OE#
A_CE2#
A_A10
A_D15
A_D7
A_D13
A_D6
A_D12
A_D5
A_D11
A_D4
A_D3
B_CC/BE3/B_REG
B_CC/BE2/B_A12
B_CC/BE1/B_A8
B_CC/BE0/B_CE1
F15
G18
K14
M18
A_CC/BE3/A_REG
A_CC/BE2/A_A12
A_CC/BE1/A_A8
A_CC/BE0/A_CE1
C5
F9
B10
G12
A_REG#
A_A12
A_A8
A_CE1#
B_CPAR/B_A13
K13
A_CPAR/A_A13
G10
A_A13
B_CFRAME/B_A23
B_CTRDY/B_A22
B_CIRDY/B_A15
B_CSTOP/B_A20
B_CDEVSL/B_A21
B_CBLOCK/B_A19
G19
H17
J13
J17
H19
J19
A_CFRAME/A_A23
A_CTRDY/A_A22
A_CIRDY/A_A15
A_CSTOP/A_A20
A_CDEVSL/A_A21
A_CBLOCK/A_A19
C8
A8
B8
A9
C9
E10
B_CPERR/B_A14
B_CSERR/B_WAIT
J18
B18
A_CPERR/A_A14
A_CSERR/A_WAIT
F10
B3
A_A14
A_WAIT#
B_CREQ/B_INPACK
B_CGNT/B_WE
E18
J15
A_CREQ/A_INPACK
A_CGNT/A_WE
E7
B9
A_INPACK#
A_WE#
B_CSTSCHG/B_BVD1(STSCHG/RI)
B_CCLKRUN/B_WP(IOIS16)
B_CCLK/B_A16
F14
A18
H18
A_CSTSCHG/A_BVD1(STSCHG/RI)
A_CCLKRUN/A_WP(IOIS16)
A_CCLK/A_A16
B2
C3
E9
B_CINT/B_READY(IREQ)
B19
A_CINT/A_READY(IREQ)
C4
A_STSCHG_P
A_IOIS16#
A_A16
R262
A_IREQ#
B_CRST/B_RESET
F17
A_CRST/A_RESET
A6
A_RESET
B_CAUDIO/B_BVD2(SPKR)
C17
A_CAUDIO/A_BVD2(SPKR)
A2
A_SPKR_P
B_CCD1/B_CD1
B_CCD2/B_CD2
B_CVS1/B_VS1
B_CVS2/B_VS2
N13
B17
C18
F19
A_CCD1/A_CD1
A_CCD2/A_CD2
A_CVS1/A_VS1
A_CVS2/A_VS2
C15
E5
A3
E8
A_CD1#
A_CD2#
A_VS1#
A_VS2#
B_RSVD/B_D14
B_RSVD/B_D2
B_RSVD/B_A18
N17
A15
K15
A_RSVD/A_D14
A_RSVD/A_D2
A_RSVD/A_A18
B13
D2
C10
A_D14
A_D2
A_A18
PCI7411GHK
*43K
5VSUS
U5
A_A23
A_A22
A_A15
A_A20
A_A21
A_A19
5VSUS
CN6
33R
A_D3
A_D4
A_D11
A_D5
A_D12
A_D6
A_D13
A_D7
A_D15
A_A10
A_CE2#
A_OE#
A_A11
A_IORD#
A_A9
A_IOWR#
A_A17
A_A24
A_A7
A_A25
A_A6
A_A5
A_A4
A_A3
A_A2
A_A1
A_A0
A_D0
A_D8
A_D1
A_D9
A_D10
2
3
37
4
38
5
39
6
41
8
42
9
10
44
11
45
46
55
22
56
23
24
25
26
27
28
29
30
64
31
65
66
SKTAAD0/D3
SKTAAD1/D4
SKTAAD2/D11
SKTAD3/D5
SKTAD4/D12
SKTAD5/D6
SKTAAD6/D13
SKTAAD7/D7
SKTAAD8/D15
SKTAAD9/A10
SKTAAD10/CE2#
SKTABAD11/OE#
SKTAAD12/A11
SKTAAD13/IORD#
SKTAAD14/A9
SKTAAD15/IOWR#
SKTAAD16/A17
SKTAAD17/A24
SKTAAD18/A7
SKTAAD19/A25
SKTAAD20/A6
SKTAAD21/A5
SKTAAD22/A4
SKTAAD23/A3
SKTAAD24/A2
SKTAAD25/A1
SKTAAD26/A0
SKTAAD27/D0
SKTAAD28/D8
SKTAAD29/D1
SKTAAD30/D9
SKTAAD31/D10
A_CE1#
A_A8
A_A12
A_REG#
7
12
21
61
-SKTACBE0/CE1#
-SKTACBE1/A8
-SKTACBE2/A12
-SKTACBE3/REG#
A_A23
A_A15
A_A22
A_A21
A_A20
A_A13
A_A14
A_WAIT#
A_INPACK#
A_WE#
A_IREQ#
A_A19
A_IOIS16#
A_RESET
A_D14
A_A18
A_VS1#
A_VS2#
A_CD1#
A_CD2#
A_SPKR_P
A_STSCHG_P
A_D2
19
54
20
53
50
49
13
14
59
60
15
16
48
33
58
40
47
43
57
36
67
62
63
32
SKTAPCLK/A16
-SKTAFRAME/A23
-SKTAIRDY/A15
-SKTATRDY/A22
-SKTADEVSEL/A21
-SKTASTOP/A20
SKTAPAR/A13
-SKTAPERR/A14
0SKTASERR/WAIT#
-SKTAREQ/INPACK#
-SKTAGNT/WE#
-SKTAINT/RDY
-SKTALOCK/A19
-SKTACLKRUN/WP
-SKTARST/RESET
SKTARSVD/D14
-SKTRSVD/A18
-SKTAVS1/VS1#
-SKTAVS2VS2#
-SKTACD1/CD1#
-SKTACD2/CD2#
SKTAAUDIO/BVD2
-SKTASTSCHG/BVD1
SKTARSVD/D2
17
17
17
TPS_DATA
TPS_CLOCK
TPS_LATCH
TPS_DATA
TPS_CLOCK
TPS_LATCH
AVPP
A_VCC
17,27 PCICGRST#
SKTA/VCC1
SKTA/VCC2
17
51
1
2
3
4
5
6
7
8
9
10
11
12
5V_0
5V_2
5V_1
NC_3
DATA
NC_2
CLOCK
SHDN#
LATCH
12V_1
NC_0 BVPP/BVCORE
12V_0
BVCC1
AVPP/AVCORE BVCC0
AVCC0
NC_1
AVCC1
OC#
GND
3.3VIN0
RESET#
3.3VIN1
NC
U21-2
25
U21-3
A_VCC
24
23
22
21
20
19
18
17
16
15
14
13
3VSUS
TPS2224A/2220A (PWR)
For PCI1510
SKTA/VPP1
SKTA/VPP2
AVPP
18
52
C513
10U/10V/0805
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
1
34
35
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
GND
GND
87
88
C488
0.001U_0402
PV stage:
Remove unused PCI1510RVGF circuit.
Griffey 12/08/2004
CARDBUS SLOT
FOX=WZ21131-G2
PCI7411GHK
PROJECT : CT3

Size
Document Number
Custom
CardBus
Date:
5
Rev
1A
Connector
Sheet
1
16
of
39
CardBus
SI stage:
Remove reserve resistor R693~R695 for
PCI1510RVGF
Sting 09/24/2004
3VSUS
3VSUS
U21-1
10,14,23 AD[0..31]
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VCCP
VCCP
U2
V1
V2
U3
W2
V3
U4
V4
V5
U5
R6
P6
W6
V6
U6
R7
V9
U9
R9
N9
V10
U10
R10
N10
V11
U11
R11
W12
V12
U12
N11
W13
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
W4
W7
W9
W11
10,14,23
10,14,23
10,14,23
10,14,23
C/BE3#
C/BE2#
C/BE1#
C/BE0#
10,14,23
PAR
P9
10,14,23 FRAME#
10,14,23 TRDY#
10,14,23
IRDY#
10,14,23 STOP#
10,14,23 DEVSEL#
V7
R8
U7
W8
N8
W5
FRAME
TRDY
IRDY
STOP
DEVSEL
IDSEL
V8
U8
PERR
SERR
U1
T2
REQ
GNT
P5
R3
T1
PCLK
PRST
GRST
10,14,23
10,14,23
10
10
B
W3
W10
AD25
R284
PERR#
SERR#
REQ0#
GNT0#
PCLK_7411
2
PCLK_7411
10,14,23,27 PCIRST#
16,27 PCICGRST#
7411_PME#
100R
T3
3VSUS
U21-5
U27
SCL
M3
SCL
SDA
R303
10K
SDA
8
7
6
5
M2
PCI7411GHK
SUSPEND
R2
DATA
CLOCK
LATCH
N1
L6
N2
SPKROUT
L7
PCMSPK
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
N3
M5
P1
P2
P3
N5
R1
INTE#
10
INTF#
10
INTG#
10
SERIRQ 10,11,14,27
PLOCK# 10
CARD_LED 18,25
CLKRUN# 10,14,23
TPS_DATA
TPS_CLOCK
TPS_LATCH
CLK48M
M1
OUT
VDD
GND
OE
C530
C585
*0.01U_0402
*0.01U_0402
*FCM1608K221
C/BE3
C/BE2
C/BE1
C/BE0
PAR
SI stage:
Remove all componet of PLL circuit and Add
CLK48M input from CKG.
Sting 10/12/2204
3VSUS
C528
RI_OUT/PME
3VSUS
C529
0.001U_0402
0.01U_0402
PCI7411GHK
C498
C511
0.1U
0.1U
PV stage:
Remove R701 & R702 for unused PCI1510RVGF
circuit.
Griffey 12/10/2004
U21-4
*0R
L41
3VSUS
R336 2.7K
3VSUS
*FCM1608K221
*SG-8002CA 48M
3VSUS
PCIXX21 Power Terminals
Griffey 12/08/2004
+3V
L40
R302
2.7K
SDA
PV stage:
Remove reserve relatived circuit for PCI1510RVGF.
48MHz Clock
CLK48M 3
SCL
24LC08
When -VCCD0 and -VCCD1 asserted high,

PLOCK# and INTF# will provide a SDA
signaling for I2C bus, PLOCK# will provide a
SCL signaling for I2C bus.
20
R322
1
2
3
4
A0
A1
A3
GND
TPS_DATA 16
TPS_CLOCK 16
TPS_LATCH 16
Y7
CLK_48
VCC
NC
SCL
SDA
C461
3VSUS
C467
0.001U_0402
0.01U_0402
C519
C536
0.1U
0.1U
C635
0.1U
C636
0.1U
H8
H9
H10
H11
H12
J8
M7
J12
M9
M10
M12
K8
K12
N7
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
G7
G8
G13
H13
J9
J10
J11
K9
K10
K11
L8
L9
L10
L11
L12
M8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1.5V
1.5V
VR_EN
C438
C531
M19
H1
0.1U
0.1U
H2
R698
0R
PCI7411GHK
VR_EN# :0
Internal voltage regulator enable
for 1.5/2.5V core power.
R305
11
0R
RI#
U21-6
W17
3VSUS
NC
TEST0
T19
R606
10K
EMI
P12
PCLK_7411
VCO_LF
PV stage:
Pouplate R704 and C1045 for getting better
EMI performance.
Sting 11/19/2004
CLK48M
PCI7411GHK
R679
*22R
3VSUS
R704
22R
U21-10
10,14,23 PCI_PME#
7411_PME#
DTC144EUA
Q50
A_USB_EN
E2
R306
*10K
B_USB_EN
E1
R307
*10K
C1036
*22P
C1046
22P
PROJECT : CT3
PCI7411GHK
Size
Document Number
Custom
Date:
5
Rev
3A
CardBus
Sheet
1
17
of
39
U21-8
MC_PWR_CTRL_0
MC_PWR_CTRL_1
SD_CDZ
MS_CDZ
SM_CDZ
E3
F5
F6
SD_CD
MS_CD
SM_CD
G5
F3
H5
G3
G2
G1
MS_CLK/SD_CLK/SM_EL_WP
MS_BS/SD_CMD/SM_WE
MS_DATA3/SD_DAT3/SM_D3
MS_SDIO(DATA0)/SD_DAT0/SM_D0
D
SD_CLK/SM_RE/SC_GPIO1
SD_CMD/SM_ALE/SC_GPIO2
SD_DAT0/SM_D4/SC_GPIO6
SD_WP/SM_CE
CARD POWER CONTROL

U21-9
L5
SC_PWR_CTRL
SC_CD
MS_CLK_SD_CLK_SM_ELWPZ_R
R347
MS_BS_SD_CMD_SM_WEZ
MS_DATA3_SD_DAT3_SM_D3
J5
J3
H3
J6
J1
J2
H7
SM_REZ
SM_ALE
SM_D4
SM_D5
SM_D6
SM_D7
SD_WP_SM_CEZ
J7
K1
K2
SM_CLE
SM_RBZ
Reserve for smart card which is powered by 5V.
L2
33R MS_CLK_SD_CLK_SM_ELWPZ
3VSUS
SC_CLK
SC_RST
SC_VCC_5V
SI stage:
Remove reserve resistor R696 fro
PCI1510RVGF.
Sting 10/12/2004
SC_DATA
SC_OC
K5
K3
K7
R389
10K
R692
L1
L3
5VSUS
*10K
VCC_XD
PCI7411GHK
R716
22R
3VSUS
3VSUS
SM_CLE/SC_GPIO0
SM_R/B/SC_RFU
SM_PHYS_WP/SC_FCB
Q56
R316
MC_PWR_CTRL_0#
PCI7411GHK
8.2K
Q34
PV stage:
1. Disconnect SM_PHYS_WP.
2. Tie SM_EL_WP with SM_PHYS_WP of SM card to allow
for normal operation of SD and SM.
PV stage:
Add a discharge circuit for media
card power.
Sting 11/19/2004
2N7002E
MC_PWR_CTRL_0#
F1
F2
MC_PWR_CTRL_0#
PV stage:
Remove reserve relatived circuit for
PCI1510RVGF.
Griffey 12/08/2004
AO3403
Sting 11/19/2004
VCC_XD
3
5VSUS
Q43
VCC_XD
R408
SM_XD_WP1
XD_WP#
2
3
VCC
D19
SD_CDZ
OE
*1SS355
PV stage:
1. Add quick switch circuit.
SM_CDZ
R436
*100K
Griffey 12/10/2004
B
GND
CLOSE TO XD
SOCKET
1U
C1049
U47
3.3K
MS_CLK_SD_CLK_SM_ELWPZ
10U/10V/0805
100K
3VSUS
R718
43K
C552
*2N7002E
17,25 CARD_LED
R380
D20
SM_CDZ
NC7SZ384P5X
*1SS355
R737
*0R
SM_XD_WP
XD_WP#
VCC_XD
VCC_XD
CN7
R724
0R
MS_BS_SD_CMD_SM_WEZ
XD-SD-MS-D3
XD-SD-MS-D2
MS_BS_SD_CMD_SM_WEZ
XD-SD-MS-D1
XD-SD-MS-D0
XD-SD-MS-D2
MS_CDZ
XD-SD-MS-D3
R731
0R
SM_D4
SM_D5
R414
R415
0R
0R
SD-CLK
MS-CLK
XD-D4
XD-D5
3VSUS
5IN1_GND
SM-CD-COM
SM-CD-SW
NC
SD-WP-SW
SD-DAT1
SD-DAT0
SD-CLK
SD-VCC
SD-CMD
SD-DAT3
SD-DAT2
MS-BS
MS-DATA1
MS-DATA0
MS-DATA2
MS-INS
MS-DATA3
MS-CLK
MS-VCC
SM/XD-D4
SM/XD-D5
SM/XD-D6
SM/XD-D7
SM-LVD
#SM/XD-R/B
#SM/XD-RE
#SM/XD-CE
SM-VCC
#SM-CD
SM/XD-D3
SM/XD-D2
SM/XD-D1
SM-D0
SM/XD-WP-IN
#SM/XD-WE
#SM/XD-ALE
##SM/XD-CLE
XD-CD
XD-VCC
SD-CD-COM
SD-CD-SW
SM-WP-SW
5IN1_GND
5IN1_GND
5IN1_GND
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
XD-D6
XD-D7
R416
R417
0R
0R
SM_RBZ
SM_REZ
SD_WP_SM_CEZ
XD-SD-MS-D3
XD-SD-MS-D2
XD-SD-MS-D1
XD-SD-MS-D0
R753
SM_CDZ
0R MS_DATA3_SD_DAT3_SM_D3
XD_WP#
MS_BS_SD_CMD_SM_WEZ
SM_ALE
SM_CLE
SM_CDZ
43K
SD_WP_SM_CEZ
R413
R412
R410
R409
R411
VCC_XD
SM_D6
SM_D7
8.2K
SM_CDZ
3VSUS
R751
R752
0R
*0R
SD_WP_SM_CEZ
XD-SD-MS-D1
XD-SD-MS-D0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Q57
AO3403
3
SM_CDZ
XD_VCC
SD_CDZ
XD_WP#
C1050
1U
XD_VCC
R755
*0R
VCC_XD
TAITWUN-R007-020-N5-44P
PV stage:
1. Add pull-up circuit.
PV stage:
1. Add R717 to solve SM card can't write protect issue.
2. Add R718 to solve cross-talk issue of MS-PRO card.
3. Add R719~R736 as terminal on all multi-funtion pin.
5 IN1 CARD READER
Griffey 12/20/2004
Sting 11/19/2004
VCC_XD
MS_BS_SD_CMD_SM_WEZ
R742
10K
SM_REZ
R743
10K
SD_WP_SM_CEZ
R744
10K
SM_RBZ
R745
22K
PROJECT : CT3
Size
C
Document Number
Date:
Rev
3A
CARD READER CONN

Sheet
18
1
of
39
IEEE 1394a
IEEE 1394 CONNECTOR
L38
3VSUS
R13
R14
V17
V19
T18
R0
U18
TPBIAS0
FBM1608
1394_AVDD
C524
C478
C455
*270P
C486 C492
C437
R0
R259
56.2/F
0.01U_0402
0.1U
0.001U_0402
0.1U/0402
0.1U
C472
1U/16V
R263
56.2/F
R626
R625
0R
0R
R237
TPA0P
TPA0N
6.34K
R1
U19
U15
TPA0+
TPA0-
V15
W15
TPA0P
TPA0N
TPB0+
TPB0-
V14
W14
TPB0P
TPB0N
PHY_TEST_MA
R17
TPBIAS0
TPB0P
TPB0N
R276
56.2/F
R238
CML1
1
4
*MCM3216-S
L1394_TPA0+
2
L1394_TPA03
1
4
CML2
L1394_TPB0+
2
L1394_TPB03
*MCM3216-S
R269
56.2/F
R627
R628
0R
0R
R1
TPBIAS0
5
6
AVDD
AVDD
AVDD
AVDD
VDPLL
5
6
U21-7
CN19
4.7K
1394_CONN
PHY_TEST_MA
TPB0_DF
CNA
M11
CPS
R236
390K
P15
CNA
R607
390K
R280
5.11K/F
R19 1394_XOUT
2
22P
5VSUS
Y5
24.576MHZ
1
XI
PC0 (TEST1)
PC1 (TEST2)
PC2 (TEST3)
VSPLL
AGND
AGND
AGND
AGND
TPBIAS1
TPA1+
TPA1TPB1+
TPB1-
SI stage:
Change R682 and R683 value from 56R to 0R cause of
BOM error in A-test.
Sting 09/24/2004
Closed Phy IC
C430
XO
C506
270P
IN
OUT
ON# SET
0R
C573
C571
470P
22P
R12
U13
V13
C572
R365
6.8K
GND
100U/10V
AAT4610A
0.1U/0402
USB 1
TPBIAS1
R629
V18
W18
R682
C439
R18 1394_XIN
T17
N12
P14
U14
U16
U17
U33
5
CPS
1394_TPA1+
1394_TPA1-
CN22
1394_TPA1+ 31
1394_TPA1- 31
V16
W16
0R
11
11
1394_TPB1+ 31
1394_TPB1- 31
2
1
USBP0USBP0+
USBPWR0
USBP0-1
USBP0+1
3
4
L37
*CMM211T-900M-S
PCI7411GHK
R254
56.2/F
TPB1_DF
R239
56.2/F
C568
*Clamp-Diode
C442
1U/16V
R242
56.2/F
C570
*Clamp-Diode
5VSUS
C447
270P
U19
5
IN
OUT
R683
0R
1
R252
5.11K/F
C444
*270P
1394_TPA1+
1394_TPA1-
C407
0.1U/0402
ON# SET
C397
C408
470P
R205
6.8K
GND
100U/10V
2
Closed Phy IC
2
TPBIAS1
Suyin_020016MR004S100ZU
ESD
1
R246
56.2/F
0R
8
7
6
5
GND
GND
GND
GND
R630
1
2
3
4
AAT4610A
R631
0R
CN16
USBP1USBP1+
2
1
USBPWR1
USBP1-1
USBP1+1
3
4
L31
*CMM211T-900M-S
ESD
0R
GND
GND
GND
GND
8
7
6
5
Suyin_020016MR004S100ZU
USB 2
R632
1
2
3
4
11
11
C420
*Clamp-Diode
C415
*Clamp-Diode
PROJECT : CT3

Size
Document Number
Custom
Date:
5
Rev
2A
IEEE 1394A, USBX2

Sheet

1
19
of
39
The AMC20493-001 modem is used for mother board family MBAMC20493-010.

AMCVDD
RCOSC1
22
22
DIB_DATAN
DIB_DATAP
3
4
DIB_DATAN
DIB_DATAP
22
22
PWRCLKP
PWRCLKN
7
8
PWRCLKP
PWRCLKN
BITCLK
SDINA
AC_RESET#
SYNC
SDATA_OUT
BITCLK
MR18
33R
22
BITCLK
SDINA
MR19
33R
21
SDATA_IN0
20
B
21,22 97DOCK_OK
GPIO_4
GPIO_5
MR11
33R
CK26
24
XTLO
MR10
*1M
CK27
25
XTLI
MC29
33P
33P
MC30
23
33
44
AVDD
AVDD
45
27
LINEINL_PR
22
LINE_IN_R
28
LINEINR_PR
22
LINE_OUT_L
39
AMPL
LINE_OUT_R
40
AMPR
HP_OUT_L
42
PC_BEEP 22
AMPL
21,22
AMPR
21,22
LINEOUTL_PR 22
HP_OUT_R
43
MIC_IN
29
CD_IN_L
30
CDAUDL
SmartAMC
GND
MY1
24.576MHZ
1
2
PC_BEEP
PC_BEEP
LINE_IN_L
LINEOUTR_PR
MIC_1
MC12
CD_IN_R
32
CDAUDR
CD_IN_GND
31
CDGND
SPDIF
46
REF_FLT
VC_SCA
VREF_SCA
38
37
36
MBIAS/AVDD
34
SDATA_IN1
47
48
MC18
MC17
4.7U/10V
0.1U_0603_25V
13
MIC_BIAS
22
10U/10V/0805
SPDIF
MR17
*3K
MR16
0R
MIC1
MIC1
21,22
22,31
MIC_BIAS
AGND
AGND
10,14,22
PRIMARY_DN
17
16
15
AVSS_CLK
10,14,22 -CODEC_RST
10,14,22 SYNC1
10,14,22 SDOUT1
14
MC40
0.1U
AGND
35
41
31,32 MUTE_LED
33R
ID0#
ID1#
2
9
19
MR25
MC20
10U/10V/0805
MC46
0.1U
DSPKOUT
26
11
12
GNDC
GNDC
GNDC
RC_OSC 1
VDD_CLK
MU2
MC13
249K
10U_1206_10V
MC35
0.1U
MC47
1000P
MR22
18
10
0.1U_0603_25V
MC39
0.1U
VDD
MC38
0.1U
MC19
10U/10V/0805
VDDC
VDDC
MC34
10,22
800mA
AMCVDD
3VSUS
MC45
0.1U_0603_25V
MC44
1U/16V
MC41
MC43
0.1U_0603_25V
0.1U
CX20468-31
AGND
AGND
MR20
10K
MR21
SDINA
0R
AGND
FROM CD-ROM
CDAUDL
CDAUDL
C309
1U/16V
CDINL2
22
CDAUDR
CDAUDR
C307
1U/16V
CDINR2
CDGND
CDGND
C308
1U/16V
CDGND1
PC SPEAKER
22
+3V
22
R293
10K
R291
20K
C543
CDINL2
28
CDINR2
28
CDGND1
28
R292
20K
0.1U_0603_25V
AGND
AGND
AGND
17
PCMSPK
11
SPK
PCBEEP1
PCBEEP2
R429
PC_BEEP
1K
MIC_BIAS
C547 0.47U
MIC_BIAS 21
U25
TC7SH86FU
R401
10K
C610
R430
1000P
2.2K
AGND
PROJECT : CT3

Size
Document Number
Rev
1A
AMC97 CODEC
Date:
1

7
Sheet
20
8
of
39
AUDIO AMPLIFIER
L17
BK2125HS220
1
2
2 0.47U
C319 1
2 0.47U
10
6
5
C321 2
1 4.7UF/6.3V
11
RLIN-1
RLIN-2
AGND
R319
R320
R338
R339
2
3
AGND
R418
15K
AGND
0R
R419
0R
R420
0R
R421
0R
0.1U
AGND
L_SPK+
AGND
DOCK_OK
15
17
L18
BK1608HS241-T
R360
22
1
24
13
12
25
26
27
28
29
30
31
32
33
10K
L_SPK-
AMCVDD
C332
VOLMUTE# 27
C331
180P
180P
D15
RB500V-40
AGND
AGND
TPA0312
PWP24
0312 Gain Table
AGND
GAIN0
0
0
1
1
X
GAIN1
0
1
0
1
X
+5V
SE/BTL
0
0
0
0
1
AMCVDD
U24
GMT_G910T21U
AV(inv)
6 dB
10 dB
15.6 dB
21.6 dB
4.1 dB
Vin
C311
800mA (30MIL)
Vout
C534
C312
C313
0.47U
AGND
T10U/10V
AGND
0.01U/50V
AGND
0.1U_0603_25V
AGND
0R
R375
C535
R374
GAIN0
GAIN1
180P
R335
15K
*1K
1K
10K
*10K
GND4
GND3
GND2
GND1
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
180P
+5VAMP
SHUTDOWN
BYPASS
C334
53398-0410
0.047U
C318
LIN+
LHPIN
LLINEIN
C330
14
C333
L19
BK1608HS241-T
0.47U
L_SPK+
L_SPK-
LIN-1 C317
1K
SE/BTL
HP/LINE
4
9
AMPL
R334
PC-BEEP
R_SPK+
R_SPK-
GND
0.47U
LOUT+
LOUT-
RLINEIN
RHPIN
RIN+
21
16
C328
ROUT+
ROUT-
PVDD1
PVDD2
23
20
8
4
3
2
1
R_SPK+
1K RIN-1
RRIN-2
RRIN-1
C320 1
CN23
L21
BK1608HS241-T
AGND
VDD
7
18
L20
BK1608HS241-T
R_SPK-
R361
AGND
SPEAKER OUT
C327
22U_1206_16V
AMPR
19
0.047U
C329
C322
4.7U/10V
U7
0.1U_0603_25V
AGND
20,22
C324
20,22
C551
R143
15K
10U_1206_16V
C316
+
C325
0.01U/50V
0.1U_0603_25V
AGND
+5VAMP
+5V
+5VAMP
4.7U/10V
AGND
2ND HEADPHONE OUT

LSPK+
R384
*30R-0805
LSPK+_2
RSPK+
R385
*30R-0805
RSPK+_2
C576
C577
*180P
*180P
1
2
6
3
4
5
9
7
8
PAVILION
10
CN24
*PHONEJACK-BLACK
MICROPHONE
FCM1608K221
L24
AGND
20,22
31
+5VAMP
AMCVDD
MIC1
MIC_PR
R399
C340
20,22 97DOCK_OK
DOCK_OK
2K
R152
220K
10
PAVILION
CH501H-40
R151
*4.7K
R398
4.7K
2
1
C339
CN26
PHONEJACK-BLACK
AGND
AGND
PRESARIO
20
AGND
R435
MIC_BIAS
R151
3K
C634
2
D18
Q42
DTA124EUA
7
8
31 JACK_DETECT#
220P_50V
R400
R397
220K
1
2
6
3
4
5
1K
R398
4.7UF/6.3V
AGND
1U/16V
AGND
HEADPHONE OUT
R_SPK+ C338
31
D_LSPK+
L_SPK+ C337
100U/6.3V
LSPK+
R386
30R-0805
LSPK+_1
31
D
100U/6.3V
RSPK+
R387
30R-0805
RSPK+_1
D_RSPK+
R396
R395
C341
C342
1K
1K
180P
180P
1
2
6
3
4
5
PAVILION
PRESARIO
7
8
10
CN25
PHONEJACK-BLACK
PROJECT : CT3

Size
Document Number
Date:
AGND
1
Rev
1A
AUDIO AMP_ TI-TPA0312

5
Sheet
21
8
of
39
3VDAA
MC14
0.1U_0603_25V
ML1
RING_1
DGND_LSD
24
FBM2125-0805
MR8
1M-1206
DVdd
8
25
NC1
TAC1
21
RAC1
20
TAC1
RAC1/RING
MC4
RING_2
0.033uF/200V-1206
MD4
2004S
TAC1/TIP
MR9
NC2
MC5
RAC2
PADDLE
TAC2
19
MJ1
GND
18
MD3
2004S
MU1
12
TRDC
MR3
MC8
EIC
11
EIC
RXI
MR5
RBias
MR7
59K
MC26
MDC
3800-2P-R-MODEN
MC2
*0.47UF-1812
FBM2125-0805
MC3
0.1U_0603_25V
0.01U/100V
AGND_LSD
BRIDGE_CC
CX20493-28P-MODEN
*CMSZ5240B
*470P/CC1808
<POWER/VOLTAGE>
CC1808-MODEN
ML2
6.8M
MC24
<PIC SPEC NO>
1
2
MD2
MRV1
P31B
AGND_LSD
TRDC
*CMSZ5240B
*470P/CC1808
<POWER/VOLTAGE>
CC1808-MODEN
1M-1206
NC3
MD1
MC9
0.033uF/200V-1206
*100P
29
RAC1
MC1
22
MR1
*7.5K-1210
15nF
AGND_LSD
RXI
BR904_CC
237K
SI stage:
Change this part type from Y5V to X7R
to improve signal quality.
Sting 10/06/2004
MC7
0.047uF/200V-1206
MC33 must be placed

near pin 26 (CLK).
BR904_AC1
PCLKN
PCLK2
MR15
MC37
47P
PCLKP 1
4
PCLK
MID82146
MR14
835-00252-MODEN
MR12
*10K
0R
MC36
*10P
MC22
GPIO1
RBias
1
5
PWR+
3VDAA
AGND_LSD
2
MC23
CLK
AVdd
MC32
MC11
MC31
*0.001uF
2.2U/25V
0.1U_0603_25V
6 AGnd
*0.01uF
0.1U_0603_25V
0R
MC32, MC11 and MC31

must be placed near
pins 2 (AVdd) and 6
(AGnd).
MD6
MC42
150P
BAV99
VZ
10
VZ
MC11 must
have max.
ESR of
2-ohms
AGND_LSD
EIO
17
EIO
DIB_DATAP
MC15
DIB_P
10P
27
TXO
DIB_N
10P
28
DIB_N
Vc
C922 and C924 must be Y3 type Capacitors for

Nordic Countries only
VRef
MC16
C944, C974 and C976

must be placed near
pins 3 (Vc) and 4
(VRef).
SI stage:
Connect H1/H3 to AGND via a O ohm
resistor by Conexant's comment.
14
TXO
13
TXF
DC_GND
DGnd
HOLE3
H-TS315BC295D110P2
DGND_LSD
MC28
MC27
*0.001uF
0.1U_0603_25V1U/10V/X7R
MC10
MC25
AGND_LSD
AGND_LSD
AGND_LSD
Layout trace short.
0.001U
AGND_LSD
MCN1
20,21
AMPL
20,21
AMPR
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
20 LINEOUTL_PR
H2
*HOLE1
H-C157D118P2
20 LINEOUTR_PR
AMCVDD
20
R715
PC_BEEP
10,14,20 BITCLK
0R
10,20
SDINA
10,14,20 -CODEC_RST
10,14,20 SYNC1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
3-179369-30P-LUV
MDC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
LINEINL_PR
20
LINEINR_PR
20
MIC1
CDAUDL
CDGND
CDAUDR
3VSUS
SPDIF
20,21
20
20
20
20,31
97DOCK_OK 20,21
SDOUT1 10,14,20
31
32
33
34
35
36
37
38
39
40
AGND
MR6
110R
15
H1
*HOLE1
H-C236D118P2
0R
MR2
27R-0805
C940 must have max. ESR of 2-ohms
Sting 10/13/2004
R714
MQ2
CMPTA44
MQ1
CZTA44
23
Vref_LSD
Circuit traces for C922 and C924 should be less

than 2 inches.
EIF
DIB_DATAN
DIB_DATAN
16
DIB_P
TXF
20
MQ3
CMPTA44
Q4B
EIF
DIB_DATAP
MC6
0.047uF/200V-1206
GND
20
MR4
348K
31
32
33
34
35
36
37
38
GND
MDC_MGND
POWER
FBM2125-0805
0R
PWR+
Vc_LSD
MR23
2 MT1
CLK 26
10P
PWRCLKP
0R
MC22 & MC23 must be

placed near pins 7
(PWR+) and 6
(AGnd).
20
MR24
PWRCLKN
CLK2
MC33
15K
ML3
GND
20
MR13
MD5
BAV99
MC21
150P
AGND
PROJECT : CT3
*MDC1

Size
Document Number
Custom
AGND
AGND
A
Rev
2A
MODEM DAA
Date:

E
Sheet
22
of
39
8100CL(10/100M)
8110SB(1G)
DVDD33
3.3VD
26,41,56,71,84,94,107
3.3VD
26,41,56,71,84,94,107
AVDDL
3.3VA
3,7,20
2.5VA
3,7,20,16
DVDD
2.5VD
32,54,78,99
1.8VD
32,54,78,99,24,45,64,110,116,126
AVDD25
2.5VA
12
NC
AVDDH
NC
3.3VA
10,120
4.7K
1
10K
Q40
SI3443DV
XTAL2
Y1
25.0000MHz
R248
C296
5.6K
27P
GND
TX1P
TX1N
12/11 FROM FAE for

8110SB
R275
L36
PBY201209T-4A
24
24
TX2P
TX2N
24
24
TX3P
TX3N
C459
0.1U/0402
C504
0.1U/0402
C493
0.1U/0402
C473
0.1U/0402
10
1
Q29
10,14,17
2 CTRL25
C523
0.1U/0402
R282
C525
C540
C457
C456
0.1U/0402
0.1U/0402
0.1U/0402
0.1U/0402
DVDD
MDI0+
MDI0AVDDL
VSS
MDI1+
MDI1AVDDL
CTRL25
VSS
AVDDH
HSDAC+
HSDACVSS
MDI2+
MDI2AVDDL
VSS
MDI3+
MDI3AVDDL
VSSPST
GND
ISOLATEB
VDD18
INTAB
VDD33
RSTB
CLK
GNTB
REQB
PMEB
VDD18
AD31
AD30
GND
AD29
AD28
VSSPST
AD2
VSSPST
GND
VDD18
AD3
AD4
AD5
AD6
VDD33
AD7
CBE0B
VSSPST
AD8
AD9
M66EN
AD10
AD11
AD12
VDD33
AD13
AD14
VSSPST
GND
AD15
VDD18
CBE1B
PAR
SERRB
SMBDATA
GND
SMBCLK
VDD33
PERRB
STOPB
DEVSELB
TRDYB
VSSPST
CLKRUNB
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
AD2
GND
GND
DVDD
AD3
AD4
AD5
AD6
LANVCC
AD7
C/BE0#
GND
AD8
AD9
M66EN
AD10
AD11
AD12
LANVCC
AD13
AD14
GND
GND
AD15
DVDD
C/BE1#
PAR
SERR#
C/BE0#
R125
10,14,17
*15K
C/BE1#
PAR
SERR#
10,14,17
10,14,17
10,14,17
PERR#
STOP#
DEVSEL#
TRDY#
10,14,17
10,14,17
10,14,17
10,14,17
CLKRUN#
10,14,17
T123
T118
LANVCC
PERR#
STOP#
DEVSEL#
TRDY#
GND
R131
0R
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
C449
0.1U/0402
AD[0..31]
AVDDL
GND
GND
ISOLATEB
DVDD
INTC#
LANVCC
PCIRST#
PCLK_LAN
GNT2#
REQ2#
LAN_PME#
DVDD
AD31
AD30
GND
AD29
AD28
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
AD27
AD26
LANVCC
AD25
AD24
C/BE3#
DVDD
AD16_LAN
AD23
GND
AD22
AD21
GND
GND
AD20
DVDD
AD19
LANVCC
AD18
AD17
AD16
C/BE2#
FRAME#
GND
IRDY#
DVDD
C539
10U/10V/0805
3
C515
C532
*0.1U/0402
C542
*0.1U/0402
*0.1U/0402
C497
*0.1U/0402
C458
*2SB1188
*0.1U/0402
1K
INTA#
Q33
2SB1197K
CTRL18 1
R279
15K
10,14,17,27 PCIRST#
2
PCLK_LAN
10
GNT2#
10
REQ2#
LANVCC
LANVCC
+3V
AVDDL
TX0P
TX0N
AVDDL
GND
TX1P
TX1N
AVDDL
CTRL25
GND
AVDDH
*0R
V_12P
GND
AVDDL
GND
*2SB1188
*0R
GND
AD27
AD26
VDD33
AD25
AD24
CBE3B
VDD18
IDSEL
AD23
GND
AD22
AD21
VSSPST
GND
AD20
VDD18
AD19
VDD33
AD18
AD17
AD16
CBE2B
FRAMEB
GND
IRDYB
VDD18
C541
C310
C306
TX0P
TX0N
24
24
0.1U/0402
0.1U/0402
C303
0.1U/0402
C537
0.1U/0402
C514
0.1U/0402
C300
0.1U/0402
C575
0.1U/0402
C579
10U/10V/0805
10U/10V/0805
C448
C480
*0.1U/0402
*0.1U/0402
24
24
Q30
CTRL25 1
R295
AD[0..31]
VSS
RSET
VDD18
CTRL18
LG2
HG
XTAL2
XTAL1
AVDDH
VSSPST
GND
LED0
VDD18
LED1
LED2
LED3
GND
EESK
VDD18
EEDI
EEDO
VDD33
EECS
LWAKE
AD0
AD1
U4
R249
*0R
VCC
NC
NC
GND
27P
LANVCC
AVDDH
CS
SK
DI
DO
8
7
6
5
AD0
AD1
C297
12/5 FROM FAE

for B TEST
For
8110SB
1
2
3
4
93C46-3GR
XTAL1
LANVCC
GND
EESK
DVDD
EEDI/AUX
EEDO
LANVCC
EECS
DTC144EUA
LANVCC
U22
LANVCC
5
6
D
D
3VPCU
DVDD
Q41
D
D
LAN_LINK#
24 LAN_SPEED_LED#
3VAUXON
27
2
1
24
0.1U_0603_25V C1047
R265
2
EECS
EESK
EEDI/AUX
EEDO
RTL8110S(B)/8100C
R394
GND
RSET
DVDD
CTRL18
GND
GND
XTAL2
XTAL1
AVDDH
GND
GND
SI stage:
Add a 0.1uF to make Q40 turn on slowly, because 3VPCU will drop
when LANVCC turned on quickly. it will make EC state machine
crazy.
Sting 10/15/2004
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
12/5 FROM FAE

AVDDH
R273
10,14,17 C/BE3#
10,14,17 AD16
R381
R707
IRDY#
FRAME#
C/BE2#
33R
PCLK_LAN
*0R
10,14,17
10,14,17
10,14,17
0R
AD[0..31]
R286
*22R
For
8100CL
C521
*22P
LANVCC
SI stage:
Add R707 for ID selection of Lan
controller.
Sting 10/04/2004
1
R672
10K
LAN_PME#
C477
*0.1U/0402
V_12P
PCI_PME#
10,14,17
PROJECT : CT3
Q53
2N7002E

Size
C
Document Number
Date:
Rev
2A
RTL8100CL / RTL8110SB
Sheet
23
of
39
SI stage:
Modfied transformer circuit for 10/100M
Sting 09/24/2004
application.
FOR 8110SBL
C202
*0.01U/0402
CC0402
C210
*0.01U/0402
CC0402
U18
1
23
TX3P
23
TX3N
23
TX2P
TX3P
TX3N
23
TX2N
23
TX1P
TX2P
TX2N
CT2
23
TX1N
TX1P
TX1N
TCT1
MCT1
TD1+
MX1+
TD1-
MX1-
TCT2
MCT2
TD2+
MX2+
TD2-
MX2-
TCT3
MCT3
TD3+
MX3+
TD3-
MX3-
R84
24
23
X-TX3P
22
X-TX3N
R90
21
20
X-TX2P
19
X-TX2N
18
LANCT2 R92
17
X-TX1P
16
X-TX1N
15
LANCT1 R95
14
X-TX0P
13
X-TX0N
*75/F
X-TX3P
31
X-TX3N
31
*75/F
U17
X-TX2P
31
X-TX2N
31
X-TX1P
31
X-TX1N
31
CT1
TX0P
TX0N
6
7
8
TX1P
TX1N
CT2
1
2
3
CT
TD+
TD-
CT
TX+
TX-
RD+
RDCT
RX+
RXCT
11
10
9
LANCT1
X-TX0P
X-TX0N
16
15
14
X-TX1P
X-TX1N
LANCT2
75/F
ATPL-119
CT1
23
TX0P
23
TX0N
10
TX0P
11
TX0N
12
TCT4
MCT4
TD4+
MX4+
TD4-
MX4-
75/F
10/100M
X-TX0P
31
X-TX0N
31
LAN_1
C232
*0.01U/0402
CC0402
C223
0.1U/0402
CC0402
*IH-009
C239
1500P/2KV
CC1808
8100CL NO STUFF
1G
8100CL: 0.1U
8110SBL: 0.01U
CN3
R82
LANVCC
23 LAN_SPEED_LED#
Close to Chip
C446
0.1U/0402
330R
C454
0.1U/0402
8100CL: 0.1U
8110SBL:
0.01U
R243
49.9/F
R247
49.9/F
R253
49.9/F
R257
49.9/F
A1
A2
X-TX3N
X-TX3P
X-TX1N
X-TX2N
X-TX2P
X-TX1P
TX1N
X-TX0N
TX1P
X-TX0P
10
LED1_YELP_Y
LED1_YELN_Y
RX2RX2+
RX1TX2-
TX2+
RX1+
TX1TX1+
TX0N
TX0P
LANVCC
R106
23
330R
B1
11
LAN_LINK#
B2
12
2
1
TX3N
RING_RJ11
13
TIP_RJ11
14
TX2N
MDC
3800-2P-R-MODEN
TX2P
C393
470P/CC1808
C474
*0.01U_0402
R271
*49.9/F
R264
*49.9/F
GND
LED2_GRNN_G
GND
15
16
CN4
TX3P
R267
*49.9/F
LED2_GRNP_G
C394
470P/CC1808
R261
*49.9/F
RING
TIP
LAN_CONN
10
BASE :OFF
100 BASE : YELLOW
1000 BASE : GREEN
LED1
APECIFICATION
A1(+)
A2(-)
YELLOW
LED2
APECIFICATION
B1(+)
B2(-)
GREEN
C463
*0.01U_0402
PROJECT : CT3
Size
C
Document Number
Date:
Rev
2A
LAN, RJ11, RJ45

Sheet
1
24
of
39
5VPCU
5VPCU
R2
*150R
LED3
PWR_LED_1 1
*LED HSMB-C112 BLUE
PAVILION
LED11
PWR_LED_1
*LED HSMB-C172 BLUE

LED17-21VGC-TR8
Q1
27,32 PWR_LED
LED HSMD-C170 ORANGE
POWER
1
150R
PAVILION
R370
DTC144EUA
LED HSMB-C172 BLUE
LED13
*LED HSMB-C112 BLUE

R368
150R
LED8
27
MBATLED0
1
2
PAVILION
HSMD-C110 ORANGE
DTC144EUA
LED12
PRESARIO
2
HSMD-C110 ORANGE
Q37
LED15
PRESARIO
PRESARIO
HSMD-C110 ORANGE
27,32
MX7
SW3
MY3
Q32
17,18 CARD_LED
1
3
5
27,32
1
3
5
Q13
2
4
SW4
2
4
R118
150R
DTC144EUA
PAVILION
LED9
PAVILION
*STS-055B
PRESARIO
2
1
3
5
SW7
*LED HSMB-C172 BLUE
TP_R#
TP_LED
LED HSMD-C112 BLUE
PAVILION
LED4
27
TP_R#
*LED HSMB-C172 BLUE
STS-055B
32
DTC144EUA
2
4
R278
150R
LED1
Touchpad control
PRESARIO
STS-055B
R369
150R
LED5
15,32
RF_LED#
PRESARIO
LED HSMB-C112 BLUE
HSMD-C110 ORANGE
LED14
PRESARIO
+3V
32
TP_L#
1
3
5
SW5
TP_L#
2
4
PAVILION
R367
150R
LED7
*STS-055B
28
HDDLED#
Q36
DTC144EUA
PAVILION
*LED HSMB-C112 BLUE
2
4
1
3
5
SW8
PRESARIO
R71
150R
LED10
STS-055B
Q10
CAPSLED
DTC144EUA
PROJECT : CT3
27
Size
Custom
Document Number
Date:
Rev
1A
LED, SW
Sheet
1
25
of
39
8Mbit (1M Byte), TSSOP40

D
D[0..7]
U32
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
ENV0
ENV1
BADDR0
BADDR1
TRIS
SHBM
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
27
27
27
CS#
RD#
WR#
ENV0
ENV1
BADDR0
BADDR1
TRIS
SHBM
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
CS#
RD#
WR#
21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
22
24
9
D0
D1
D2
D3
D4
D5
D6
D7
25
26
27
28
32
33
34
35
RESET#/NC
RY/BY#/NC
NC1
NC2
NC3
10
12
29
38
11
VCC
VCC
31
30
27
D0
D1
D2
D3
D4
D5
D6
D7
R388
*100K
1.AMD-29LV081B require MAX 500nS Tready for it's hardware

reset.And MAX6326_UR29 has >100mS reset timing.So we can tie
it's reset# pin to +3VALW directly.
2.SIO has internal 20 mS delay of VCC1_PWROK
3VPCU
C578
*0.1U/0402
3VPCU
AMD :Pin 10 is RESET# ; Pin12 is RY/BY#

SST :Pin10,12 are NC
C560
0.1U/0402
23
39
GND
GND
CE#
OE#
WE#
*ST Micro M29W008AB/AMD-29LV081B/SST39VF080
SI stage:
Add PLCC32 cause of it is convenient for Bios
Sting 10/01/2004
debugging.
4Mbit (512k Byte), TSSOP32
JPBIOS1
ENV0
ENV1
BADDR0
BADDR1
TRIS
SHBM
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
CS#
RD#
WR#
A18
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
22
24
31
1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
CE#
OE#
WE#
VPP
U31
D0
D1
D2
D3
D4
D5
D6
D7
VCC
GND
13
14
15
17
18
19
20
21
32
D0
D1
D2
D3
D4
D5
D6
D7
3VPCU
16
*PLCC-32P
ENV0
ENV1
BADDR0
BADDR1
TRIS
SHBM
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
20
19
18
17
16
15
14
13
3
2
31
1
12
4
5
11
10
6
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
CS#
RD#
WR#
30
32
7
CE#
OE#
WE#
D0
D1
D2
D3
D4
D5
D6
D7
21
22
23
25
26
27
28
29
D0
D1
D2
D3
D4
D5
D6
D7
A18
A18
VCC
GND
24
3VPCU
39VF040
PROJECT : CT3
Size
B
Document Number
Date:
Rev
2A
BIOS ROM
Sheet
1
26
of
39
3VPCU
3VPCU
3VPCU
C563
10,11,14,17
SERIRQ
10 LFRAME#/FWH4
10
LAD0/FWH0
10
LAD1/FWH1
10
LAD2/FWH2
10
LAD3/FWH3
2
PCLK_591
PCLK_591
R680
22R
11
2
D13
KBSMI#
C1037
22P
11
SCI#
10
10
GATEA20
RCIN#
32
32
32
32
32
32
32
25,32
MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7
32
32
32
25,32
32
32
32
32
32
32
32
32
32
32
32
32
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
R288
3VPCU
SERIRQ
DRQ0#
LFRAME#/FWH4
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
PCLK_591
591RESET#
KBSMI#591
1
1SS355
SWI#2
T67
SCI#
31
MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7
71
72
73
74
77
78
79
80
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68
TINT-
105
106
107
108
109
T64
T65
T66
T68
R352
32
32
25
32
SERIRQ
LDRQ
LFRAME
LAD0
LAD1
LAD2
LAD3
LCLK
LREST
SMI
PWUREQ
PSCLK1
PSDAT1
KB_CLK
KB_DAT
TPCLK
TPDATA
TPCLK
TPDATA
CAPSLED
NUMLED
20M
NUMLED
110
111
114
115
116
117
118
119
591_32KX1
158
591_32KX2
160
TINT
TCK
TDO
TDI
TMS
R353
IOPB0/URXD
IOPB1/UTXD
IOPB2/USCLK
IOPB3/SCL1
IOPB4/SDA1
IOPB7/RING/PFAIL
PORT-B
Key matrix scan
PORT-C
PORT-D-1
PORT-E
JTAG debug port
PSCLK1/IOPF0
PSDAT1/IOPF1
PSCLK2/IOPF2
PSDAT2/IOPF3
PSCLK3/IOPF4
PSDAT3/IOPF5
PSCLK4/IOPF6
PSDAT4/IOPF7
IOPC0
IOPC1/SCL2
IOPC2/SDA2
IOPC3/TA1
IOPC4/TB1/EXWINT22
IOPC5/TA2
IOPC6/TB2/EXWINT23
IOPC7/CLKOUT
IOPD0/RI1/EXWINT20
IOPD1/RI2/EXWINT21
IOPD2/EXWINT24
IOPE4/SWIN
IOPE5/EXWINT40
IOPE6/LPCPD/EXWIN45
IOPE7/CLKRUN/EXWINT46
PORT-H
PS2 interface
IOPH0/A0/ENV0
IOPH1/A1/ENV1
IOPH2/A2/BADDR0
IOPH3/A3/BADDR1
IOPH4/A4/TRIS
IOPH5/A5/SHBM
IOPH6/A6
IOPH7/A7
IOPI0/D0
IOPI1/D1
IOPI2/D2
IOPI3/D3
IOPI4/D4
IOPI5/D5
IOPI6/D6
IOPI7/D7
PORT-I
32KX1/32KCLKOUT
32KX2
PORT-J-1
Y8
591_32KX3
IOPA0/PWM0
IOPA1/PWM1
IOPA2/PWM2
IOPA3/PWM3
IOPA4/PWM4
IOPA5/PWM5
IOPA6/PWM6
IOPA7/PWM7
PWM or
PORT-A
KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15
120K
IOPJ0/RD
IOPJ1/WR0
SELIO
32.768KHZ
S5_ON
SUSON
MAINON
SWI#
VRON
11
11
BATLOW#
PWROK
26
CS#
DNBSWON#591
BATLOW#
PWROK
CS#
148
149
155
156
3
4
27
28
IOPM0/D8
IOPM1/D9
IOPM2/D10
IOPM3/D11
IOPM4/D12
IOPM5/D13
IOPM6/D14
IOPM7/D15
173
174
47
32
R294
R301
5VTP
4.7K
4.7K
PORT-K
PORT-M
PORT-L
SEL0
SEL1
CLK
17
35
46
122
159
167
137
TPCLK
TPDATA
RN62
1
3
5
7
2
4
6
8
IOPD4
IOPD5
IOPD6
IOPD7
PORT-D-2
PORTJ-2
GND1
GND2
GND3
GND4
GND5
GND6
GND7
T115
IOPJ2/BST0
IOPJ3/BST1
IOPJ4/BST2
IOPJ5/PFS
IOPJ6/PLI
IOPJ7/BRKL_RSTO
IOPK0/A8
IOPK1/A9
IOPK2/A10
IOPK3/A11
IOPK4/A12
IOPK5/A13/BE0
IOPK6/A14/BE1
IOPK7/A15/CBRD
IOPL0/A16
IOPL1/A17
IOPL2/A18
IOPL3/A19
IOPL4/WR1
81
82
83
84
87
88
89
90
93
94
TEMP_MBAT
MBATV
10K
R337
BADDR0
*10K
R340
BADDR1
*10K
R348
MUSIC#
10K
R290
SHBM
10K
R350
KBSMI#
R681
10K
I/O Address
Data
BADDR1-0
Index
0 0
2E
2F
4F
0 1
4E
(HCFGBAH, HCFGBAL)
1 0
(HCFGBAH, HCFGBAL)+1
Reserved
1 1
AD_AIR
SYS_I
T116
T117
CC-SET
34
VADJ
15
32
33
36
37
38
39
40
43
PR_INSERT# 31
CELL-SET 34
VFAN_1
30
3VAUXON 23
CIR_OUT 31
DOCK5VON 31
PCICGRST# 16,17
IR_CLKO
R351
10K
EC_BT_OFF#
26
29
30
MUSIC#
IR_CLKO
DVD#
2
44
24
25
NBSWON#
ACIN
SUSB#
FANSIG
EC_RF_OFF#
R740
R741
T129
T130
MBATLED0
PWR_LED
MBCLK
MBDATA
PCIRST#
0*
0*
152
U30
8
7
6
5
MBCLK
MBDATA
VCC
NC
SCL
SDA
A0
A1
A3
GND
1
2
3
4
*24LC08
25
25,32
3,34
3,34
10,14,17,23
BT_OFF# 11,32
IRCLK
29
IRDATA
29
RSMRST# 11
FANSIG
30
RF_OFF# 11,14
CIR_IN
29,31
THRM_EC 3
MUSIC#
32
DVD#
32
ACIN
SUSB#
LID_EC#
34
11
15
ENV0
ENV1
BADDR0
BADDR1
TRIS
SHBM
A6
A7
26
26
26
26
26
26
26
26
D0
D1
D2
D3
D4
D5
D6
D7
26
26
26
26
26
26
26
26
RD#
WR#
26
26
TP_LED
25
D/C#
BL/C#
34
34
A8
A9
A10
A11
A12
A13
A14
A15
26
26
26
26
26
26
26
26
A16
A17
A18
A19
26
26
26
26
C561
*0.1U
CLOSE TO U23
SI stage:
Add LPC debug port for software team
to debug convenient.
PV stage:
1. Reserve 0R for RF_OFF#
and BT_OFF# circuit.
Griffey 12/11/2004
2
4
1
3
5
CN27
SERIRQ
LFRAME#/FWH4
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
PCLK_591
LPC_DRQ0#
PCIRST#
32
Pin 24 if no pull-high,
will can't reboot.
PAVILION
SW1
*STS-055B
ENV1
BADDR0
BADDR1
SHBM
RD#
WR#
SELIO#
41
42
54
55
D/C#
143
142
135
134
130
129
121
120
A8
A9
A10
A11
A12
A13
A14
A15
113
112
104
103
48
A16
A17
A18
A19
WR1#
PC97551
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
+3V
+5V
16
17
*EIC-3801-15
3VPCU
RP2
MY4
MY5
MY6
MY7
10
9
8
7
6
1
2
3
4
5
MY3
MY2
MY1
MY0
PV stage:
Modify pin name.
10KX8
Griffey 12/10/2004
RP1
MY8
MY9
MY10
MY11
T70
T62
Sting 10/06/2004
PRESARIO
NBSWON#
138
139
140
141
144
145
146
147
150
151
5VPCU
3VPCU
MBCLK
MBDATA
168
169
170
171
172
175
176
1
124
125
126
127
128
131
132
133
34
34
T61
99
100
101
102
153
154
162
163
164
165
SHBM=1: Enable shared memory with host BIOS
TEMP_MBAT 34
MBATV
34
SWID2
C533
1U/16V
PSCLK1
PSDAT1
KB_CLK
KB_DAT
ENV1
C494
0.1U/0402
0.1U/0402
0.1U/0402
0.1U/0402
Should have a 0.1uF capacitor close to every
GND-VCC pair + one larger cap on the
supply.
RESERVE
FOR 97551
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
D14 2
1SS355
DNBSWON#
35,38
35,38
35,39
11
33,37
1
VOLME_UP#
VOLME_DN#
62
63
69
70
75
76
AGND
11
MY16
32
MY16
33,36,37,38 HWPG
11
SUSC#
31
VOLME_UP#
31 VOLME_DN#
21
VOLMUTE#
C567
5.6P
11
12
20
21
85
86
91
92
97
98
C566
8P
96
C562
DA0
DA1
DA2
DA3
DA output
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7
C452
10,12
161
Host interface
GA20/IOPB5
KBRST/IOPB6
VCCRTC
0R
AD0
AD1
AD2
AD3
IOPE0AD4
IOPE1/AD5
IOPE2/AD6
IOPE3/AD7
DP/AD8
DN/AD9
AD Input
IOPD3/ECSCI
5
6
10K
SI stage:
Change R352 value from 120K to 20M.
Sting 09/24/2004
7
8
9
15
14
13
10
18
19
22
23
R358
95
16
U23
DRQ0#
*0R
*0R
R359
AVCC
R321
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
LPC_DRQ0#
LPC_DRQ0#
VDD
10
34
45
123
136
157
166
LDRQ#(pin 8) internal is no use
C491
C550
0.1U/0402
10U/10V/0805
0.1U/0402
C546
C538
0.1U/0402
VBAT
KBC-NS87551L
VCCRTC
3VPCU
+3V
10
9
8
7
6
1
2
3
4
5
MY15
MY14
MY13
MY12
10KX8
R241
10K
MY16
Pin 103 internal is

"A19",Can't use to
GPIO
MY4
MY5
MY6
MY7
CP1
2
4
6
8
220PX4
1
3
5
7
MY8
MY9
MY10
MY11
CP2
2
4
6
8
220PX4
1
3
5
7
MY0
MY1
MY2
MY3
CP3
2
4
6
8
220PX4
1
3
5
7
MX4
MX5
MX6
MX7
CP4
2
4
6
8
220PX4
1
3
5
7
MX0
MX1
MX2
MX3
CP5
2
4
6
8
220PX4
1
3
5
7
MY12
MY13
MY14
MY15
CP6
2
4
6
8
220PX4
1
3
5
7
C440
220P_50V
MY16
8P4R-10K
3VPCU
5VPCU
R312
470K
591RESET#
C545
0.1U/0402
R354
R355
4.7K
4.7K
MBCLK
MBDATA
3VPCU
RN61
1
3
5
7
2
4
6
8
NBSWON#
DVD#
VOLME_UP#
VOLME_DN#
PROJECT : CT3
8P4R-10K
Size
C
Document Number
Date:
Rev
2A
KBC PCU-97551
Sheet
1
27
of
39
HDD, CD-ROM
CD-ROM
A
CDINL2
R123
20
CDINR2
R121
20
CDGND1
R122
PDIAG#
R105
6.8K
CDAUD_L
CDAUD_L
CD_GND
PLTRST_#
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0
CDAUD_R
6.8K
CD_GND
3.4K
0R
CDVCC
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
PDIOW#
PIORDY
IRQ14
PDA1
PDA0
PDCS1#
ODDLED#
PDIAG
CDVCC
R112
DASP_ON 11
*470R CDSEL
T44
+5V
HDDLED#
CN17
Q52
2N7002E
+5V
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PDDREQ
PDIOR#
C292
C291
C294
C293
0.1U/0402 0.1U/0402 0.1U/0402 0.1U/0402
PDDACK#
IOCS16#
PDIAG#
PDA2
PDCS3#
C295
10U/10V/0805
T56
CDVCC
CD.46
T46
CD.50
T45
CD-ROM
CDSEL
--> NC, Slave device
--> Low, Master device
R611
10K
ODDLED#
3
R612
CDAUD_R
60MIL
L15
PBY201209T-4A
+5V
R610
10K
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
51
52
51
52
20
*0R
ADD DASP_ON FOR IDE CABLE SELECT
CN18
PLTRST_#
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0
10
PDA[0..2]
10
PDD[0..15]
10
PDIOW#
10
PDDREQ
10
PIORDY
10
PDIOR#
10
IRQ14
10
PDDACK#
10
PDCS1#
10
PDCS3#
5,10,11 PLTRST#
PDA[0..2]
PDD[0..15]
PDIOW#
PDDREQ
PIORDY
PDIOR#
IRQ14
PDDACK#
PDCS1#
PDCS3#
PLTRST#
25
HDDLED#
HDD_VDD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
PDDREQ
PDIOW#
PDIOR#
PIORDY
PDDACK#
IRQ14
PDA1
PDA0
PDCS1#
HDDLED#
C558
*100P
PLTRST# R633
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PCSEL
--> NC, Slave device
--> Low, Master device
PCSEL
R134
470R
PDIAG
PDA2
PDCS3#
R135
*10K
60MIL
HDD_VDD L16
PBY201209T-4A
+5V
HDD_CONN
C298
HDD CONNECTOR0.1U/0402
PLTRST_#
47R
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
C299
1000P
C301
C302
10U/10V/0805
0.1U/0402
PROJECT : CT3

Size
Document Number
Custom
HDD&ODD
Date:
1

7
Rev
2A
CONN.
Sheet
28
of
8
39
5VPCU
27
IRDATA
27
IRCLK
R357
*4.7K
R363
*4.7K
C565
*27P
C569
*27P
5VPCU
PRESARIO
R366
*47R
5VPCU
R422
*4.7K
*4.7UF/6.3V
*IRM-368
CIR_IN
VCC
C574
IR2
27,31
U8
1
DAT
GND
IRCLK
RST#
IRDATA
5VPCU
1
2
3
4
5
6
7
8
9
PB2
PB3
TCC
RST#
VSS
PA0
PA1
PA2
PA3
PB1
PB0
OSCI
OSCO
VDD
PA7
PA6
PA5
PA4
18
17
16
15
14
13
12
11
10
R144
*10R
5VPCU
Y2
1
*12M/30PPM
*IRDC362
R356
*1K
RST#
C564
*1U/16V
PROJECT : CT3
Size
B
Document Number
Date:
Rev
1A
REMOTE IRDC362
Sheet
E
29
of
39
+5V_CRT2
CRT_R
CRT_G
CRT_B
C2
F1
FUSE1A6V_POLY
2
1
0.1U_0603_25V
CRT PORT
+5V_CRT2
16
+5V
Intel has required that the termination resistor (150 ohm)

should be placed at both side of GMCH and DB15.
CRT_R1
L66
0R
CRT_R2
L27
BLM18BA750SN1T
CRT_R3
CRT_G1
L67
0R
CRT_G2
L1
BLM18BA750SN1T
CRT_G3
CRT_B1
L68
0R
CRT_B2
L26
BLM18BA750SN1T
CRT_B3
T1
R11
R10
R7
C931
*10P
150R
150R
CN8
CRT_CONN
6
1
7
2
8
3
9
4
10
5
C932
*10P
C933
*10P
C934
5.6P
C935
5.6P
C936
5.6P
C6
5.6P
C350
5.6P
C14
5.6P
11
CRT_SENSE#
10,11
D
12
13
14
15
+3V
150R
EMI
D7
DA204U
17
1
+5V
R111
PV stage:
Adjust Capacitors and Bead to improve
CRT timing issue.
+5V
+5VFAN
AHCT1G125DCH
C12
FAN_PWR1
1
2
3
C274
T10U/10V
39R
39R
CRTVSYNC
CRTHSYNC
R160
0R
DDCDAT1
D6
DA204U
1
R110
10K
FAN
VSYNC1
+3V
1
2
3
C3
C5
C11
C13
*22P
*33P
*33P
*22P
D5
DA204U
1
27
HSYNC
C588
100P
2
D29
*DA204U
AHCT1G125DCH
DDCCLK
DDCCLK
R6
2.2K
R9
2.2K
Q20
1
2N7002E
3
DDCDAT
U46
VIN
VEN
VSET
*G993
*1K
VO
GND
GND
R703
GND
GND
+3V
D30
*DA204U
Q21
2N7002E
1
CRTHSYNC
3
R5
R8
2.2K
2.2K
FAN_PWR1
CRTVSYNC
D31
*DA204U
8
7
1
5
6
+5V
VFAN_1
DDCDAT
For EMI
HSYNC1
SI stage:
Add GMT solution for B-test to costdown.
Sting 09/24/2004
CRT_B3
U2
FAN
CONTROL
2
1
CRT_G3
4
2
FANSIG
C
R158
R159
DDCCLK1
CN15
Q12
DTC144EUA
VSYNC
0R
U1
1K
VFAN_1
Griffey 12/09/2004
Q11
IRLML5103
27
0.1U_0603_25V
R109
4.7K
CRT_R3
3
R157
DDCCLK1
+5V
C1045
*0.1U
D32
*DA204U
1
DDCDAT1
3
2
1
1
1
1
HOLE9
H-C295D110P2
Add ESD protection by Sting 08/03/2004
HOLE12
H-C236D110P2
HOLE19
H-TC236BC295D110P2
HOLE18
H-TS315BC295D110P2
HOLE10
H-C236D110P2
HOLE11
H-C236D110P2
HOLE8
H-C295D110P2
HOLE17
H-C276D165P2
HOLE7
H-TS315BC295D110P2
HOLE6
H-C295D110P2
HOLE16
H-C276D165P2
HOLE15
H-C276D165P2
HOLE5
H-TS315BC295D110P2
HOLE4
H-C295D110P2
HOLE14
H-C295D165P2
PAD6
EMIPAD433X157
HOLE2
H-C236D110P2
HOLE1
H-C236D110P2
EMI
PAD4
EMIPAD433X157
PAD3
EMIPAD433X157
HOLE24
H-D110N-CT3
HOLE23
H-TS315BC295D110P2
HOLE22
H-RE315X354D110P2
PAD5
EMIPAD433X157
PAD7
1
EMI spring
PROJECT : CT3
Size
C
Document Number
Date:
Rev
2A
FAN, CRT, EMI PAD

Sheet
1
30
of
39
VA
L2
BK2125-33T
VA_P
L42
5VPCU
C37
0.1U/0402
FBMJ2125HM330-T
+5VAMP
+5VAMP_PR
JACK_DETECT#
SPDIF
C54
0.1U/0402
C591
270P
*SI3443DV
Q5
C590
*270P
R41
*100K
C589
0.1U
CC0402
MIC_PR
21
21
27
11
11
D_RSPK+
D_LSPK+
VOLME_UP#
USBP4USBP4+
27
CIR_OUT
AGND
AGND
CIR_OUT
R19
VIN
C596
55
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
1
3
5
7
9
11
13
15
17
19
21
23
GND
D0+
D0DDCCLK
D1+
D1DDCDAT
D2+
D2HPD
CLK+
CLK49
51
53
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
58
58
57
57
C597
0.1U/50V
60
59
15,33,34,35,36,37,38
0R TVGND
S-CVBS1-PR
S-YD1-PR
S-CD1-PR
VOLME_DN#
27 VOLME_DN#
CIR_IN
27,29
CIR_IN
5VDOCK
MUX_IN
0.1U C594
CC0402
L44
FCM2012K800
VA_P
55
0.1U/50V
3
21
56
JACK_DETECT#
SPDIF
X-TX3P
24
27
X-TX3N
24
X-TX1P
24
X-TX1N
24
JACK_DETECT# 21
SPDIF
20,22
+5VAMP_PR
MUTE_LED 20,32
1394_TPA1+ 19
1394_TPA1- 19
C593
1394_TPB1+ 19
0.1U
1394_TPB1- 19
CC0402
DOCK5VON
C366
*0.022U
Q8
*DTC144EUA
5VDOCK
L43
32
S-CVBS
S-CVBS1-PR
L7
SBK201209T-151Y-S
C80
5VDOCK
DOCK_PRESENT
*33P
C64
5.6P
5VDOCK
VCC
IN_B1
*150R
S-YD
S-YD1-PR
L6
SBK201209T-151Y-S
*33P
VCC
IN_B1
IN_B0
R674
1
C598
120P
S-CD
S-CD1-PR
R283
100K
L5
SBK201209T-151Y-S
C128
*33P
C57
5.6P
+3V
D33
DA204U
SEL
COM
GND
VCC
IN_B1
S-YD1
D34
DA204U
+5V
SEL
6
4
GND
R675
2
D35
DA204U
1
S-CD1
S-CD1-PR
+5V
IN_B0
S-YD1-PR
3
C382
0.1U
CC0402
COM
S-CVBS1-PR
C374
0.1U
CC0402
U12
NC7SB3157
C121
5.6P
C383
0.1U
CC0402
150R
PR_INSERT# 27
S-CVBS1
+5V
NC7SB3157
R748 *150R
32
U13
5
C113
5.6P
3VPCU
COM
PR_INSERT#
NC7SB3157
150R
32
IN_B0
R673
CIR_OUT
SEL
GND
C77
5.6P
R747
C595
0.1U
CC0402
*150R
150R
C601
120P
DOCK_PRESENT 1
R37
Q7
2
2
0R
MMBT3904
1
C600
120P
SI stage:
Add ESD protection circuit
Sting 10/06/2004
by HP request.
U10
R746
VA_P
PR_INSERT#
FBMJ2125HM330-T
+5V
C58
5.6P
VOLME_DN#
CIR_IN
5VSUS
C592
0.1U
CC0402
C112
4
5
6
X-TX2P
X-TX2N
X-TX0P
X-TX0N
56
60
59
PR_PRESENT#
24
24
24
24
3
2
1
CN12
PR_PRESENT#
PV stage:
SEL
FUNCTION(COM)
1. Change L5,L6,L7,C57,C58,C64,C77,C113,C121 value to
LOW
IN_B0
improve S-video quality.
2. Reserve S-video impedance
match
circuit.
HIGH
MUX_IN
R713
1
IN_B1
SI stage:
Griffey 12/22/2004
Add R713 to enable the mux in the Tampa-2 cable.
(connects the component TV output to the composite/Svideo output lines).
Sting 10/12/2004
1
4.7K
PROJECT : CT3
Size
Custom
Document Number
Date:
Rev
2A
CABLE DOCKING
Sheet
E
31
of
39
AV BOARD
KEYBOARD CONNECTOR
TOUCH PAD CONNECTOR
CN2
C264
5VSUS
0.1U/0402
CN5
27
27
TPDATA
27
TPCLK
5VTP
L13
SBK160808T-221
L14
SBK160808T-221
C289
*10P
12
11
10
9
8
7
6
5
4
3
2
1
TPDATA-1
TPCLK-1
C290
*10P
25
TP_L#
25
TP_R#
MX1
MX7
MX6
MY9
MX4
MX5
MY0
MX2
MX3
MY5
MY1
MX0
MY2
MY4
MY7
MY8
MY6
MY3
MY12
MY13
MY14
MY11
MY10
MY15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
BK1608HS800-T
L39
12
UP CONTACT
TOUCH PAD
27
25,27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
25,27
27
27
27
27
27
27
CN20
24
MX6
MX7
MY7
1
2
3
4
C611 C612 C613
*AV_CONN
1
*33P
UP CONTACT
*33P
*33P
DOWN CONTACT
MX6
KEYBOARD
MX7
ENTER
MENU
CN10
POWER BOARD
MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7
27
NUMLED
27
NBSWON#
27
MUSIC#
27
DVD#
20,31 MUTE_LED
8
6
4
2
8
6
4
2
8
6
4
2
27
MY16
25,27 PWR_LED
RF_LED#
14
RF_LINK
Q2
BLUELED
L47
Q3
15,25
L45
L46
7
5
3
1
7
5
3
1
7
5
3
1
5VPCU
+5V
DTC144EUA
DTC144EUA
C605
0.1U/0402
3VSUS
DAUGHTER BOARD
LFBR32164M241
RP8
20
LFBR32164M241
RP9
LFBR32164M241
RP10
MLB-160808-0220A
DOWN CONTACT
MX0
BACK
MX1
MX2
PLAY/PAUSE
11
11
USBP2+
USBP2-
11
11
USBP5+
USBP5+3V
MX3
FORWARE
STOP
MX4
MX5
VOL UP
MUTE
MX6
MX7
VOL DN
WIRELESS
B
POWER BOARD
C606
0.1U/0402
CN11
C607
0.1U/0402
MLB-160808-0220A
MLB-160808-0220A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
3
5
7
9
11
13
15
17
19
19
5VSUS
2
4
6
8
10
12
14
16
18
20
BT_OFF#
BLUELED
BT_OFF# 11,27
BC0EX1
BC0EX2
S-YD
S-CD
S-CVBS
14
14
31
31
31
TOP VIEW
C608
0.1U/0402
20
2
BT_OFF#
C609
0.1U/0402
DAUGHTER BOARD
A
PROJECT : CT3

Size
Document Number
Custom
BLUETOOTH/TP/BTB
Date:
5
Sheet
1
Rev
1A
32
of
39
CPU VCC_CORE
(MAX1907)
SI stage:
Change PR143 value from 100K ohms to
10K ohm to solve panel display abnormal
issue.
Sting 10/06/2004
5VPCU
+3V
Vert_C
10R 1907VDD 1
10K
VIN_1907
2.2U/10V/X5R
Vert_C
1907AGND
1
2
3
B0
B1
B2
DPRSLPVR
35
5
6
7
8
PQ116
0.844V ~ 1.356V
27A
30
IR7821
LX
32
1907LX
PL7
Vert_C
DL
29
0.62uH
1907DL
CPU_CORE
PR149
0.001/2W/5%
1907_7 2
2
1
2P
GND
PGND
11
28
TON
40
PC156
1907AGND
1907VCC
PQ118
2P
1P
PQ117
27,37
20
PR153 0R
VRON
VRON-1
7
STP_CPU#
*10K
PR150
1907TON
DPSLP
3
2
1
2,11
IR7832
SUS
3
2
1
DPRSLPVR
PC160
PC161
CPU_CORE
1P
+
PD28
SHDN
EC31QS04
PR255
11
PC159
IR7832
DPRSLPVR
CPU_CORE
IR7821
PR151
PR152
1.5K
2K/F
330U/2.5V/ESR-9/POS
1907B0
1907B1
1907B2
15,31,34,35,36,37,38
330U/2V/ESR-9/SP
S2
S1
S0
PQ115
.22U/25V/0805/X7R
330U/2V/ESR-9/SP
6
5
4
Vert_C
1907DH
330U/2.5V/ESR-9/POS
1907S2
1907S1
1907S0
1907AGND
33
D5
D4
D3
D2
D1
D0
CM1
T60
1907VCC
0.748V for suspend mode

(Deeper sleep)
DH
CLKEN
PC147
1907BST
CM2
21
22
23
24
25
26
2
2R
CPU_VID5
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0
1
PR256
3
2
1
4
4
4
4
4
4
34
31
3
2
1
38
V+
BST
5
6
7
8
CLK_EN#
VDD
10
VCC
IMVPOK
VIN
CH501H-40
2.2U/25V/1206/X7R
SYSPOK
37
PC151
PD27
2.2U/25V/1206/X7R
36
PC155
10U/25V1210/X6S
10K
VIN
PL6
3216-800T40
PC154
10U/25V1210/X6S
PR148
+3V
PC150
10U/25V1210/X6S
HWPG
VIN_1907
PC149
0.1U
PR254
HWPG
0R
PC153
2200P
27,36,37,38
5,11 IMVPOK
PC148
Vert_C
PC146
5
6
7
8
PR143
PR144
1907VCC
5
6
7
8
1U/16V
PC152
100K
49.9K/F
PR154
1907TIME
39
1907AGND
270P
PC163
1907CC
12
OA+
OA-
TIME
FB
CC
CSN
15
1907REF
ILIM
CSP
18
1907ILIM
27
DDO
NEG
14
POS
PC166
4700P
PR156
3.01K/F
PC164
100P
CM-1
CM+1
1907_OA-
PR158
PR157
200/F
200/F
PC162
*470P
Vert_C
CM1
CM2
1907FB
PR160
1.24K/F
13
PU3
MAX1907AETL
41
GND
REF
232K/F
B
1907FB
19
0.22U
PC165
PR159
1907_OA+
17
16
PJ1 SHORT
PC167
PR105
34.8K/F/0603
100P
1907REF
PR162
1907AGND
1907VCC
1907VCC
1907AGND
100K/F
1907AGND
1907AGND
1907AGND
1907B2
GND
PR165
0R
0R
1907B1
VCC_BOOT
B1
B2
GND GND
REF REF
OPEN OPEN
VCC VCC
REF VCC
SUSPEND MODE (SUS=HIGH)

Output
S1
S0
S2
OPEN VCC
PR164
0.748V
PR167
0R
1907B0
B0
GND
REF
OPEN
VCC
VCC
Output
1.708V
1.372V
1.036V
0.700V
1.212V
D5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output
1.196V
1.180V
1.164V
1.148V
1.132V
1.116V
1.100V
1.084V
1.068V
1.052V
1.036V
1.020V
1.004V
0.988V
0.972V
0.956V
0.940V
0.924V
0.908V
0.892V
0.876V
0.860V
0.844V
0.828V
0.812V
0.796V
0.780V
0.764V
0.748V
0.732V
0.716V
0.700V
D5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output
1.708V
1.692V
1.676V
1.660V
1.644V
1.628V
1.612V
1.596V
1.580V
1.564V
1.548V
1.532V
1.516V
1.500V
1.484V
1.468V
1.452V
1.436V
1.420V
1.404V
1.388V
1.372V
1.356V
1.340V
1.324V
1.308V
1.292V
1.276V
1.260V
1.244V
1.228V
1.212V
PROJECT : CT3

Size
Document Number
Custom
Date:
5
Rev
2A
CPU CORE POWER

Sheet

1
33
of
39
ADAPTER 18.5V 65W 3.51A

3S2P 4400mAH
3S4P 8800mAH
20 MIL TO CABLE DOCK
VIN
VIN
PQ44
PR1
VA-1
PR140
SBM1040
10K
PL2
PC2
.1U/50V
PC1
.1U/50V
VIN-1
A04407
1
CSSP-1
7
6
POWER JACK
AO4407
2P
1 VA-2
2P
1
2
3
4
1P
1P
0.033/1W/3720
8
7
6
5
1
2
3
4
PR2
200K
8
7
6
5
PR4
PL3
G2
PQ45
15uH/4.4A/CDRH104R
PQ51
PC14
REF4.096
75K/F
27
CH501H-40
75K/F
10K
AD_AIR
G1
16
17
15
VCTL
CELLS
CSIN
BATT
18
19
CSIP
PGND
1772LX
1772DLOV
22
23
LX
26
PR16
PU2
REF4.096
PR17
PR20
100K
2.61K/F
3VPCU
CH501H-40
2N7002E
15K
PC265
PR257
PR29
Vert_C
1M
ICTL
14
REFIN
13
ACIN
ICHG
ACOK
12
11
10
GND
GND
CCV
7
CCI
CCS
CLS
REF
4
6
1772CCI
1772CCV
.01U/50V
100K/F
2
13.7K/F
3VPCU
PR22
10,15,23,26,27,31,36
PC19
CELL-SET
.1U/50V
HI = LDO =
CC-SET = 1.05V/A
4 CELL
LOW = LDO/2 = 3 CELL
CC-SET
REF4.096
PR28
PD41
.01U/50V
PQ156
CELL-SET 27
1772ICTL PR26
1U/10V/X7R
PR27
12.4K/F
2
2N7002E
3VPCU
ACIN
PR142
3VPCU
1772CELLS
10K/F
1772ICHG
1K
PR25
27
1U/10V/X7R
DTA124EUA
PC17
PR24
.1U/50V
PC16
Vert_C
PR141
1772_5.4V
1772_5.4V
PC15
PR23
1772CCS 5
CH501H-40
1772CLS
ACOK
LDO
DCIN
1
1772DCIN
Battery Low 7.5V
PC13
PQ114
100K
MAX1772EEI
PD25
PD26
PR12
CSIN
27
VA
CSIP
3
BL/C#
PQ49
2N7002E
37.4K/F
VA2
DLOV
1772BST
PR19
12.4K/F
BL/C#
DHI
2
3
PR18
100K
25
SYS_I
CSSN
27
LMV331
27
CSSP
Vert_C
24 1772DHI
CSSN
2N7002E
Vert_C
PR21
27
Vert_C
1772_5.4V
PC10
.1U/50V
CH501H-40
28
Vert_C
PQ48
P343
D/C#
1U/10V/X7R
INP
PR15
47K
PU1
P3411
P342
D/C#
0R
47.5K/F
CSSP
PR14
SW1010C
PC9
BST
PR13
4.7R
.1U/50V
PD3
.1U/50V
PC12
.1U/50V
PR9
PC11
PD2
PR11 33R
20
P344
4.7R
DLO
1772_5.4V
2N7002K
PC145
1772DLO
2
3VPCU
.1U/50V
PQ47
2
1
5VPCU
3VPCU
.1U/50V
.1U/50V
VIN
PC144
.1U/50V
PC7
10U/25V/1206
PC6
P346
10U/25V/1206
10K
PD1
CH501H-40
1P
1P
PR8
21
P345
100K
PC8
ACOK
3VPCU
4.7R
2P
0.05/1W/3720
7 S1D2
4.7R
FBMJ3216HS800
PR7
PR10
PC5
2P
CSIN-1
SI4814DY
PL4
PR6
MBAT+
100U/25V
1U/25V
PR5
PC134
PC4
PC3
2
2.2U/25V
PR3
100K
D1
DTA124EUA
PC254 1
3P348
S2
PQ46
FBMJ3216HS800
1
2
3
4
5
PQ42
15,31,33,35,36,37,38
JP1
PD21
CSSN-1
PL1
FBMJ3216HS800
VA2
SBM1040
CSIP-1
1
PR139 10K
Vert_C
BATTERY CHARGER
PD22
2
From Docking CNN
VA
CC-SET 27
PC18
10K
.1U/50V
121K/F
Charge
Current=VICTL*1.24
1U/25V
1772ACOK
1772ACIN
PC20
PR30
1ST_BAT_CONN
.01U/50V
CN9
8
7
1
5
4
3
2
6
PL5
FBMJ3216HS800
10K/F
MBAT+1
MBAT+
TEMP_MBAT 27
P3417
P3418
PC24
PR31
.01U/50V
100K/F
PR32
100R
PR33
100R
MBATV
MBATV
MBDATA
MBCLK
MBCLK
PR34
PD6
ZD5.6V
PROJECT : CT3
14K/F
PD5
ZD5.6V
27
PC26
3,27
.01U/50V
MBDATA
3,27
Size
Document Number
Custom
Rev
2A
MAX1772/CHARGING
Date:
5
Sheet

1
34
of
39
VIN
SMDDR_VTERM
+2.5V
PR174
22R
PR172
1M
+5V
+1.5V
PR175
22R
PR176
22R
+3V
PR177
22R
+15V
PR178
47R
PR179
1M
PR180
1M
MAIND
36,38
Z2706
Z2705
Z2704
Z2707
2
2
PC168
2200P
PQ122
2N7002E
PQ123
2N7002E
PQ121
2N7002E
PQ119
DTC144EUA
MAINON
27,39
Z2725
MAIND
MAINON_G
PQ124
2N7002E
Vert_C
PQ125
2N7002E
Vert_C
PQ126
2N7002E
SI stage:
Change PR178 value from 22 ohm to 47 ohm, Intel has required the timing
sequence of +1.5V and +3V in the system, we'd like to increase the value to
make +3V discharge slowly to meet the specification of falling time.
Sting 10/19/2004
1.5V_S5
VIN
5V_S5
3V_S5
+15V
PR181
1M
PR182
22R
PR184
22R
PR258
22R
PR185
1M
Z2712
S5_OND
Z2724
S5_OND
36
S5_ONG
S5_ON 2
PR186
PQ128
1M
DTC144EUA
PC169
2200P
2
1
S5_ON
27,38
PQ129
2N7002E
PQ131
2N7002E
PQ157
2N7002E
PQ132
2N7002E
Vert_C
VIN
3VSUS
PR187
1M
5VSUS
PR189
22R
2.5VSUS
PR190
22R
+15V
PR259
22R
PR191
1M
SUSD
36
Z2710
Z2709
SUSON 2
2
PR192
1M
PC171
2200P
PQ133
DTC144EUA
SUSON
27,38
SUSD
SUSON_G
PQ135
2N7002E
PQ136
2N7002E
PQ158
2N7002E
PQ137
2N7002E
PROJECT : CT3

Size
Document Number
Custom
Date:
5
Rev
2A
DISCHARGE
Sheet

1
35
of
39
3VPCU
3V_S5
PQ141
AO6402
Vert_C
35
PR198
1
PL8
10R_0805
2
S5_OND
S5_OND
100mA
3
3V_S5
VIN
VIN_1999
S0-S5
1
2
5
6
Vert_C
3V_S5
3V_S5
FBMJ3216HS800
11,12,35
PR197
1999_RST#
1999_V+
PC174
1
2
PC177
PC176
PC178
PC184
PC185
PQ142
PC179
2.2U/25V/1206/X7R
4
.1U/50V
PC258
10U/25V/1206
10R_0805
2.2U/25V/1206/X7R
PR199
PC175
.1U/50V
PC172
0.1U
2200P
390K
PR200
100K
2.2U/25V
PC173
.1U/50V
1999_RST#
1
AO4914
PL9
PC182
1999_LX3
3VPCU
3VPCU
13
14
PR203
FB5
V+
PRO-
DL5
ILIM5
LDO5
SKIP-
VCC
TON
DH5
BST5
LX5
22 3VPCU
PC259
2
1999_DL5
19
4
PQ154
18
PC193
PC192
1U/10V/X7R
1999_DH5
16
PC190
SI4800DY
1999_LX5
15
PL10
PC191
.1U/50V
AO4702
51R
1
3
+5V
SUSD
12,14,15,21,27,28,30,31,32,35
PR206
PC199
4.7U/10V
+5V
5VSUS
PC201
+5V
5VSUS
0.1U
60.4K/F
4.6A
5V_AL
ALWAYS
PQ145
AO4812
1999_REF2V
PR205
S0-S1
1999_ILIM3
1999_ILIM5
0.1U
S0-S3
Vert_C
80.6K/F
82.5K/F
5VSUS
MAIND
2A
PR208
12,16,18,19,31,32,35
PC203
60.4K/F
PR207
5VPCU
5VPCU
3
2
1
PD30
CHP202U
10,25,27,29,31,32,33,34,37,38
PC198
.1U/50V
5.8UH/6A/CDRH104R
PQ155
5VPCU
PC195
2.2U/25V
S0-S3
MAIND
5VPCU
330U/6.3V/ESR-25
1999VCC
35,38
1.5A
PC196
PC194
PR204
VIN_1999
17
1999_BST5
10,11,14,16,17,18,19,20,22,32,35
PC188
0.1U
PC189 .1U/50V
20
MAX1999
0R
Vert_C
1999_BST3
21 5VPCU
3VSUS
3VSUS
PC186
0.1U
10U/25V/1206
1999SKIP# 12
OUT5
2.2U/25V/1206/X7R
1999_ILIM5 11
OUT3
REF
.1U/50V
1999PRO# 10
FB3
1.5A
2200P
0R
23
+
9
PR202
24
35
DL3
GND
SUSD
3VSUS
1U/16V
1
SHDN-
+3V
+3V
7
PC187
2
ILIM3
2,3,8,10,11,12,13,14,15,17,20,23,25,27,30,31,32,33,35
1999_DL3
3
2
1
1999_REF2V
ON5
5
6
7
8
1999_ILIM3 5
+3V
S0-S1
LDO3
25
26
DH3
4.3A
AO4812
ON3
27
3
5V_AL
28
LX3
PGOOD
ALWAYS
PQ143
1
2
BST3
5
6
7
8
N.C
2
1
1
2
C
330U/6.3V/ESR-25
.1U/50V
1
4.7U/10V
PU4
27,33,37,38 HWPG
1999_REF2V
PC181
2.2U/25V
2
PR201
100K
.1U/50V
5.8UH/6A/CDRH104R
3V_AL
3VPCU
PC180
3VPCU
3VPCU 10,15,23,26,27,31,34
1999_DH3
2.6A
5VPCU
5V_S5
1999_DL3
PC255
.01U/50V
5VPCU
2
1999-4
1999_DL3 1
50mA
3
AO6402
+10V
2
1999-5
12,35
5V_S5
S0-S5
5V_S5
+10V
+15V
PC170
S5_OND
PD40
CHN217
ALWAYS
PQ127
PD31
CHN217
PC204
.01U/50V
1
2
5
6
Only for power
.01U/50V
PC205
.1U/50V
PROJECT : CT3
+15V
35
Size
Document Number
Custom
MAX1999
PC256 PC257
.1U/50V 2.2U/25V
Date:
8
/ 3VPCU / 5VPCU / 15V

2
Sheet
36
1
of
39
Rev
2A
5VPCU
Vert_C
PR209
Vert_C
1992_VCC
PL11
PC212
PC213
24
19
2
SI4800DY
1992_BST17
BST
1992_DH 15
DH
PC214
1
2
3
PQ146
PL12
2.5UH/7.5A
.1U/50V
1992_LX 16
LX
1992_DL 18
DL
VIN_1992
PR212
V+
14
PR210
POK
LSAT
SHDN
23
AGND
21
N.C
Ra
1992SHDN#
VRON
PR211
27,33
0R
PGND
11
CSP
12
CSN
10
OUT
N.C
TON
REF
13
FB
1992_FB
1992AGND
ILIM
Rb
N.C
*100P
PR215
1992TON
*0R
1992REF
PR216
1992_CSP
.1U/50V
2
SKIP
1
2
3
PR214
100K/F
AO4704
PC220
1
27,33,36,38
1992AGND
20
PQ147
10K/F
HWPG
0R
2.49K/F
PC219
2.5V_PG
PC221
5.1K/F
1U/16V
22
8
7
6
5
VCC
PR213
PC208
1992AGND
8
7
6
5
1
2
1
2
2.2U/25V
.1U/50V
DCR 10mOHM
PC216
PC215
*220U/4V
PC218
470U/4V/ESR-15/NEO
S0-S1
PC217
6.5A
2200P
VCCP 2,3,4,5,8,9,10,12
.1U/50V
1.05V
2.2U/10V/X5R
CH501H-40
4.7U/25V/1210/X7R
VCCP
0805/5A
4.7U/25V/1210/X7R
VCCP
4.7U/25V/1210/X7R
VIN_1992
PC211
OVP/UVP
PC210
20R
PC207
VDD
PC209
PD32
VIN
1992_VDD
1U/16V
PJ2 SHORT
1992ILIM
MAX1992ETG
1992AGND
1992AGND
1992AGND
PU5
PC222
PR218
*470P
Vout=VFB(1+Ra/Rb)
#VFB=0.7V
47.5K/F
1992AGND 1992AGND
PROJECT : CT3

Size
Document Number
Custom
Date:
1
Rev
2A
VCCP
Sheet
5
37
of
39
Vert_C
Vert_C
Vert_C
VIN_1845
5VPCU
1
2
3
27,35
27,35
PR221
HWPG
S5_ON
SUSON
0R
Rd
28
PP5
0R
PP6 11
PR225
0R
PP7 12
13
1845ILIM1
PQ152
ILIM1
10
6
GND
23
1845VCC
PD43
1
2
RDSON 17mOHM
Vert_C
PR228
Re
*5.11K/F
Vout=(1+Re/Rf)*1
PC244
MAX8743
PR230
1845REF
Fix 2.5V Output
Vert_C
PC242
.22U/25V/0805/X7R
*100P
REF
SKIP
PC237
AO4704
2
*0R
1845REF
ILIM2
PC264
1845FB1
51845TON1
PR224
ON2
4
1
FB1
ON1
2.5UH/7.5A
TON
PGOOD
UVP
PC243
OUT1
PC239
CS1
FB2
S0-S5
1.5V_S5
1845_DL1
OUT2
2
5
6
7
8
2
1845_LX1
24
14
3
2
1
22
27
DL1
PR226
0
VCC
LX1
CS2
PR223
1845ILIM2
DH2
15
12,35
PL15
16
6A
*EC31QS04
27,33,36,37
1845_DH1
18
*15K/F
RDSON 17mOHM
26
1845FB2
DH1
PQ150
SI4800DY
AO4704
BST1
LX2
PC240
2.2U/10V/X5R .1U/50V
1
1
2
PQ151
DL2
1845_BST1
470U/4V/ESR-15/NEO
PR220
21
25
2.2U/25V
VDD
BST2
.1U/50V
17
1845_DH2
2.5UH/7.5A
Rc
Vout=(1+Rc/Rd)*1
1845_LX2
PL14
2.2U/25V
.1U/50V
*EC31QS04
470U/4V/ESR-15/NEO
PD42
20
1.5V_S5
1.5V_S5
5
6
7
8
PC263
8
7
6
5
PC234
19
1845_DL2
PC233
3
2
1
PC236
1845_BST2
OVP
1845VDD
20R
1
2
3
2.5VSUS 5,8,9,13,35,39
PU6
V+
S0-S3
Vert_C
2
1
1
2
8
7
6
5
PC232
.1U/50V
0805/5A
100U/25V
1845VCC
SI4800DY
PC231
4.7U/25V/1210/X7R
PR222
2200P
VIN_1845
PQ149
PC262
PC230
PD35
CHP202U
VIN
PL13
.1U/50V
.1U/50V
2200P
2.5VSUS
2.2U/25V/1206/X7R
6.5A
4.7U/25V/1210/X7R
2.5VSUS
VIN_1845
PC228
PC226
1U/16V
PC227
PC261
PC260
PC225
PR229
0R
Vert_C
Rf
*10K/F
*100P
1845VCC
PR232
PR231
240K/F
180K/F
1845ILIM1
1845ILIM2
PR233
PR234
100K/F
100K/F
Fix 1.5V Output
2.5VSUS
1.5V_S5
PC245
.1U_0603_25V
PC223
5
6
7
8
5
6
7
8
.1U_0603_25V
MAIND
+2.5V
MAIND 4
35,36
MAIND
35,36
PQ153
1A
PQ148
3
2
1
+1.5V
5A
S0-S1
3
2
1
S0-S1
+1.5V 4,8,11,12,35
+2.5V 5,6,8,12,35
PC249
0.1U
PC224
D
+1.5V
SI4800DY
+2.5V
SI4800DY
MAIND
0.1U
PROJECT : CT3

Size
Document Number
Custom
2.5VSUS
Date:
1
Rev
2A
/ 1.5V_S5
Sheet
5
38
of
39
DDR
1.25V (0.2A)
S0-S3
330U/2.5V/ESR-9/POS
5,13 SMDDR_VREF
SMDDR_VTERM
PC250
SMDDR_VREF
1.2A
+
SMDDR_VTERM
S0-S1
PR251
27,35
MAINON
MAINON
1
2
3
4
LP2996_SD#
100K
PC251
PC252
GND
VTT
SD
PVIN
VSENSE AVIN
VREF VDDQ
PU7
SMDDR_VTERM
7,13,35
2.5VSUS
2.5VSUS 5,8,9,13,35,38
LP2996
PC253
.1U/16V
.1U/16V
PR253
8
7
6
5
10U/6.3V
200K
Footprint/PSOP8-8P
B
PROJECT : CT3

Size
Document Number
Custom
Date:
5
Rev
2A
DDR_VTERM
Sheet
1
39
of
39

HP Dv4000 - Quanta Ct3

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5

PAGE 3 --- 1. Add R733 as pull-up resistor for PREQ#.

Remove R701 & R702 for unused PCI1510RVGF circuit.

PAGE 27 --- 1. Reserve 0R for RF_OFF# and BT_OFF# circuit.

PAGE 28 --- 1. Change HDD and ODD select definition.

CT3 BLOCK DIAGRAM

PENTIUM-M / ALVISO / ICH6-M

478 Pins (micro FC-PGA)

CRT port PAGE: 30

CPU CORE MAX1907

DDR I/F 2.5V

SYSTEM POWER MAX1845

PCB THICKNESS: 1.2mm

33MHZ, 3.3V PCI

1st IDE - HDD

2nd IDE - CDROM

CARDBUS / IEEE 1394

PAGE: 16, 17, 18, 19

3.3V LPC, 33MHz

PCI DEVICES IRQ ROUTING

GBIT ETHERNET AD16

Quanta Computer Inc.

Monday, December 27, 2004

DOTHAN FSB 400

DOTHAN FSB 533

* Frequence select by CPU auto sense.

FSC FSB FSA

Place these termination to close CK410M.

Quanta Computer Inc.

Monday, December 27, 2004

Layout note: 0.5" max length.

H_GTLREF = 2/3 * VCCP +-2%

Quanta Computer Inc.

Monday, December 27, 2004

Dothan CPU (Host Bus)

Remove +1.8V optional cause of the

Quanta Computer Inc.

Monday, December 27, 2004

CPU POWER / GND

This group should be

It's point to point, 55ohm trace,

Quanta Computer Inc.

Monday, December 27, 2004

Place near chip

These pins can't leave as NC

CFG[3:17] have internal pullup.

CFG[18:19] have internal pulldown.

Low=PCIE Reverse Lanes

Low=FSB Dynamic ODT Disabled

Low=CPU core VCC 1.05V

Quanta Computer Inc.

Monday, December 27, 2004

For terminal R-pack.

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY B

Quanta Computer Inc.

Monday, December 27, 2004

Note: All VCCSM pins

Note: All VCCSM pins

Quanta Computer Inc.

Quanta Computer Inc.

For Doathan A-X step

For Doathan B-X step & later