BO CO TI VI IU KHIN AVR

Thnh vin:
V nh Chinh Phm Hoi Phc Trn Minh Tnh Hunh Thanh Long

GVHD: ThS L Hoi Ngha

NI DUNG
Tng quan v vi iu khin AVR Kin trc vi iu khin AVR Atmega16 Gii thiu PWM AVR iu khin ng c DC Cc cng c lp trnh AVR

&1.Tng quan v vi iu khin AVR

AVR do hng Atmel ch to ra, l h VK 8bit theo cng ngh mi vi nhng tnh nng rt mnh c tch hp trong trong chip. AVR n nh hn rt nhiu so vi dng VK 8051 Tnh nng mi ca h AVR : - Giao din SPI ng b, giao tip I2C, USART. - Cc li vo ra B Timer/Counter 8bit v 16bit lp trnh c. - Tch hp b bin i ADC 10bit. - C sn cc knh bm xung PWM. - B nh EEPROM.

Lch s pht trin AVR

Ban u AVR MCU (Micro Controller Unit) c pht trin ti mt phng ASIC (Application Specific IC) Trondheim Nauy, l ni m 2 ngi sng lp ca Atmel Nauy lm vic nh l sinh vin. V n c bit n vi tn RISC (Micro RISC). Khi cng ngh ny c bn cho Atmel, cu trc bn trong AVR c pht trin xa hn bi Alf v Vegard ti Atmel Nauy, mt cng ty con ca Atmel c thnh lp bi 2 thnh vin trn. AVR l vit tt ca Advanced Virtual RISC, nhng cng c th l vit tt cho 2 ngi sng lp: Alf and Vegard [RISC], nhng Atmel ni rng AVR chng l vit tt ca bt c ci g c. Mt sn phm u tin ca AVR l AT90S8515, cng c ng gi DIP 40 chn ging nh 8051 vy, n bao gm phc hp a ch cc thnh phn bn ngoi v data bus. iu khc bit l chn RESET (8051 RESET tch cc mc cao, AVR li tch cc mc thp), ngoi tr im ny, cc ng ra u ging nhau.

u th ca MCU AVR
Kt ni phn cng cho AVR n gin vi nhng linh kin thng dng nh in tr, t in, thch anh. Dng ra iu khin Port ln v khng cn dng in tr ko. Thit k mch np cho AVR kh n gin giao tip qua cng LPT, COM, USB. H tr ISP lp trnh trc tip trn mch. H tr lp trnh trn nn ngn ng ASM, C vi nhiu cng c h tr nh CodeVision, AVR Studio.

Phn loi AVR

a. tinyAVRs : - 1-8 kB b nh chng trnh. - 8-32 chn. -Hn ch cc thit b ngoi vi.

b.megaAVRs:
- 4-256 kB b nh chng trnh. -28-100 chn. - M rng tp lnh. -Nhiu thit b ngoi vi. c. XmegaAVRs: - 16-256 kB b nh chng trnh. -44-100 chn. - M rng cc thit b nh DMA, "Event System", v h tr m ha . -M rng thit b ngoi vi vi DACs. d. Application specific AVRs: -megaAVRs vi cc thnh phn c bit khng c trong cc sn phm khc ca AVR nh l LCD controller, USB controlller, PWN, CAN, v.v...

The New 32-Bit AVRs: Nm 2006 Atmel tung ra VDK mi, 32 bit, kin trc AVR32. Chng bao gm tp lnh SIMD v DSP, cng vi cc thnh phn x l{ audio v video. Dng VDK 32 bit ny c d nh cnh tranh vi VDK ARM. Cc tp lnh ging vi cc nhn RISC khc, nhng khng tng thch vi cc dng AVR trc cng nh nhn ARM khc.

Mt s AVR ph bin
AT90S1200 AT90S2313 AT90S2323 and AT90S2343 AT90S2333 and AT90S4433 AT90S4414 and AT90S8515 AT90S4434 and AT90S8535 AT90C8534 ATtiny10, ATtiny11 and ATtiny12 ATtiny15 ATtiny22 ATtiny26 ATtiny28 ATmega8/8515/8535 ATmega16 ATmega161 ATmega162 ATmega163 ATmega169 ATmega32 ATmega323 ATmega103 ATmega64/128/2560/2561

&2. Kin trc vi iu khin AVR Atmega16

AVR c cu trc Harvard, trong ng truyn cho b nh d liu (data memory bus) v ng truyn cho b nh chng trnh (program memory bus) c tch ring. Data memory bus ch c 8 bit v c kt ni vi hu ht cc thit b ngoi vi, vi register file. Trong khi program memory bus c rng 16 bits v ch phc v cho instruction registers.

S chn

S khi

Cc Port xut nhp

Port A:
Port A l bn cnh l Port xut nhp thng thng 8 bit cn c thit k cho b ADC chuyn i tng t s. Port A thit k vi in tr ni treo ln mc cao. L port xut nhp thng thng 8 bit. L port xut nhp thng thng 8 bit. Bn cnh Port C cn c mt s chn giao tip JTAG PC5-TDI, PC3-TMS, PC2 TCK. L port xut nhp thng thng 8 bit. VCC, AVCC, AREF, XTAL1, XTAL2, RESET

Port B:

Port C:

PORT D:

Cc chn khc:

CPU

CPU (tt)
ALU:
ALU lm vic trc tip vi cc thanh ghi chc nng chung. Cc php ton c thc hin trong mt chu kz xung clock. Hot ng ca ALU c chia lm 3 loi: i s, logic v theo bit.

Thanh ghi trng thi:

y l thanh ghi 8 bit lu tr trng thi ca ALU sau cc php tnh s hc v logic.

CPU(tt)
C: Carry Flag c nh . Z: Zero Flag C zero. N: Negative Flag kt qu php ton m. V: Twos complement overflow c b 2. S For signed tests (S=N XOR V) kim tra 2 c N v V. H: Half Carry Flag c s dng trong BCD cho mt s ton hng. T: Transfer bit used by BLD and BST instructionsc s dng lm ni trung gian trong cc lnh BLD,BST. I: Global Interrupt Enable/Disable Flag y l bit cho php ton cc ngt. Nu bit ny trng thi logic 0 th khng c mt ngt no c phc v.

CPU(tt)
Atmega 16 c 32 thanh ghi chc nng chung thc thi nhiu tc v trong
Mt 8 bit output ton hng v mt 8 bit cho input kt qu. Hai 8 bit output ton hng v mt 8 bit cho input kt qu. Hai 8 bit cho output kt qu v mt 16 bit cho input kt qu. Mt 16 bit cho output ton hng v mt 16 bit cho input kt qu.

Memorry
B nh chng trnh Flash
B nh Flash 16KB ca ATmega16 dng lu tr chng trnh vi rng 16 bit. Do cc lnh ca AVR c di 16 hoc 32 bit nn b nh Flash c sp xp theo kiu 8KX16. B nh chng trnh ch gm 1 phn l Application Flash Section nhng trong cc chip AVR mi chng ta c thm phn Boot Flash section. Boot Section. Thc cht, application section bao gm 2 phn: phn cha cc instruction v phn cha interrupt vectors. Cc vector ngt nm phn u ca application section t a ch 0x0000 v di n bao nhiu ty thuc vo loi chip v phn cha instruction nm lin sau . Cc chng trnh c vit sau a ch .

Memorry(tt)
B nh d liu SRAM

Memorry
y l phn cha cc thanh ghi quan trng nht ca chip, vic lp trnh cho chip phn ln l truy cp b nh ny v b nh ny gm cc phn sau:
Phn 1: l phn u tin trong b nh d liu bao gm 32 thanh General Purpose Rgegister GPR. Tt c cc thanh ghi ny u l cc thanh ghi 8 bits. Tt c cc chip trong h AVR u bao gm 32 thanh ghi Register File c a ch tuyt i t 0x0000 n 0x001F. Mi thanh ghi c th cha gi tr dng t 0 n 255 hoc cc gi tr c du t -128 n 127 hoc m ASCII ca mt k t no Cc thanh ghi ny c t tn theo th t l R0 n R31. Chng c chia thnh 2 phn, phn 1 bao gm cc thanh ghi t R0 n R15 v phn 2 l cc thanh ghi R16 n R31. Phn 2: l phn nm ngay sau SFR bao gm 64 thanh ghi IO hay cn gi l vng nh IO. Vng nh I/O l ca ng giao tip gia CPU v thit b ngoi vi. Vng nh I/O c th c truy cp nh SRAM hay nh cc thanh ghi I/O. Nu s dng instruction truy xut SRAM truy xut vng nh ny th a ch ca chng c tnh t 0x0020 n 0x005F. Nhng nu truy xut nh cc thanh ghi I/O th a ch ca chng c tnh t 0x0000 n 0x003F. Phn 3: internal SRAM l vng khng gian cho cha cc bin trong lc thc thi chng trnh.

Memorry(tt)
B nh d liu EEPROM
ATmega16 cha b nh d liu EEPROM dung lng 512 byte, v c sp xp theo tng byte, cho php cc thao tc c/ghi tng byte mt. EEPROM c tch ring v c a ch tnh t 0x0000H.

Qu trnh thc thi lnh

Cc instruction c cha trong b nh chng trnh Flash memory di dng cc thanh ghi 16 bit. B nh chng trnh c truy cp trong mi chu k xung clock v 1 instruction cha trong program memory s c load vo trong instruction register, instruction register tc ng v la chn register file cng nh RAM cho ALU thc thi. Trong lc thc thi chng trnh, a ch ca dng lnh ang thc thi c quyt nh bi mt b m chng trnh PC (Program counter). Hu ht cc instruction u c thc thi trong 1 chu k xung clock.

&3. Gii thiu PWM AVR iu

khin ng c DC
PWM l cm t Pulse Witdth Modulation l mt k thut dng iu khin ng c DC bng cch iu chnh rng ca xung. Khong thi gian m xung mc logic cao s ng vi thi gian c dng in qua ng c v ngc li. PWM s dng k thut ng m ngun cung cp cho ng c vi nhng khong thi gian gin cch khc nhau t iu khin c tc ca ng c.

Cu to ng c DC
ng c mt chiu c ng dng rng ri trong rt nhiu lnh vc iu khin t ng. Cu to ca ng c mt chiu gm c Stato v Roto. Stato thng lm bng nam chm vnh cu hoc nam chm in nhng ng c cng sut ln. Roto l nhng cun dy c qun trn li thp. Roto thng l b phn quay cn Stato th ng yn. Cc u ra ca cun dy Roto c t ln b c gp c cc chi than nhm m bo t thng qua cun dy Roto l lin tc tc l duy tr lc t tc dng quay ln Roto mt cch lin tc. ng c DC c mt s loi nh Servo, Step, Encoder

Thit k PWM nh th no?

Dng IC 555 to xung:

Thit k PWM nh th no?

Dng module PWM tch hp sn ca AT Mega 16 AT Mega 16 c 4 knh PWM tng ng vi 4 chn l:

Timer 0

Timer 1

Timer 2

S khi
S khi Timer 16 bit:

Cc ch nh thi
Ch Thng Thng: y l ch hot ng n gin nht ca Timer .B m s lin tc m tng ln cho n khi vt qu gi tr ln nht TOP v sau s c khi ng li ti gi tr Bottom.Trong cc hot ng thng thng th c trn s c thit lp khi gi tr trong Timer t gi tr khng v khng b xo i.Tuy nhin nu m ngt trn c chp nhn th c ngt s t ng b xo khi ngt c thc hin.Gi tr trong Timer c th c vit vo bt c lc no.

Cc ch nh thi(tt)
Ch So Snh (CTC) : y l ch m gi tr trong Timer lun c so snh vi gi tr trong thanh ghi ORC .Khi gi tr trong Timer bng gi tr trong thanh ghi ORC th gi tr trong Timer s b xo i.Gi tr trong ORC ng vai tr l gi tr TOP cho b m.Ch ny cng cho php to ra tn s so snh u ra.Tuy nhin trong ch ny nu gi tr mi ghi vo thanh ghi ORC m nh hn gi tr tc thi ca b m th th 1 so snh s b l, khi b m s m n gi tr ln nht sau ri xung gi tr 0 trc khi so snh tip theo xut hin.

Cc ch nh thi(tt)
Ch Fast PWM:
Cho php to ra sng vi tn s cao.S khc bit c bn gia Fast PWM vi cc loi PWM khc l n ch s dng 1 sn dc.B m s m t Bottom n Max sau khi ng li t bottom. Trong ch khng o u ra ca chn so snh OCx s bi xo khi c php ton so snh gia TCNTx v thanh ghi ORC l bng nhau. V s c st ln 1 khi gi tr t Bottom. Trong ch o ,u ra o s c set ln 1 khi s so snh gia thanh ghi ORC v gi tr trong Timer bng nhau v s b xo khi gi tr t Bottom.Trong c hai trng hp ny tn s ca ch Fast PWM u gp i so vi ch phase correct PWM s dng hai sn dc.

Cc ch nh thi(tt)
Ch Phase correct PWM:
Ch ny hot ng da trn hai sn ln xung.B m s m lin tc t gi tr BOTTOM n gi tr MAX v sau t gi tr MAX n gi tr BOTTOM.Trong ch so snh khng o chn so snh (OCx) s b xa khi gi tr TCNTx bng gi tr OCRx trong qu trnh m ln v s c set bng 1 khi gi tr so snh xut hin trong qu trnh m xung.Ch so snh o th cc gi tr l ngc li.Vi hot ng hai sn xung ny th ch ny khng to ra c tn s nh nh ch mt sn xung .Nhng do tnh cn i ca hai sn xung th n tt hn cho iu khin ng c.

PWM Timer 1 16 bit

Step 1: pin PWM l output bng cch set gi tr trong thanh ghi DDRn.X Step 2: chn ch PWM bng cch set thanh ghi TCCR1A Step 3: chn xung clock bng cch set thanh ghi TCCR1B Step 4: chn gi tr ca thanh ghi OCRn Step 5: bt u PWM

Code PWM ch Pharse Correct

S dng 2 knh OC1A, O1CB:
Step1: OC1A, OC1B output:
DDRD=0x30=0b001100000;

PORTD=0x00;
Step2: PWM Mode Pharse Correct
TCCR1A=0xF1=0b11110001;

Step3: Select clock source

TCCR1B=0x8B;

Step4: set OCRL=0x00, OCRH=0x00; Step5: bt u PWM

Mt s mch iu khin ng c DC bng PWM

Mch cu H:

Mt s mch iu khin ng c DC bng PWM(tt)

Mch 1 Fet 1 Role

Mt s mch iu khin ng c DC bng PWM(tt)

Mch IC 298:

&4.Cc cng c lp trnh AVR

Thit k phn cng Lp trnh iu khin

Thit k phn cng

Thit k ngun 5V cho AVR y l bc khi u quan trng v cn thit, v nu khng c b ngun n nh cho con AVR th d c lm mch np ng, cu hnh ng cc chng trnh np, AVR vn lm vic khng tt. Dn n vic chng trnh np khng c c AVR. Sau y l s ngun 5V:

Thit k phn cng(tt)

S mch np qua cng LPT

Thit k phn cng(tt)

S mch np qua cng LPT dng IC m 74HC244

Thit k phn cng(tt)

Mch np qua cng USB AVR 910

Thit k phn cng(tt)

KT NI MCH NP VI AVR

Lp trnh iu khin
Cng c lp trnh:
AVR Studio CodeVision

Lp trnh Input-Output
Cu trc chn ca AVR c th phn bit r chc nng (vo ra) trng thi (0 1) t ta c 4 kiu vo ra cho mt chn ca avr.Khc vi 89 l ch c 2 trng thi duy nht (0 1) . c bit ngun t chn ca AVR kho iu khin Led trc tip (mA) cn 89 ch l vi uA . iu khin cc chn ny chng ta c 2 thanh ghi ->PORTx :gi tr ti tng chn (0 1) c th truy cp ti tng bit PORTx.n ->DDRx : thanh ghi ch trng thi ca tng chn , vo hoc l ra .Gi tr 1 l ra v 0 l vo .

Lp trnh Input-Output

Thanh ghi DDRx y l thanh ghi 8 bit (ta c th c v ghi cc bit thanh ghi ny) v c tc dng iu khin hng cng PORTx (tc l cng ra hay cng vo). Nu nh mt bit trong thanh ghi ny c set th bit tng ng trn PORTx c nh ngha nh mt cng ra. Ngc li nu nh bit khng c set th bit tng ng trn PORTx c nh ngha l cng vo. Thanh ghi PORTx y cng l thanh ghi 8 bit (cc bit c th c v ghi c) n l thanh ghi d liu ca cng Px v trong trng hp nu cng c nh ngha l cng ra th khi ta ghi mt bit ln thanh ghi ny th chn tng ng trn port cng c cng mc logic. Trong trng hp m cng c nh ngha l cng vo th thanh ghi ny li mang d liu iu khin cng. C th nu bit no ca thanh ghi ny c set (a ln mc 1) th in tr ko ln (pull-up) ca chn tng ng ca port s c kch hot. Ngc li n s trng thi hi-Z. Thanh ghi ny sau khi khi ng Vi iu khins c gi tr l 0x00. Thanh ghi PINx y l thanh ghi 8 bit cha d liu vo ca PORTx (trong trng hp PORTx c thit lp l cng vo) v n ch c th c m khng th ghi vo c.

Lp trnh Input-Output
c d liu t ngoi th ta phi thc hin cc bc sau:

a d liu ra thanh ghi iu khin DDRxn t cho PORTx (hoc bit n trong port) l u vo (xa thanh ghi DDRx hoc bit). Sau kch hot in tr pull-up bng cch set thanh ghi PORTx ( bit). Cui cng c d liu t a ch PINxn (trong x: l cng v n l bit).

a d liu t vi iu khin ra cc cng cng c cc bc hon ton tng t.

Ban u ta cng phi nh ngha l cng ra bng cch set bit tng ng ca cng .v sau l ghi d liu ra bit tng ng ca thanh ghi PORTx.

Thanks so much