Q1:What if we declare output as reg in dataflow modelling?

Q2:jahan pe else if use kartay hain wahan else k baad begin aur end lagatay hain ya koi farq nahen parta Q3:slide 51 lecture 4 combinational logic.old (important) Q4:slide 53 lecture 4 combinational logic.old (important) egarding multiple assignments of single variable also ambiguity r

Q5: Transforming n-bit input to m-bit output is encoding n>m.slide 54 lecture 4 combinational logic.old (important) Q6: m-bit input to m^2 or less bit-outputs is function of decoder. Q7: new lecture slide 70 and 72 consult kr k confirm karna hai. Q8: slide 75 new important conditions for avoiding latches. Q9: slide 77 new guidlines for avoiding glue logic Q10: In xilinx basic elements are Configurable Logic Blocks, I/O blocks and wire s and switches. CLBs consist of slices and each slice has logic cells. Q11: slide 90 new and 91 too. Q12: Lecture 5 new slide 20 (important) D flip flop with negative edge reset. Edge qualifier as senstivity list should only be edge qualifier. Q13: Lecture 5 new Slide 22 two cycles active low reset What do you mean by two cycles active low reset? Q14: Lecture 5 new slide 25. What do u mean by feedback registers.