A

ACL10 LA-1331 Schematics Document

2

REV 2.0 (For 030)

INTEL Mobile P4 uFCBGA/uFCPGA Northwood

MCH-M(845-MP) + ICH3-M + SQ17
3

Title

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE
Size
Document Number
Custom
401207
Date:
A

, 18, 2004

Sheet
E

TRANSFERRED FROM THE CUSTODY OF THE COMPE

Rev
2A
of

83

ACL10 LA-1331 BLOCK DIAGRAM

4

Mobile
Northwood
(uFCBGA/uFCPGA)

Thermal Sensor
MAX6654MEE
NE1617

Clock Generator
W320-04
ICS9508-05

PAGE 5

PAGE13

PAGE 4,5,6

PSB

CRT
Connector

CPU VID
PAGE 6

400MHz

PAGE 15

Brookdale-M

AGP
Connector

TV-OUT
Connector
PAGE 15

AGP Bus

PAGE 14

200MHz (2.5V)

MCH-M 845MP
625 BGA

SO-DIMM x 2(DDR)

Memory Bus

BANK 0,1,2,3

PAGE 10,11,12

REV B0
PAGE 7,8,9

PAGE 28
266MHz (1.8V)

Mini PCI
PAGE 27

LAN
RTL8100-B(L)

RJ-45
PAGE 20

PCI BUS
33MHz (3.3V)

FAN Controller

USB
PAGE 26

PAGE 34

IDE HDD

ICH3-M

PAGE 19

DC/DC Interface
RTC Battery

421 BGA

CARDBUS

Audio CD-DJ
OZ165

REV B1

OZ6933

PAGE 23

48MHz (3.3V)

ATA 66/100

PAGE 20

Slot 0/1

HUB Interface

Smart Media

PAGE 22,23

PAGE 16,17,18

IEEE1394
VT6306

PAGE 29

24.576MHz (3.3V)

LPC BUS 33MHz (3.3V)

AC-LINK

PAGE 21

AC97 CODEC
ALC 101/201

PAGE 30

Super I/O

Embedded
Controller

LPC47N227
REV B

MDC
Connector

PAGE 19

BATTERY
Charger

Audio Amplifier
TPA0132

PAGE 31

PAGE 38

RJ-11

PAGE 14

NS PC87591

PAGE 24

PAGE 37

CD-ROM/DVD

Power Interface &

TEMP. sensing circuit

PAGE 20

PAGE 32

PAGE 38,39,40,42

Parallel
PAGE 25

FIR
PAGE 25

Scan KB

FDD

BIOS & I/O PORT

PAGE 33

PAGE 14

PAGE 19

Title

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE
Size
Document Number
Custom
401207
Date:
A

, 18, 2004

Sheet
E

TRANSFERRED FROM THE CUSTODY OF THE COMPE

Rev
2A
of

83

Voltage Rails

PIR
REV 0.1

Power Plane

Description

S1

S3

S5

VIN

Adapter power supply (19V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

1.2VP

1.2VP switched power rail for CPU VID

ON

OFF

OFF

+1.25VS

1.25VS power rail

ON

OFF

OFF

+1.5VS

AGP 4X

ON

OFF

OFF
ON*

+1.8VALW

1.8V always power rail

ON

ON

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+2.5V

2.5V power rail

ON

ON

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

+3V

3.3V power rail

ON

ON

OFF

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5V

5V power rail

ON

ON

OFF

+5VS

5V switched power rail

ON

OFF

OFF

+12VALW

12V always on power rail

ON

ON

ON*

+12V

12V power rail

ON

ON

OFF

+12VS

12V switched power rail

ON

OFF

OFF

RTCVCC

RTC power

ON

ON

ON

+SDREF

+SDREF power

ON

ON

OFF

Note : "ON*" means that this power plane is "ON" only with AC power available, otherwise it is "OFF".

External PCI Devices

Device

IDSEL#

REQ#/GNT#

Interrupts

IEEE 1394

AD16

PIRQA

Mini-PCI

AD18

1/4

PIRQC/PIRQD

CardBus

AD20

PIRQA/PIRQB

LAN

AD17

PIRQB

SM

AD22

PIRQC/PIRQD

Date

Page
7

Change R212,R214 & R213 to 8.2K ohm for Intel recommand

2001/12/29

14

Stuff R361=22 Ohm and no-stuff R360 for Data-IN1 of MDC module.

2001/12/29

15

Change L28 & L29 to 0 Ohm for EMI issue.

2001/12/29

16

Change R39 power-plane to +3VALW for Resume-well Power-plane(+3VALW)

2001/12/29

17

DEL C73, C87, C371 for EMI issue.

2001/12/29

17

Change L37 power-plane to +1.8VS for Intel recommand.

2001/12/29

17

Change R279 power-plane to +3VS for Intel recommand.

2001/12/29

17

Change U29 pinV22,U18 & P14 power-plane to +CPU_CORE for Intel recommand.

2001/12/29

17

Change R284 power-plane to +3VALW for Intel recommand.

2001/12/29

18

Change "SMB_ALERT#" power-plane to +3VALW for "RESUME-WELL" power-plane(+3VLAW).

2001/12/29

18

Exchang D13,D14,D16,D17,D18 and R28,R34,R30,R29 to RP135,R466,R468 for cost-down.

2001/12/29

20

Add D43 for leakage.

2001/12/29

21

Exchang L42 to L52,L53, L54, L55 for ME limitation.

2001/12/29

27

Add D42 for leakage.

2001/12/29

31

Add R465 for PC99 Spec.

2001/12/29

34

Add C368, C369 for EMI solution.

2001/12/29

35

EC control "EC_RSMRST#". ->DEL R92, Stuff R48.

2001/12/29

35

Change R97 to 100K for "VGATE" of Max1718A issue.-> Change PR134= 0 Ohm.

2002/01/07

39

Change PR68 from 10k_1% to 10.5k_1%.(increase 5valwp to 5.125v).

2002/01/07

40

Change PR81 from 2.15k_1% to 1.87k_1%.( CPU thermal OTP from 83+-3C to 85+-3C).

2002/01/07

42

Add PR147, PR161 to 2.7_0805. for EMI requirement.

2002/01/07

42

Add PC120, PC121, PC122 to 1000pf. for ESD.

2002/01/07

42

Add PQ44 to 2N7002 for CPU SPEED STEP.

2002/01/07

42

Change PR130, PR152 from 0 to 2.2. for EMI requirement.

2002/01/07

42

Change PR143 from 53.6k_1% to 100k_1%. for CPU OCP.

2002/01/07

42

Change PR145 from 100k_1% to 53.6k_1%. for CPU OCP.

2002/01/07

42

Change PR148 from 30k_1% to 48.7k_1%. for CPU OCP.

2002/01/07

42

Change PU12 VIN from +2.5VP to +3VALWP.

REV 0.2
Date

Page

2002/01/11

EC SM Bus1 address
3

EC SM Bus2 address

Device

Address

Device

Address

Smart Battery

0001 011Xb

MAX6654MEE

1001 110Xb

1010 000Xb

OZ165

1011 0100b (B4h)

1011 000Xb

Smart Battery

0001 011Xb

Docking

0011 011Xb

DOT Board

XXXX XXXXb

EEPROM(24C16/02)
(24C04)

Clock Generator
W320-04 / ICS9508-05

1101 0000

Description
Change PH1 and PH2 design by high active for AC-IN issue.

REV 0.3
Date

Page

Description

None

REV 1.0
Date

Page

None

Date

Page

2002/04/10

Address

40

REV 2.0

ICH3-M SM Bus address

Device

Description

2001/12/29

20

GCR: (For LAN Issue)

<1>Isolation U18 pin6 for Realtek application notice.
<2>Change R204 from 5.9K+-1% to 5.6K +-1%.
<3>Change L23 from 4.7UH to 0 ohm.

DDR SODIMM SM Bus address

DDR SLOT
4

SA2

SA1

SA0

DDR SODIMM0 (REVERSE)

DDR SODIMM1 (NORMAL)

Title

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE
Size
Document Number
Custom 401207
Date:
A

, 18, 2004

Sheet
E

TRANSFERRED FROM THE CUSTODY OF THE COMPE

Rev
2A
of

83

+CPU_CORE

K2
K4
L6
K1
L3
M6
L2
M3
M4
N1
M1
N2
N4
N5
T1
R2
P3
P4
R3
T2
U1
P6
U3
T4
V2
R6
W1
T5
U4
V3
W2
Y1
AB1

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

J1
K5
J4
J3
H3
G1

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
ADS#

AC1
V5
AA3
AC3

AP#0
AP#1
BINIT#
IERR#

H6
D2
G2
G4

BR0#
BPRI#
BNR#
LOCK#

AF22
AF23

BCLK0
BCLK1

HREQ#[0..4]

HREQ#[0..4]

HADS#

+CPU_CORE

7
7
7
7

HBR0#
HBPRI#
HBNR#
HLOCK#

13
13

CLK_HCLK
CLK_HCLK#

7
7
7

HIT#
HITM#
HDEFER#

2
10K
2
200_0603

CLK_HCLK
CLK_HCLK#

F3
E3
E2

A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35

D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8
D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63

Mobile
NorthWood

HIT#
HITM#
DEFER#

H1
H4
H23
H26
A11
A13
A15
A17
A19
A21
A24
A26
A3
A9
AA1
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
AD1
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AD4
AD8

VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56

1
R87
1
R280

A10
A12
A14
A16
A18
A20
A8
AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19
B7
B9
C10
C12
C14
C16
C18
C20
C8
D11
D13
D15
D17
D19
D7
D9
E10

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HD#[0..63]

VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74

HA#[3..31]

F13
F15
F17
F19
F9
F11
E8
E20
E18
E16
E14
E12

U7A

HA#[3..31]

VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73

B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24

HD#[0..63] 7

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

NorthWood

+CPU_CORE

Title

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE
Size
Document Number
Custom
401207
Date:
A

, 18, 2004

Sheet
E

TRANSFERRED FROM THE CUSTODY OF

Rev
2A
of

83

VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
SKTOCC#
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128

H_INTR

H_PWRGD

PM_CPUPERF#

1
200

Place resistor <100mils from

CPU pin

H_TRDY#

F1
G5
F4
AB2
J6

16
16
16
16
16
16
16
16
16
16
7

H_A20M#
H_F_FERR#
H_IGNNE#
H_SMI#
H_PWRGD
H_STPCLK#
H_DPSLP#
H_INTR
H_NMI
H_INIT#
H_RESET#

H_A20M#
C6
H_F_FERR#
B6
H_IGNNE#
B2
H_SMI#
B5
H_PWRGD AB23
H_STPCLK#
Y4
H_DPSLP# AD25
H_INTR
D1
H_NMI
E5
H_INIT#
W5
H_RESET# AB25

7
7
13
13

H_DBSY#
H_DRDY#
H_BSEL0
H_BSEL1

H5
H2
AD6
AD5
H_THERMDA
H_THERMDC

+1.2VP
1
R66

H_THERMTRIP#

2
56

ITP_BPM0
ITP_BPM1
ITP_PRDY#
ITP_PREQ#

ITP_TCK
ITP_TDI
+1.2VP

ITP_TMS
ITP_TRST#

Murata LQG21F4R7N00

L3

ITP_TMS
ITP_TCK
ITP_TRST#
ITP_TDI

AC26
AD26

H_VSSA

L24
P1
R215

R67

51.1_1%

+CPU_CORE

2
R82
2
R62
2
R81
2
R68

NorthWood

51.1_1%

ITP_PREQ#
1
200_0603
ITP_PRDY#
1
200_0603
ITP_BPM0
1
200_0603
ITP_BPM1
1
200_0603

+H_GTLREF1
1

All of these pin

connected inside

GTLREF0
GTLREF1
GTLREF2
GTLREF3
NC1
NC2

AA21
AA6
F20
F6
A22
A7

TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
TESTHI10
GHI#

AD24
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6

TESTTHI0_1

DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3

E22
K22
R22
W22

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3

F21
J23
P23
W23

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

ADSTB#0
ADSTB#1

L5
R5

+CPU_CORE

TESTTHI2_7

TESTTHI8_10

1
R221
1
R223

2
56
2
56

1
R70

2
56

PM_CPUPERF#
H_DSTBN#[0..3]

H_DSTBP#[0..3]

H_ADSTB#0 7
H_ADSTB#1 7

E21
G25
P26
V21

DBR#

AE25

PROCHOT#
MCERR#
SLP#

C3
V6
AB26

H_PROCHOT#

VSSA
VSSSENSE

AD22
A4

H_VSSA
1

VCCA
VCCSENSE
VCCIOPLL
NC7
NC8

ITP_CLK0
ITP_CLK1
COMP0
COMP1

+CPU_CORE

1
R79

2
56

H_SLP#

H_SLP#
2
R218

NorthWood
3

C359
6,42
6,42
6,42
6,42
6,42

+5VALW

.1UF

GTL Reference Voltage

2
16
15
14
13
12
11
10
9

2
1

49.9_1%

1
EC_SMD2 29,32
THRM#
33

R25
C20

R_B

+H_GTLREF1
EC_SMC2 29,32

Trace width>=7mila

2 H_PROCHOT#
470

1
R287

Q23
3904

C21

100_1%
1UF_0603

220PF
4

NC
STBY
SMBCLK
NC
SMBDATA
ALERT
ADD0
NC

2
Q22
3904

R_A

470

PROCHOT#

R24

1
1
2

2
R38

R37

1K

10K

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

Address:1001_110X

NE1617/ MAX6654MEE

1
1K

2
R65

NC
VCC
DXP
DXN
NC
ADD1
GND
GND

33

10K

U6
1
2
3
4
5
6
7
8

1. Place R_A and R_B near CPU.

2. Place decoupling cap 220PF near CPU.(Within
500mils)

R36

R274

1K

Layout note :

2
2

C56
.1UF

+5VALW

16

+CPU_CORE

TP2

+CPU_CORE

1
200

AD2
AD3

NC3
NC4

R275

H_THERMDA
H_THERMDC

H_DBI#[0..3] 7

H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3

DBI#0
DBI#1
DBI#2
DBI#3

CPU_VR_VID4
CPU_VR_VID3
CPU_VR_VID2
CPU_VR_VID1
CPU_VR_VID0

W =15mil

C55
2200PF_0603

H_DSTBP#[0..3] 7

+1.2VP

+5VALW

Thermal Sensor
MAX6654MEE

PM_CPUPERF# 16
H_DSTBN#[0..3] 7

H_DBI#[0..3]

C231
33UF_D2_16V

8P4R_1.5K

THERMTRIP#

TCK
TDI
TDO
TMS
TRST#

AF25
AF3

Mobile

THERMDA
THERMDC

D4
C1
D5
F7
E6

AD20
A5
H_VCCIOPLL AE23

8
7
6
5

C19
33UF_D2_16V

RP21
1
2
3
4

DBSY#
DRDY#
BSEL0
BSEL1

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5

J26
K25
K26
L25

DP#0
DP#1
DP#2
DP#3

A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#
DPSLP#
LINT0
LINT1
INIT#
RESET#

AC6
AB5
AC4
Y6
AA5
AB4

H_VCCA
TP1

A2

4.7UH_80mA_0805
2
4.7UH_80mA_0805
2

L27

B3
C4

RS#0
RS#1
RS#2
RSP#
TRDY#

2
R78

H_INIT#

H_RS#0
H_RS#1
H_RS#2

VCCVID

H_RESET#

H_NMI

7
7
7

AF4

1
51.1_1%

2
R220

H_DPSLP#

NC5
NC6

H_F_FERR#

H_STPCLK#

AE21
AF24

1
56
1
300

H_IGNNE#

VID0
VID1
VID2
VID3
VID4

2
R80
2
R224

U7B

H_SMI#

AE5
AE4
AE3
AE2
AE1

H_A20M#

VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181

1
200
1
200
1
200
1
200
1
200
1
200
1
200
1
200

F8
G21
G24
G3
G6
J2
J22
J25
J5
K21
K24
K3
K6
L1
L23
L26
L4
M2
M22
M25
M5
N21
N24
N3
N6
P2
P22
P25
P5
R1
R23
R26
R4
T21
T24
T3
T6
U2
U22
U25
U5
V1
V23
V26
V4
W21
W24
W3
W6
Y2
Y22
Y25
Y5

2
R282
2
R77
2
R84
2
R72
2
R222
2
R285
2
R71
2
R83

AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE26
AE7
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF26
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
B26
B4
B8
C11
C13
C15
C17
C19
C2
C22
C25
C5
C7
C9
D10
D12
D14
D16
D18
D20
D21
D24
D3
D6
D8
E1
E11
E13
E15
E17
E19
E23
E26
E4
E7
E9
F10
F12
F14
F16
F18
F2
F22
F25
F5

+CPU_CORE

SCHEMATIC, M/B LA-1331

Size

Rev
2A

401207
Date:

TRANSFERRED FROM THE CUSTODY OF THE COMPE

Document Number

+5VALW
B

, 18, 2004

Sheet
E

of

83

Layout note :

Layout note :

Place close to CPU, Use 2~3 vias per PAD.

Place .22uF caps underneath balls on solder side.
Place 10uF caps on the peripheral near balls.
Use 2~3 vias per PAD.

Place close to CPU power and

ground pin as possible
(<1inch)

Please place these cap in the socket cavity area

Used ESR 25m ohm cap total ESR=2.5m ohm

+CPU_CORE

1
C382
+
220UF_D2_4V_25m

C383
+
220UF_D2_4V_25m

C384
220UF_D2_4V_25m

C381
+
@220UF_D2_4V_25m

1
C86
+
@220UF_D2_4V_25m

C390
220UF_D2_4V_25m

C68
+
220UF_D2_4V_25m
2

C57
+
220UF_D2_4V_25m

1
C385
+
220UF_D2_4V_25m

C331
10UF_6.3V_1206_X5R

C322
10UF_6.3V_1206_X5R

1
C316
10UF_6.3V_1206_X5R

C307
10UF_6.3V_1206_X5R

C299
10UF_6.3V_1206_X5R

+CPU_CORE

+CPU_CORE

1
C380
+
220UF_D2_4V_25m

C332
10UF_6.3V_1206_X5R

C323
10UF_6.3V_1206_X5R

C317
10UF_6.3V_1206_X5R

C308
10UF_6.3V_1206_X5R

+
C300
10UF_6.3V_1206_X5R

+CPU_CORE

Please place these cap on the socket north side

C341
.22UF_X7R

C340
.22UF_X7R

C339
.22UF_X7R

C338
.22UF_X7R

1
C293
.22UF_X7R

C294
.22UF_X7R

C295
.22UF_X7R

1
C296
.22UF_X7R

1
C297
.22UF_X7R

C52
10UF_6.3V_1206_X5R

C45
10UF_6.3V_1206_X5R

1
C30
10UF_6.3V_1206_X5R

C26
10UF_6.3V_1206_X5R

C24
10UF_6.3V_1206_X5R

+CPU_CORE

+CPU_CORE

C342
.22UF_X7R

C302
10UF_6.3V_1206_X5R

C22
10UF_6.3V_1206_X5R

C65
10UF_6.3V_1206_X5R

C62
10UF_6.3V_1206_X5R

+CPU_CORE

C311
10UF_6.3V_1206_X5R

1
C344
10UF_6.3V_1206_X5R

C329
10UF_6.3V_1206_X5R

C320
10UF_6.3V_1206_X5R

+CPU_CORE

C351
10UF_6.3V_1206_X5R

CPU Voltage ID
+3VS

Please place these cap on the socket south side

C49
10UF_6.3V_1206_X5R

C37
10UF_6.3V_1206_X5R

5,42
5,42
5,42
5,42
5,42

CPU_VR_VID0
CPU_VR_VID1
CPU_VR_VID2
CPU_VR_VID3
CPU_VR_VID4

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4

5,42
5,42
5,42
5,42
5,42

C298
10UF_6.3V_1206_X5R

C286
10UF_6.3V_1206_X5R

C64
10UF_6.3V_1206_X5R

C59
10UF_6.3V_1206_X5R

+CPU_CORE

RP50
8P4R_1K
8
7
6
5

R362
1K

1
C28
10UF_6.3V_1206_X5R

C25
10UF_6.3V_1206_X5R

1
2

C23
10UF_6.3V_1206_X5R

1
2
3
4

+CPU_CORE
3

C305
10UF_6.3V_1206_X5R

1
C335
10UF_6.3V_1206_X5R

C325
10UF_6.3V_1206_X5R

C315
10UF_6.3V_1206_X5R

+CPU_CORE

C348
10UF_6.3V_1206_X5R

EMI Clip PAD for CPU

PAD1

PAD2
1

PAD3
1

COMPAL ELECTRONICS, INC

PAD-2.5X3

PAD-2.5X3

PAD-2.5X3

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331 TRANSFERRED

Size

Document Number

Rev
2A

401207
Date:
A

FROM THE CUSTODY OF THE COMPE

, 18, 2004

Sheet
E

of

83

HD#[0..63]

HD#[0..63] 4

HSWNG0
HSWNG1

2
1

AC2
AC13
1

R_E

ST0
ST1
ST2

AGP_ADSTB0
AGP_ADSTB0#
AGP_ADSTB1
AGP_ADSTB1#
AGP_SBSTB
AGP_SBSTB#

AGP_ADSTB0
AGP_ADSTB0#
AGP_ADSTB1
AGP_ADSTB1#
AGP_SBSTB
AGP_SBSTB#

R24
R23
AC27
AC28
AF27
AF26

AD_STB0
AD_STB#0
AD_STB1
AD_STB#1
SB_STB
SB_STB#

14
14
14
14
14
14
14
14
14

AGP_FRAME#
AGP_DEVSEL#
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_PAR
AGP_REQ#
AGP_GNT#
AGP_PIPE#

AGP_FRAME#
AGP_DEVSEL#
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_PAR
AGP_REQ#
AGP_GNT#
AGP_PIPE#

Y24
W28
W27
W24
W23
W25
AG24
AH25
AF22

G_FRAME#
G_DEVSEL#
G_IRDY#
G_TRDY#
G_STOP#
G_PAR
G_REQ#
G_GNT#
PIPE#

Trace
width>=7mila

49.9_1%

1UF_0603

220PF

GTL Reference Voltage

1. Place R_E and R_F near MCH

2. Place decoupling cap 220PF near MCH pin.(Within 500mils)

AGP_ADSTB0

2
R265

AGP_ADSTB0#
1
@8.2K

2
R247

1
8.2K

AGP_ADSTB1

2
R239

AGP_ADSTB1#
1
@8.2K

2
R230

1
8.2K

AGP_SBSTB

2
R231

Place closely
ball P26

C292
.1UF

Place closely pin P22

CLK_AGP_MCH
2

RBF#
WBF#

AE22
AE23

AGP_RBF#
AGP_WBF#

VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40

A19
A23
A27
D5
D9
D13
D17
D21
E1
E4
E26
E29
F8
F12
F16
F20
F24
G26
H9
H11
H13
H15
H17
H19
H21
J1
J4
J6
J22
J29

AGP_ST0
0=System memory is DDR
1=System memory is SDR

AGP_ST0

**

2
R213

1
2K

2
R216

RP18
AGP_FRAME# 1
AGP_TRDY# 2
AGP_PAR
3
AGP_STOP# 4

@8P4R_8.2K
8
7
6
5

RP17
AGP_GNT#
1
AGP_REQ#
2
AGP_IRDY# 3
AGP_DEVSEL# 4

@8P4R_8.2K
8
7
6
5

RP15
1
2
3
4

@8P4R_8.2K
8
7
6
5

AGP_WBF#
AGP_PIPE#
AGP_RBF#

1
8.2K

2
R262

2
R237
CLK_AGP_MCH

1
36.5_1%

R268
@33

CLK_AGP_MCH 13

AGP_RBF# 14
AGP_WBF# 14

@10PF

+1.5VS

R51
1K_1%_0603

Place this cap near AGP Conn.

+AGP_NBREF
R56
1K_1%_0603

C120
.1UF

HUB Interface Reference

+1.8VS

Layout note :
1. Place R_C and R_D in middle of Bus.
2. Place capacitors near MCH.

R290
301_1%

C313

Layout note :

R209
150_1%

P22

+1.5VS
C337

100_1%

H_DSTBN#[0..3] 5
H_DSTBP#[0..3] 5

C238
.01UF

Place this cap near MCH

+AGP_VGAREF

BROOKDALE(MCH-M)

+1.5VS
4

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

+CPU_CORE

R210
301_1%

AD25

C319
.01UF

C326

14
14
14
14
14
14

N22
K27
K5
L24
M23
K7
J26
A3
A7
A11
A15

R269

R_F

H_DSTBN#[0..3]
H_DSTBP#[0..3]

AA21

AGP_SBA[0..7] 14

1
AG25
AF24
AG26

R273

24.9_0603_1%
2

24.9_0603_1%

AGPREF

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

AGP_ST0
AGP_ST1
AGP_ST2

+CPU_CORE

BROOKDALE(MCH-M)
R252

+VS_HUBREF

14 AGP_ST[0..2]

R238

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

GRCOMP

R260
150_1%

HRCOMP0
HRCOMP1

M7
R8
Y8
AB11
AB17

AGP_SBA[0..7]
AH28
AH27
AG28
AG27
AE28
AE27
AE24
AE25

66IN

+V_MCH_GTLREF
HVREF0
HVREF1
HVREF2
HVREF3
HVREF4

+1.8VS

2
36.5_1%

1
@8.2K

AGP_ST1
AGP_ST2

AGP_SBSTB#
1
@8.2K

2
R212
2
R214

*
*

R_C

C373
@470PF

R291
@56.2_1%

+VS_HUBREF
R286
0
R289
301_1%

R_D
AGP_ST1
0=533Mhz
1=400Mhz

1
8.2K

AA7
AD13

1
R270

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

HLRCOMP

AD4
AE6
AE11
AC15
AD3
AE7
AD11
AC16

P27
P26

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

DBI#0
DBI#1
DBI#2
DBI#3

HLRCOMP
HI_REF

HUB_PSTRB 16
HUB_PSTRB# 16

H_SWNG0
H_SWNG1

C290
.01UF

AD5
AG4
AH9
AD15

N25
N24

H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3

G_C/BE#0
G_C/BE#1
G_C/BE#2
G_C/BE#3

HI_STB
HI_STB#

HUB_PD[0..10] 16

HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10

BCLK
BCLK#

V25
V23
Y25
AA23

P25
P24
N27
P23
M26
M25
L28
L27
M27
N28
M24

J8
K8

AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3

HI_0
HI_1
HI_2
HI_3
HI_4
HI_5
HI_6
HI_7
HI_8
HI_9
HI_10

1
8.2K

1 2

H_DBI#[0..3]

+CPU_CORE

R254
301_1%

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

H_DBI#[0..3]

CLK_GHT
CLK_GHT#

CLK_GHT
CLK_GHT#

U6
T7
R7
U5
U2

G_AD0
G_AD1
G_AD2
G_AD3
G_AD4
G_AD5
G_AD6
G_AD7
G_AD8
G_AD9
G_AD10
G_AD11
G_AD12
G_AD13
G_AD14
G_AD15
G_AD16
G_AD17
G_AD18
G_AD19
G_AD20
G_AD21
G_AD22
G_AD23
G_AD24
G_AD25
G_AD26
G_AD27
G_AD28
G_AD29
G_AD30
G_AD31

C368
.01UF

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

RS#0
RS#1
RS#2

R27
R28
T25
R25
T26
T27
U27
U28
V26
V27
T23
U23
T24
U24
U25
V24
Y27
Y26
AA28
AB25
AB27
AA27
AB26
Y23
AB23
AA24
AA25
AB24
AC25
AC24
AC22
AD24

13
13

HREQ#[0..4]

W2
W7
W6

14 AGP_C/BE#[0..3]

HUB_PD[0..10]

U5B
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

H_RS#0
H_RS#1
H_RS#2
HREQ#[0..4]

AGP_AD[0..31]

5
5
5
4

CPURST#
HTRDY#
DEFER#
BPRI#
HLOCK#
RSTIN#
TESTIN#
DBSY#
DRDY#
HIT#
HITM#
BREQ#0
ADS#
BNR#

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

HOST

H_DBSY#
H_DRDY#
HIT#
HITM#
HBR0#
HADS#
HBNR#

HADSTB#0
HADSTB#1

AE17
U7
Y4
Y7
W5
J27
H26
V5
V4
Y5
Y3
V7
V3
W3

5
H_RESET#
5
H_TRDY#
4
HDEFER#
2
4
HBPRI#
4
HLOCK#
14,16,19,20,21,22,23,24,27,28,34 PCIRST#
5
5
4
4
4
4
4

R5
N6

AA2
AB5
AA5
AB3
AB4
AC5
AA3
AA6
AE3
AB7
AD7
AC7
AC6
AC3
AC8
AE2
AG5
AG2
AE8
AF6
AH2
AF3
AG3
AE5
AH7
AH3
AF4
AG8
AG7
AG6
AF8
AH5
AC11
AC12
AE9
AC9
AE10
AD9
AG9
AC10
AE12
AF10
AG11
AG10
AH11
AG12
AE13
AF12
AG13
AH13
AC14
AF14
AG14
AE14
AG15
AG16
AG17
AH15
AC17
AF16
AE15
AH17
AD17
AE16

H_ADSTB#0
H_ADSTB#1

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

AGP

5
5

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

T4
T5
T3
U3
R3
P7
R2
P4
R6
P5
P3
N2
N7
N3
K4
M4
M3
L3
L5
K3
J2
M5
J3
L2
H4
N5
G2
M6
L7

HUB

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

14 AGP_AD[0..31]

U5A

HA#[3..31]

HA#[3..31]

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

Size

TRANSFERRED FROM THE CUSTODY OF THE COMPE

Document Number

Rev
2A

401207
Date:
A

, 18, 2004

Sheet
E

of

83

U5D
U5C

VCC1_8_0
VCC1_8_1
VCC1_8_2
VCC1_8_3
VCC1_8_4

L29
N26
L25
M22
N23

VCCGA1
VCCHA1

T17
T13

VCC_MCH_PLL1
VCC_MCH_PLL0

VSSGA2
VSSHA2

U17
U13

VSS_MCH_PLL1
VSS_MCH_PLL0

+1.5VS

L34

L33
4.7UH_30mA
2

4.7UH_30mA

"Trace A"

"Trace A"
AA4
AA8
AA29
AB6
AB9
AB10
AB12
AB13
AB14
AB15
AB16
AB19
AB22
AC1
AC4
AC18
AC20
AC21
AC23
AC26
AD6
AD8
AD10
AD12
AD14
AD16
AD19
AD22
AE1
AE4
AE18
AE20
AE29
AF5
AF7
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF25
AG1
AG18
AG20
AG22
AH19
AH21
AH23
AJ3
AJ5
AJ7
AJ9
AJ11
AJ13
AJ15
AJ17
AJ27

C310
33UF_D2_16V

C309
33UF_D2_16V

"Trace A"

Layout note :
Trace width 5mil ; Spacing
10mil
Trace A to ball U7/T13 or
U7/T7 =1.5" Max

10 DDR_CB[0..7]

DDR_SDQ0
DDR_SDQ1
DDR_SDQ2
DDR_SDQ3
DDR_SDQ4
DDR_SDQ5
DDR_SDQ6
DDR_SDQ7
DDR_SDQ8
DDR_SDQ9
DDR_SDQ10
DDR_SDQ11
DDR_SDQ12
DDR_SDQ13
DDR_SDQ14
DDR_SDQ15
DDR_SDQ16
DDR_SDQ17
DDR_SDQ18
DDR_SDQ19
DDR_SDQ20
DDR_SDQ21
DDR_SDQ22
DDR_SDQ23
DDR_SDQ24
DDR_SDQ25
DDR_SDQ26
DDR_SDQ27
DDR_SDQ28
DDR_SDQ29
DDR_SDQ30
DDR_SDQ31
DDR_SDQ32
DDR_SDQ33
DDR_SDQ34
DDR_SDQ35
DDR_SDQ36
DDR_SDQ37
DDR_SDQ38
DDR_SDQ39
DDR_SDQ40
DDR_SDQ41
DDR_SDQ42
DDR_SDQ43
DDR_SDQ44
DDR_SDQ45
DDR_SDQ46
DDR_SDQ47
DDR_SDQ48
DDR_SDQ49
DDR_SDQ50
DDR_SDQ51
DDR_SDQ52
DDR_SDQ53
DDR_SDQ54
DDR_SDQ55
DDR_SDQ56
DDR_SDQ57
DDR_SDQ58
DDR_SDQ59
DDR_SDQ60
DDR_SDQ61
DDR_SDQ62
DDR_SDQ63

G28
F27
C28
E28
H25
G27
F25
B28
E27
C27
B25
C25
B27
D27
D26
E25
D24
E23
C22
E21
C24
B23
D22
B21
C21
D20
C19
D18
C20
E19
C18
E17
E13
C12
B11
C10
B13
C13
C11
D10
E10
C9
D8
E8
E11
B9
B7
C7
C6
D6
D4
B3
E6
B5
C4
E5
C3
D3
F4
F3
B2
C2
E2
G5

SDQ0
SDQ1
SDQ2
SDQ3
SDQ4
SDQ5
SDQ6
SDQ7
SDQ8
SDQ9
SDQ10
SDQ11
SDQ12
SDQ13
SDQ14
SDQ15
SDQ16
SDQ17
SDQ18
SDQ19
SDQ20
SDQ21
SDQ22
SDQ23
SDQ24
SDQ25
SDQ26
SDQ27
SDQ28
SDQ29
SDQ30
SDQ31
SDQ32
SDQ33
SDQ34
SDQ35
SDQ36
SDQ37
SDQ38
SDQ39
SDQ40
SDQ41
SDQ42
SDQ43
SDQ44
SDQ45
SDQ46
SDQ47
SDQ48
SDQ49
SDQ50
SDQ51
SDQ52
SDQ53
SDQ54
SDQ55
SDQ56
SDQ57
SDQ58
SDQ59
SDQ60
SDQ61
SDQ62
SDQ63

DDR_CB0
DDR_CB1
DDR_CB2
DDR_CB3
DDR_CB4
DDR_CB5
DDR_CB6
DDR_CB7

C16
D16
B15
C14
B17
C17
C15
D14

SDQ64/CB0
SDQ65/CB1
SDQ66/CB2
SDQ67/CB3
SDQ68/CB4
SDQ69/CB5
SDQ70/CB6
SDQ71/CB7

J21
J9

SDREF0
SDREF1

DDR_CB[0..7]

SCK0
SCK#0
SCK1
SCK#1
SCK2
SCK#2

E14
F15
J24
G25
G6
G7

DDR_CLK0 10
DDR_CLK0# 10
DDR_CLK1 10
DDR_CLK1# 10
DDR_CLK2 10
DDR_CLK2# 10

SCK3
SCK#3
SCK4
SCK#4
SCK5
SCK#5

G15
G14
E24
G24
H5
F5

DDR_CLK3 11
DDR_CLK3# 11
DDR_CLK4 11
DDR_CLK4# 11
DDR_CLK5 11
DDR_CLK5# 11

SCK6
SCK#6
SCK7
SCK#7
SCK8
SCK#8

K25
J25
G17
G16
H7
H6

SCS#0
SCS#1
SCS#2
SCS#3
SCS#4
SCS#5

E9
F7
F9
E7
G9
G10

DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3

SDQS0
SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDQS8

F26
C26
C23
B19
D12
C8
C5
E3
E15

DDR_SDQS0
DDR_SDQS1
DDR_SDQS2
DDR_SDQS3
DDR_SDQS4
DDR_SDQS5
DDR_SDQS6
DDR_SDQS7
DDR_SDQS8

SMA0/CS#11
SMA1/CS#10
SMA2/CS#6
SMA3/CS#9
SMA4/CS#5
SMA5/CS#8
SMA6/CS#7
SMA7/CS#4
SMA8/CS#3
SMA9/CS#0
SMA10
SMA11/CS#2
SMA12/CS#1

E12
F17
E16
G18
G19
E18
F19
G21
G20
F21
F13
E20
G22

DDR_SMA0
DDR_SMA1
DDR_SMA2
DDR_SMA3
DDR_SMA4
DDR_SMA5
DDR_SMA6
DDR_SMA7
DDR_SMA8
DDR_SMA9
DDR_SMA10
DDR_SMA11
DDR_SMA12

SBS0
SBS1

G12
G13

DDR_SBS0
DDR_SBS1

SCKE0
SCKE1
SCKE2
SCKE3
SCKE4
SCKE5

G23
E22
H23
F23
J23
K23

DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3

DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3

10,11
10,11
11
11

DDR_SDQS0
DDR_SDQS1
DDR_SDQS2
DDR_SDQS3
DDR_SDQS4
DDR_SDQS5
DDR_SDQS6
DDR_SDQS7
DDR_SDQS8

10
10
10
10
10
10
10
10
10

DDR_SMA[0..12]

SMRCOMP
RCVENIN#
RCVENOUT#

J28
G3
H3

SSI_ST

H27

SRAS#
SWE#
SCAS#

F11
G11
G8

NC0
NC1

C346
.1UF_0402_X5R

DDR_SMA[0..12] 10,11
2

DDR_SBS0 10,11
DDR_SBS1 10,11
DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3
R75
2

SM_RCOMP
R CVIN#
RCVOUT# 2
R283

10,11
10,11
11
11

30.1_1%
1

1
0_0402

Layout note
Place R637
closely pinJ28

+1.25VS

C69

.1UF_0402_X5R

C358

@47PF

R_J
DDR_SRAS#
DDR_SWE#
DDR_SCAS#

DDR_SRAS# 10,11
DDR_SWE# 10,11
DDR_SCAS# 10,11

AD26
AD27

Layout note
Place R_J closely Ball
H3<40mil,Ball H3 to G3 trace
must
routing 1"

+SDREF

VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141

Murata LQG21N4R7K10

+1.8VS

VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82

N14
N16
P13
P15
P17
R14
R16
T15
U14
U16

L1
L4
L6
L8
L22
L26
N1
N4
N8
N13
N15
N17
N29
P6
P8
P14
P16
R1
R4
R13
R15
R17
R26
T6
T8
T14
T16
T22
U1
U4
U15
U29
V6
V8
V22
W1
W4
W8
W26
Y6
Y22
AA1

VCC1_5_16
VCC1_5_17
VCC1_5_18
VCC1_5_19
VCC1_5_20
VCC1_5_21
VCC1_5_22
VCC1_5_23
VCC1_5_24
VCC1_5_25

DDR_SDQ[0..63]

10 DDR_SDQ[0..63]

+1.5VS

"Trace A"

POWER/GND

VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38

R22
R29
U22
U26
W22
W29
AA22
AA26
AB21
AC29
AD21
AD23
AE26
AF23
AG29
AJ25

MEMORY

A5
A9
A13
A17
A21
A25
C1
C29
D7
D11
D15
D19
D23
D25
F6
F10
F14
F18
F22
G1
G4
G29
H8
H10
H12
H14
H16
H18
H20
H22
H24
K22
K24
K26
L23
K6
J5
J7

VCC1_5_0
VCC1_5_1
VCC1_5_2
VCC1_5_3
VCC1_5_4
VCC1_5_5
VCC1_5_6
VCC1_5_7
VCC1_5_8
VCC1_5_9
VCC1_5_10
VCC1_5_11
VCC1_5_12
VCC1_5_13
VCC1_5_14
VCC1_5_15

+2.5V

VTT_0
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18

M8
U8
AA9
AB8
AB18
AB20
AC19
AD18
AD20
AE19
AE21
AF18
AF20
AG19
AG21
AG23
AJ19
AJ21
AJ23

+CPU_CORE

BROOKDALE(MCH-M)

Layout note
Please closely pinJ21 and J9

BROOKDALE(MCH-M)
4

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331 TRANSFERRED

Size

Document Number

Rev
2A

401207
Date:
A

FROM THE CUSTODY OF THE COMPE

, 18, 2004

Sheet
E

of

83

Layout note : DDR Memory interface

Processor system bus

Layout note :

Distribute as close as possible

to MCH Processor Quadrant.(between VCCSM and VSS pin)

Distribute as close as possible

to MCH Processor Quadrant.(between VTTFSB and VSS pin)

+CPU_CORE

+2.5V

C369
.1UF_0402_X5R

C377
22UF_10V_1206

C347
22UF_10V_1206

1
C353
.1UF_0402_X5R

C375
.1UF_0402_X5R

1
C365
.1UF_0402_X5R

C374
.1UF_0402_X5R

1
C362
.1UF_0402_X5R

C247
.1UF_0402_X5R

1
C251
.1UF_0402_X5R

1
C270
.1UF_0402_X5R

1
C283
.1UF_0402_X5R

C284
.1UF_0402_X5R

+2.5V

1
C364
.1UF_0402_X5R

C367
.1UF_0402_X5R

C343
.1UF_0402_X5R

1
C366
.1UF_0402_X5R

C250
.1UF_0402_X5R

1
C256
.1UF_0402_X5R

1
C266
.1UF_0402_X5R

1
C261
.1UF_0402_X5R

1
C265
.1UF_0402_X5R

+CPU_CORE

C363
.1UF_0402_X5R

+2.5V

1
C360
.1UF_0402_X5R

1
C352
.1UF_0402_X5R

1
C349
.1UF_0402_X5R

1
C288
10UF_6.3V_1206_X5R

C345
.1UF_0402_X5R
C

C289
10UF_6.3V_1206_X5R

C245
10UF_6.3V_1206_X5R

+CPU_CORE

+2.5V

C378
150UF_D2_6.3V

Layout note : AGP/CORE

Distribute as close as possible
to MCH Processor Quadrant.(between VCCAGP/VCCCORE
and VSS pin)

1
C291
.1UF_0402_X5R

1
C285
.1UF_0402_X5R

1
C268
.1UF_0402_X5R

1
C304
.1UF_0402_X5R

1
C303
.1UF_0402_X5R

+1.5VS

C312
.1UF_0402_X5R

1
C334
10UF_6.3V_1206_X5R

C244
150UF_D2_6.3V

C314
10UF_6.3V_1206_X5R

+1.5VS

Layout note : Hub-Link

Distribute as close as possible
to MCH Processor Quadrant.(between VCCHL and VSS pin)

C328
.1UF_0402_X5R

1
C324
.1UF_0402_X5R

1
2

C58
10UF_6.3V_1206_X5R

+1.8VS

C333
.1UF_0402_X5R

Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

Size

TRANSFERRED FROM THE CUSTODY OF THE

Document Number

Rev
2A

401207
Date:
5

, 18, 2004

Sheet
1

of

83

DDR_SDQ0
DDR_SDQ6

DDR_SDQ3
DDR_SDQ2

RP47
1
2
RP46
1
2

4P2R_22
DDR_DQ0
4
DDR_DQ6
3
4P2R_22
DDR_DQ3
4
DDR_DQ2
3

RP45
1
2

4P2R_22
DDR_DQ8
4
DDR_DQ12
3

RP44
1
2

4P2R_22
DDR_DQS1
4
DDR_DQ14
3

DDR_SDQ19
DDR_SDQ17

RP43
1
2

4P2R_22
DDR_DQ19
4
DDR_DQ17
3

DDR_SDQS2
DDR_SDQ21

RP42
1
2

4P2R_22
DDR_DQS2
4
DDR_DQ21
3

DDR_SDQ23
DDR_SDQ31

RP41
1
2

4P2R_22
DDR_DQ23
4
DDR_DQ31
3

RP40
1
2

4P2R_22
DDR_DQ27
4
DDR_DQ25
3

DDR_SDQ8
DDR_SDQ12
1

DDR_SDQS1
DDR_SDQ14

DDR_SDQ27
DDR_SDQ25

DDR_SDQ26
DDR_SDQS3

RP39
1
2

4P2R_22
DDR_DQ26
4
DDR_DQS3
3

DDR_CB4
DDR_CB5

RP38
1
2

4P2R_22
DDR_F_CB4
4
DDR_F_CB5
3

RP37
1
2

4P2R_22
DDR_F_CB6
4
DDR_F_CB3
3

DDR_CB6
DDR_CB3

DDR_SDQ4
DDR_SDQ5

DDR_SDQ1
DDR_SDQS0

DDR_SMA8
DDR_SMA6

DDR_SMA3
DDR_SMA1

RP48
1
2

4P2R_10
DDR_F_SMA12
4
DDR_F_SMA9
3

RP36
1
2

4P2R_10
DDR_F_SMA8
4
DDR_F_SMA6
3

RP35
1
2

RP34
DDR_SBS0 1
DDR_SWE# 2

8,11 DDR_SBS0
8,11 DDR_SWE#

4P2R_10
DDR_F_SMA3
4
DDR_F_SMA1
3
4P2R_10
4 DDR_F_SBS0
3 DDR_F_SWE#

RP33
1
2

8,11 DDR_SCAS#
8,11 DDR_SRAS#
4P2R_22
DDR_DQ36
4
DDR_DQ37
3

DDR_SDQS4
DDR_SDQ33

RP32
1
2

4P2R_22
DDR_DQS4
4
DDR_DQ33
3

DDR_SDQ34
DDR_SDQ44

RP31
1
2

4P2R_22
DDR_DQ34
4
DDR_DQ44
3

DDR_SDQ41
DDR_SDQ43

RP30
1
2

4P2R_22
DDR_DQ41
4
DDR_DQ43
3

DDR_SDQ47
DDR_SDQ46

RP29
1
2

4P2R_22
DDR_DQ47
4
DDR_DQ46
3

RP28
1
2

4P2R_22
DDR_DQ48
4
DDR_DQ49
3

RP27
1
2

4P2R_22
DDR_DQ50
4
DDR_DQ54
3

DDR_SDQ57
DDR_SDQ60

RP26
1
2

4P2R_22
DDR_DQ57
4
DDR_DQ60
3

DDR_SDQ62
DDR_SDQ59

RP49
1
2

4P2R_22
DDR_DQ62
4
DDR_DQ59
3

DDR_SDQ36
DDR_SDQ37

DDR_SDQ48
DDR_SDQ49

DDR_SDQ50
DDR_SDQ54
4

RP74
1
2

4P2R_22
DDR_DQ7
4
DDR_DQ15
3

DDR_SDQ9
DDR_SDQ13

RP72
1
2

4P2R_22
DDR_DQ9
4
DDR_DQ13
3

DDR_SDQ11
DDR_SDQ10

RP71
1
2

4P2R_22
DDR_DQ11
4
DDR_DQ10
3

DDR_SDQ20
DDR_SDQ16

RP70
1
2

4P2R_22
DDR_DQ20
4
DDR_DQ16
3

DDR_SDQ22
DDR_SDQ18

RP69
1
2

4P2R_22
DDR_DQ22
4
DDR_DQ18
3

DDR_SDQ29
DDR_SDQ24

RP68
1
2

4P2R_22
DDR_DQ29
4
DDR_DQ24
3

DDR_SDQ28
DDR_SDQ30

RP67
1
2

4P2R_22
DDR_DQ28
4
DDR_DQ30
3

DDR_SDQS8
DDR_CB7

RP66
1
2

4P2R_22
DDR_DQS8
4
DDR_F_CB7
3

DDR_CB1
DDR_CB0

RP65
1
2

4P2R_22
DDR_F_CB1
4
DDR_F_CB0
3

DDR_SMA7
DDR_SMA11

4P2R_22
DDR_F_CB2
4
3

RP63
1
2

4P2R_10
4 DDR_F_SMA7
3 DDR_F_SMA11

DDR_SMA4
DDR_SMA5

RP62
1
2

4P2R_10
4 DDR_F_SMA4
3 DDR_F_SMA5

DDR_SMA10
DDR_SMA0

RP61
1
2

4P2R_10
4 DDR_F_SMA10
3 DDR_F_SMA0

RP60
1
2

4P2R_10
4 DDR_F_SCAS#
3 DDR_F_SRAS#

DDR_SDQ32
DDR_SDQ39

RP59
1
2

4P2R_22
DDR_DQ32
4
DDR_DQ39
3

DDR_SDQ35
DDR_SDQ38

RP58
1
2

4P2R_22
DDR_DQ35
4
DDR_DQ38
3

DDR_SDQ42
DDR_SDQS5

RP56
1
2

4P2R_22
DDR_DQ42
4
DDR_DQS5
3

RP57
1
2

4P2R_22
DDR_DQ40
4
DDR_DQ45
3

DDR_SCAS#
DDR_SRAS#

DDR_SDQ40
DDR_SDQ45

DDR_SDQ55
DDR_SDQ52

RP55
1
2

4P2R_22
DDR_DQ55
4
DDR_DQ52
3

DDR_SDQS6
DDR_SDQ53

RP54
1
2

4P2R_22
DDR_DQS6
4
DDR_DQ53
3

DDR_SDQ51
DDR_SDQ56

RP53
1
2

4P2R_22
DDR_DQ51
4
DDR_DQ56
3

DDR_SDQ61
DDR_SDQS7

RP52
1
2

4P2R_22
DDR_DQ61
4
DDR_DQS7
3

DDR_SDQ58
DDR_SDQ63

RP51
1
2

4P2R_22
DDR_DQ58
4
DDR_DQ63
3

DDR_DQ[0..63]
+SDREF
DDR_F_CB[0..7]

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

DDR_DQ4
DDR_DQ0
DDR_DQS0
DDR_DQ3
DDR_DQ7
DDR_DQ15
DDR_DQ8
DDR_DQS1
DDR_DQ9
DDR_DQ14
8
8

DDR_CLK1
DDR_CLK1#

DDR_DQ19
DDR_DQ20

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_DQS2
DDR_DQ22
DDR_DQ23
DDR_DQ29
DDR_DQ27
DDR_DQS3
DDR_DQ28
DDR_DQ30
DDR_F_CB4
DDR_F_CB6
DDR_DQS8
DDR_F_CB1
DDR_F_CB3

8
8

DDR_CLK0
DDR_CLK0#
DDR_CKE1

8,11 DDR_CKE1
RP64
1
2

+2.5V

JP26

4P2R_22
DDR_DQ1
4
DDR_DQS0
3

RP73
1
2

+2.5V

4P2R_22
DDR_DQ4
4
DDR_DQ5
3

DDR_SDQ7
DDR_SDQ15

DDR_CB2
DDR_SMA12
DDR_SMA9

RP75
1
2

DDR_F_SMA12
DDR_F_SMA9
DDR_F_SMA7
DDR_F_SMA5
DDR_F_SMA3
DDR_F_SMA1

8,11 DDR_SCS#0

DDR_F_SMA10
DDR_F_SBS0
DDR_F_SWE#
DDR_SCS#0
DDR_DQ36
DDR_DQ32
DDR_DQS4
DDR_DQ35
DDR_DQ34
DDR_DQ42
DDR_DQ41
DDR_DQS5
DDR_DQ40
DDR_DQ47

DDR_DQ55
DDR_DQ48
DDR_DQS6
DDR_DQ50
DDR_DQ51
DDR_DQ57
DDR_DQ60
DDR_DQS7
DDR_DQ62
DDR_DQ58
11,13 DIMM_SMDATA
11,13 DIMM_SMCLK
+3VS

VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID

VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS#
CAS#
S1#
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_DQS[0..8]
DDR_DQ5
DDR_DQ6

C475

DDR_SMA[0..12]

.1UF

DDR_SDQ[0..63]

DDR_DQ1

DDR_CB[0..7]

DDR_DQ2
DDR_DQ12

DDR_SDQS[0..8]

DDR_DQ[0..63] 11
DDR_F_CB[0..7] 11
DDR_DQS[0..8] 11
DDR_SMA[0..12] 8,11
DDR_SDQ[0..63] 8
DDR_CB[0..7] 8
DDR_SDQS[0..8] 8
1

DDR_DQ13
DDR_DQ11
DDR_DQ10

DDR_DQ17
DDR_DQ16
DDR_DQ21
DDR_DQ18
DDR_DQ31
DDR_DQ24
DDR_DQ25
DDR_DQ26
DDR_F_CB5
DDR_F_CB7
DDR_F_CB0
2

DDR_F_CB2

DDR_CKE0

DDR_CKE0 8,11

DDR_F_SMA11
DDR_F_SMA8
DDR_F_SMA6
DDR_F_SMA4
DDR_F_SMA2
DDR_F_SMA0
DDR_F_SBS1
DDR_F_SRAS#
DDR_F_SCAS#

2
R157

1
10

DDR_SMA2

2
R158

1
10

DDR_SBS1

DDR_SBS1 8,11

DDR_SCS#1 8,11
DDR_DQ37
DDR_DQ39
DDR_DQ33
DDR_DQ38
DDR_DQ44
DDR_DQ43
3

DDR_DQ45
DDR_DQ46
DDR_CLK2# 8
DDR_CLK2 8
DDR_DQ52
DDR_DQ49
DDR_DQ53
DDR_DQ54
DDR_DQ56
DDR_DQ61
DDR_DQ59
DDR_DQ63

DDR-SODIMM_200_REVERSE
4

DIMM0

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

Size

TRANSFERRED FROM THE CUSTODY OF THE COMPE

Document Number

Rev
2A

401207
, 18, 2004

Date:
A

Sheet

10
H

of

83

DDR_F_CB[0..7]

10 DDR_F_CB[0..7]

+2.5V

DDR_DQS[0..8]

10 DDR_DQS[0..8]

+SDREF
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

DDR_DQ5
DDR_DQ6
+1.25VS

8,10 DDR_CKE0
8,10 DDR_CKE1

+1.25VS

DDR_DQ4
DDR_DQ0

RP134
1
2

4P2R_56
4
3

RP107
4
3

4P2R_56
DDR_DQ5
1
DDR_DQ6
2

DDR_DQ3
DDR_DQ7

RP133
1
2

4P2R_56
4
3

RP106
4
3

4P2R_56
DDR_DQS0
1
DDR_DQ1
2

8,10 DDR_SBS1
8,10 DDR_SRAS#

8,10 DDR_SCS#0
8,10 DDR_SCS#1

DDR_DQS0
DDR_DQ1

DDR_SBS1
DDR_SRAS#

RP119
1
2

4P2R_56
4
3

RP92
4
3

4P2R_56
DDR_SWE#
1
DDR_SBS0
2

DDR_SCS#0
DDR_SCS#1

RP91
1
2

4P2R_56
4
3

RP117
4
3

4P2R_56
DDR_SCS#2
1
DDR_DQ37
2

DDR_DQ15
DDR_DQ8

RP132
1
2

4P2R_56
4
3

RP105
4
3

4P2R_56
DDR_DQ2
1
DDR_DQ12
2

4P2R_56
4
3

RP116
4
3

4P2R_56
DDR_DQ39
1
DDR_DQS4
2

DDR_DQ9
DDR_DQ14

RP131
1
2

4P2R_56
4
3

RP104
4
3

4P2R_56
DDR_DQ13
1
DDR_DQS1
2

DDR_DQ36
DDR_DQ32

RP90
1
2

4P2R_56
4
3

RP115
4
3

4P2R_56
DDR_DQ33
1
DDR_DQ38
2

DDR_DQ19
DDR_DQ20

RP129
1
2

4P2R_56
4
3

RP130
4
3

4P2R_56
DDR_DQ11
1
DDR_DQ10
2

RP89
DDR_DQ35
1
DDR_DQ34
2

4P2R_56
4
3

RP114
4
3

4P2R_56
DDR_DQ44
1
DDR_DQ43
2

DDR_DQ22
DDR_DQ23

RP101
1
2

4P2R_56
4
3

RP103
4
3

4P2R_56
DDR_DQ17
1
DDR_DQ16
2

DDR_DQ42
DDR_DQ41

RP88
1
2

4P2R_56
4
3

4
3

DDR_DQ29
DDR_DQ27

RP100
1
2

4P2R_56
4
3

RP102
4
3

4P2R_56
DDR_DQS2
1
DDR_DQ21
2

DDR_DQ40
DDR_DQ47

RP87
1
2

4P2R_56
4
3

RP86
4
3

4P2R_56
DDR_DQ46
1
DDR_DQ52
2

DDR_DQ28
DDR_DQ30

RP99
1
2

4P2R_56
4
3

RP128
4
3

4P2R_56
DDR_DQ18
1
DDR_DQ31
2

RP85
DDR_DQ55
1
DDR_DQ48
2

4P2R_56
4
3

RP112
4
3

4P2R_56
DDR_DQ49
1
DDR_DQS6
2

DDR_F_CB4
DDR_F_CB6

RP98
1
2

4P2R_56
4
3

RP127
4
3

4P2R_56
DDR_DQ24
1
DDR_DQS3
2

DDR_DQ50
DDR_DQ51

RP84
1
2

4P2R_56
4
3

RP111
4
3

4P2R_56
DDR_DQ53
1
DDR_DQ54
2

DDR_F_CB1
DDR_F_CB3

RP97
1
2

4P2R_56
4
3

RP126
4
3

4P2R_56
DDR_DQ25
1
DDR_DQ26
2

DDR_DQ57
DDR_DQ60

RP83
1
2

4P2R_56
4
3

RP110
4
3

4P2R_56
DDR_DQ56
1
DDR_DQ61
2

DDR_CKE0
DDR_CKE1

RP123
1
2

4P2R_56
4
3

RP125
4
3

4P2R_56
DDR_F_CB5
1
DDR_F_CB7
2

DDR_DQ62
DDR_DQ58

RP82
1
2

4P2R_56
4
3

RP109
4
3

4P2R_56
DDR_DQS7
1
DDR_DQ59
2

DDR_CKE2
DDR_CKE3

RP96
1
2

4P2R_56
4
3

RP124
4
3

4P2R_56
DDR_DQS8
1
DDR_F_CB0
2

DDR_DQ63

RP108
1
2

4P2R_56
4
3

DDR_SMA11
DDR_SMA8

RP122
1
2

4P2R_56
4
3

RP95
4
3

4P2R_56
DDR_SMA12
1
DDR_F_CB2
2

DDR_SMA6
DDR_SMA4

RP121
1
2

4P2R_56
4
3

RP94
4
3

4P2R_56
DDR_SMA7
1
DDR_SMA9
2

DDR_SMA2
DDR_SMA0

RP120
1
2

4P2R_56
4
3

RP93
4
3

4P2R_56
DDR_SMA3
1
DDR_SMA5
2

1
R444
1
R159

2
56
2
56

8,10 DDR_SCAS#

DDR_SCAS#
DDR_SCS#3

RP118
1
2

RP113

DDR_SWE# 8,10
DDR_SBS0 8,10

DDR_DQ13
DDR_DQS1
DDR_DQ11
DDR_DQ10

8
8

DDR_CLK4
DDR_CLK4#

DDR_DQ17
DDR_DQ16

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_DQS2
DDR_DQ21
DDR_DQ18
DDR_DQ31
DDR_DQ24
DDR_DQS3

4P2R_56
1
2

DDR_DQ2
DDR_DQ12

DDR_DQS5
DDR_DQ45

DDR_DQ25
DDR_DQ26
DDR_F_CB5
DDR_F_CB7
DDR_DQS8
DDR_F_CB0
DDR_F_CB2

8
8

DDR_CLK3
DDR_CLK3#

DDR_CKE3

DDR_CKE3
DDR_SMA12
DDR_SMA9
DDR_SMA7
DDR_SMA5
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SBS0
DDR_SWE#

DDR_SCS#2
DDR_DQ37
DDR_DQ39
DDR_DQS4
DDR_DQ33
DDR_DQ38
DDR_DQ44

DDR_DQ43
DDR_DQS5
DDR_DQ45
DDR_DQ46

DDR_SMA1

DDR_DQ52
DDR_DQ49

DDR_SMA10
DDR_DQS6
DDR_DQ53
DDR_DQ54
DDR_DQ56
DDR_DQ61
DDR_DQS7
DDR_DQ59
DDR_DQ63

*
For EC Tools

10,13 DIMM_SMDATA
10,13 DIMM_SMCLK

EMI Clip PAD for Memory Door

PAD4

PAD5
1

+5VALW
JP22

EC_URXD 32
EC_UTXD 32
EN_WOL# 27,32

+3VS

PAD6
1

PAD-2.5X3

PAD-2.5X3

PAD7

PAD8

PAD9

1
PAD-2.5X3

1
PAD-2.5X3

DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID

VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS#
CAS#
S1#
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

DDR_DQ4
DDR_DQ0

C518
.1UF

DDR_DQ3
1

DDR_DQ7
DDR_DQ15
DDR_DQ8
DDR_DQ9
DDR_DQ14

DDR_DQ19
DDR_DQ20

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_DQ22
DDR_DQ23
DDR_DQ29
DDR_DQ27
DDR_DQ28
DDR_DQ30
DDR_F_CB4
DDR_F_CB6
2

DDR_F_CB1
DDR_F_CB3

DDR_CKE2

DDR_CKE2 8

DDR_SMA11
DDR_SMA8
DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0
DDR_SBS1
DDR_SRAS#
DDR_SCAS#
DDR_SCS#3

DDR_SCS#3 8

DDR_DQ36
DDR_DQ32
DDR_DQ35
DDR_DQ34
DDR_DQ42

DDR_DQ41
DDR_DQ40
DDR_DQ47
DDR_CLK5# 8
DDR_CLK5 8
DDR_DQ55
DDR_DQ48
DDR_DQ50
DDR_DQ51
DDR_DQ57
DDR_DQ60
DDR_DQ62
DDR_DQ58
+3VS

PAD-2.5X3

VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS

DDR_SMA[0..12]

JP27

8,10 DDR_SMA[0..12]

EC_URXD
EC_UTXD
EC_USCLK

+2.5V

DDR_DQ[0..63]

10 DDR_DQ[0..63]

1
2
3
4
5
6

DDR-SODIMM_200_NORMAL

DIMM1
1

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

PAD-2.5X3
Size

TRANSFERRED FROM THE CUSTODY OF THE COMPE

Document Number

@ FCI SFW06R-2STE1

Rev
2A

401207
Date:
A

, 18, 2004

Sheet
E

11

of

83

Layout note :
Distribute as close as possible
to DDR-SODIMM.

1
2

1
C154
.1UF_0402_X5R

***

C161
@.1UF_0402_X5R

C112
+
150UF_D2_6.3V

C159
150UF_D2_6.3V

+
2

C160
@.1UF_0402_X5R

***

1
C162
.1UF_0402_X5R

1
C152
.1UF_0402_X5R

1
C157
.1UF_0402_X5R

1
C158
.1UF_0402_X5R

1
C135
.1UF_0402_X5R

C133
.1UF_0402_X5R

+2.5V

+2.5V

C163
.1UF_0402_X5R

C156
.1UF_0402_X5R

1
C132
.1UF_0402_X5R

C155
.1UF_0402_X5R

1
C151
.1UF_0402_X5R

C134
.1UF_0402_X5R

1
C150
.1UF_0402_X5R

+2.5V

Layout note :
Place one cap close to every 2 pull up resistors termination to
+1.25V

1
C546
.1UF_0402_X5R

1
C545
.1UF_0402_X5R

1
C544
.1UF_0402_X5R

1
C543
.1UF_0402_X5R

1
C542
.1UF_0402_X5R

1
C541
.1UF_0402_X5R

1
C540
.1UF_0402_X5R

1
C539
.1UF_0402_X5R

1
C538
.1UF_0402_X5R

+1.25VS

C547
.1UF_0402_X5R

1
C556
.1UF_0402_X5R

1
C555
.1UF_0402_X5R

1
C554
.1UF_0402_X5R

1
C553
.1UF_0402_X5R

1
C552
.1UF_0402_X5R

1
C551
.1UF_0402_X5R

1
C550
.1UF_0402_X5R

1
C549
.1UF_0402_X5R

1
C548
.1UF_0402_X5R

+1.25VS

C557
.1UF_0402_X5R

1
C566
.1UF_0402_X5R

1
C565
.1UF_0402_X5R

1
C564
.1UF_0402_X5R

1
C563
.1UF_0402_X5R

1
C562
.1UF_0402_X5R

1
C561
.1UF_0402_X5R

1
C560
.1UF_0402_X5R

1
C559
.1UF_0402_X5R

1
C558
.1UF_0402_X5R

+1.25VS

C567
.1UF_0402_X5R
3

1
C576
.1UF_0402_X5R

1
C575
.1UF_0402_X5R

1
C574
.1UF_0402_X5R

1
C573
.1UF_0402_X5R

1
C572
.1UF_0402_X5R

1
C571
.1UF_0402_X5R

1
C570
.1UF_0402_X5R

1
C569
.1UF_0402_X5R

1
C568
.1UF_0402_X5R

+1.25VS

C577
.1UF_0402_X5R

1
C586
.1UF_0402_X5R

1
C585
.1UF_0402_X5R

1
C584
.1UF_0402_X5R

1
C583
.1UF_0402_X5R

1
C582
.1UF_0402_X5R

1
C581
.1UF_0402_X5R

1
C580
.1UF_0402_X5R

1
C579
.1UF_0402_X5R

1
C578
.1UF_0402_X5R

+1.25VS

C595
.1UF_0402_X5R

+1.25VS

1
C592
.1UF_0402_X5R

1
C593
.1UF_0402_X5R

C594
.1UF_0402_X5R

C591
.1UF_0402_X5R

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331TRANSFERRED

Size

Document Number

Rev
2A

401207
Date:
A

, 18, 2004

Sheet
E

FROM THE CUSTODY OF THE COMPE

12

of

83

1
R148
1
R146
1
R108

16,32 PM_SLP_S1#
16,32 PM_SLP_S3#
16 PM_STPPCI#
16,42 PM_STPCPU#

1
R135
1
R130

+3VS
Ir ef

5.00mA

2.32mA

2
@0
2
0

DIMM_SMDATA
DIMM_SMCLK

25
34
53

VTT_PWRGD#

16

CLK_ICH14

24

CLK_SIO14

1
R144

2
475_1%
CLK_ICH48M

2
33

CLK_ICH14M

1
R101
1
R100

CLK_SIO14M

43

MULT0

2
33
2
33

29
30

SDATA
SCLK

33
35

3V66_0/DRCG
3V66_1/VCH_CLK

42

IREF

39

48MHZ_USB

38

48MHZ_DOT

56

1
2

2
1
R129

2
33

CLK_HCLK 4

1
R128

R1341

2 49.9_1%

1
R110

49.9_1%

CPU_CLKC2

44

CLK_BCLK#

CPUCLKT1

49

CLK_HT

1
R133
1
R113

2
33
2
33

CLK_HCLK# 4
CLK_GHT 7
2

49.9_1%

Place resistor near R653, R655

;Trace<=400mils
CPUCLKC1

48

CPUCLKT0

52

CPUCLKC0

51

66MHZ_IN/3V66_5

24

66MHZ_OUT2/3V66_4
66MHZ_OUT1/3V66_3
66MHZ_OUT0/3V66_2

23
22
21

PCICLK_F2
PCICLK_F1
PCICLK_F0

REF
GND_REF
GND_PCI
GND_PCI
GND_3V66
GND_3V66
GND_48MHZ
GND_IREF
GND_CPU

CLK_ICH48

CLK_BCLK

Place resistor near R645,R653

;Trace<=400mils

PWR_DWN#
PCI_STOP#
CPU_STOP#

28

Please closely pin42

16

45

SEL2
SEL1
SEL0

2
10K
2
@ 10K

1
R140

XTAL_OUT

C124
10UF_10V_1206

CLK66MCH
CLK66AGP
CLKICHHUB
CLKPCI_F2

R137
R138
R131
R127
R118
R117
R114

18
17
16
13
12
11
10

1
R116

1
R145
1
R139

2
33
2
33

1
R112

1
1
1
1
1
1
1

2
2
2
2
2
2
2

2 49.9_1%

2
33

1
R142

CLK_GHT# 7

CLK_AGP_MCH 7
CLK_AGP 14
CLK_ICHHUB 16

2
33

2
33

CLK_ICHPCI 16

33
33
33
33
33
33
33

CLK_LPC_SIO 24
CLK_PCI_LAN 20
CLK_PCI_CB 22
CLK_PCI_1394 21
CLK_PCI_SD/SM 28
CLK_LPC_EC 32
CLK_MINIPCI 27

Place caps. near

CK_Titan (U10)

4
9
15
20
31
36
41
47

W320-04

PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0

7
6
5

R1151

CLK_HT#

C115
@10PF

C119
@10PF

40
55
54

32,35 CK408_PWRGD#

MULT0

CPUCLKT2

C127
.1UF

R107
@1K

GND_CORE

27

1
10PF

R106
1K
2

R143
1K

@0

26

C118
10UF_10V_1206

2
R99

2
C101

BSEL0
1

VDD_CORE

R103
1K

H_BSEL2
H_BSEL0
2

XTAL_IN

Y1
14.318MHZ

R102
@1K

1
10PF

C123
.1UF

+3VS
L9
BLM21A601SPT
1
2

caps are internal

to CK_TITAN

+3VS

133Mhz Host CLK

2
C97

200Mhz Host CLK

+3VS_CLKVDD

+3VS

+3VS

Place Crystal within 500 mils of CK_Titan

1
L8

BLM21A601SPT

VDD_REF
VDD_PCI
VDD_PCI
VDD_3V66
VDD_3V66
VDD_48MHZ
VDD_CPU
VDD_CPU

U8

+3VS_VDD48M

100Mhz Host CLK

C108
.1UF

66Mhz Host CLK

C99
.1UF

+3VS_VDD48M

1
8
14
19
32
37
46
50

H_BSEL0
H_BSEL1

C98
.1UF

+3V_CLK = 40mils

Function

5
5

C125
.1UF

C110
.1UF

C100
.1UF

C102
.1UF

C104
22UF_10V_1206

+3VS_VDD48M = 10mils

1
2

+3V_CLK

H_BSEL0

+3V_CLK

L7
BLM21A601SPT
1
2

H_BSEL1

+3V_CLK
L6
BLM21A601SPT
1
2

+3VS

C122
@10PF

or ICS 9508-05

2
G

+5VS

DIMM_SMDATA 10,11

16,18 SMB_DATA
4

Q6

2N7002

2
G

+5VS

COMPAL ELECTRONICS, INC

3

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

DIMM_SMCLK 10,11

16,18 SMB_CLK

TRANSFERRED
SCHEMATIC, M/B LA-1331

Size
Q7

Document Number

2N7002
B

Rev
2A

401207
, 18, 2004

Date:
A

FROM THE CUSTODY OF THE COMPE

Sheet

13
H

of

83

32

KSI[0..7]

32

KSO[0..15]

KSI[0..7]
KS0[0..15]

AGP CONN.
7

JP8

AGP_SBA0
AGP_SBA2

AGP_SBSTB

13

CLK_AGP

AGP_SBA4
AGP_SBA6
CLK_AGP
AGP_AD31
AGP_AD29
AGP_AD27
AGP_AD25

AGP_ADSTB1
AGP_AD23
AGP_AD21
AGP_AD19
AGP_AD17
AGP_C/BE#2
AGP_IRDY#
AGP_DEVSEL#

7
AGP_IRDY#
7 AGP_DEVSEL#

AGP_C/BE#1
AGP_AD14
AGP_AD12
AGP_AD10
AGP_AD8
7
16

AGP_ADSTB0
C3_STAT#

AGP_AD7
AGP_AD5
AGP_AD3
AGP_AD1

+AGP_NBREF

ENBKL
ENVEE

7 AGP_C/BE#[0..3]

JP8 PIN
25,26,27,28

PCI_RST#

Int. Keyboard CONN.

JP11

ATL02/ACL00

+5VALW

NC

SQ17

NV11

+1.5V
X

KSI0
KSI2
KSI4
KSI6
KSO0
KSO2
KSO4
KSO6
KSO8
KSO10
KSO12
KSO14

PIRQA#
16,18,21,22
PCIRST# 7,16,19,20,21,22,23,24,27,28,34
AGP_GNT# 7
AGP_PIPE# 7
AGP_WBF# 7

AGP_SBA1
AGP_SBA3
AGP_SBA5
AGP_SBA7

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

+3V

VGA/B

+1.5VS

AGP_ST1

ACL10

AGP_C/BE#[0..3]

AGP_SBSTB# 7
32

NC

+3VS
+5VS
TP_DATA

AGP_C/BE#3
AGP_AD30
AGP_AD28
AGP_AD26
AGP_AD24

+12V
+3V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

KSI1
KSI3
KSI5
KSI7
KSO1
KSO3
KSO5
KSO7
KSO9
KSO11
KSO13
KSO15
+5V
TP_CLK

32
C

HEADER 2X20

AGP_ADSTB1# 7
+3.3VAUX

AGP_AD22
AGP_AD20
AGP_AD18
AGP_AD16
AGP_FRAME#

AGP_FRAME# 7
AGP_TRDY# 7
AGP_STOP# 7
AGP_PAR 7

+3VS_MDC

+5VS_MDC

AGP_RBF#

AGP_AD[0..31]
AGP_SBA[0..7]

7 AGP_SBA[0..7]

C116

C129

C117
1UF_25V_0805

1UF_25V_0805

AGP_ST0
AGP_ST2

INVT_PWM

TV_CRMA 15
TV_LUMA 15
TV_COMPS 15
TV_SYNC 15
PID0
24
PID1
24
PID2
24
PID3
24
INVT_PWM 32
+5VALW
ENBKL
32
ENVEE
32
+5VALW

16,24,34 SUS_STAT#
16 AGP_BUSY#
7
AGP_REQ#

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120

+1.5VS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120

1UF_25V_0805

AGP_AD15
AGP_AD13
AGP_AD11
AGP_AD9
AGP_ADSTB0# 7
AGP_C/BE#0
AGP_AD6
AGP_AD4
AGP_AD2
AGP_AD0

MDC_SPK

C469
1UF_25V_0805
1
2

MD_SPK

30

DAC_BRIG

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119

C472
B

+5VALW
32
DAC_BRIG
20,22,23,27,28 CBRST#
+5VALW

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119

15
CRT_R
15
CRT_G
15
CRT_B
15 CRT_HSYNC1
15 CRT_VSYNC1
15 CRT_DDCDATA
15 CRT_DDCCLK

AGP_ST[0..2]

AGP_ST[0..2]

7 AGP_AD[0..31]

1000PF

+AGP_VGAREF

HEADER 2X60

JP13
30

R94
CLK_AGP 1

C92

2
@33

MD_MIC

2
+3.3VAUX

@15PF

+3VS
16,30 IAC_SDATAO
16,30 IAC_RST#

L40

2 +3VS_MDC
CHB1608B121

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

MONO_OUT/PC_BEEP AUDIO_PWDN
GND
MONO_PHONE
AUXA_RIGHT
RESERVED
AUXA_LEFT
GND
CD_GND
+5V
CD_RIGHT
RESERVED
CD_LEFT
RESERVED
GND
RESERVED
3.3Vaux
RESERVED
GND
RESERVED
3.3Vmain
AC97_SYNC
AC97_SDATA_OUT AC97_SDATA_IN1
AC97_RESET#
AC97_SDATA_IN0
GND
GND
AC97_MSTRCLK
AC97_BITCLK

AMP-108-5424

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

MDC_DN# 33

MDC_SPK
+5VS_MDC1

+5VS

L43 CHB1608B121
1
2

+3VS

R374 10K

*
*

1
R361
1
R360

IAC_SYNC

2
22
2
@22

16,30

IAC_SDATAI1 16

1
R357

2
10K

MDC CONN.
IAC_BITCLK 16,30

COMPAL ELECTRONICS, INC

Title
PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
3

SCHEMATIC, M/B LA-1331

Document Number

Rev
2A

401207
, 18, 2004

Sheet
1

14

of

83

1
R203

+3VS

1
R196

2
@0

+5VS

R203 For CH7011/SQ17

**
2

D8
DAN217

D9
DAN217

D10
DAN217

L20
14

1
C222
14

2
22PF

L25
1
2
FBM-11-160808-121

TV_LUMA

1
C221

2
22PF

JP2

L24

1
2
FBM-11-160808-121
14

TV_CRMA

14

TV_COMPS

TV_OUT CONNECTOR

R196 For CH7007

**

1
2
@FBM-11-160808-121

TV_SYNC

1
2
3
4
5
6
7

1
2
C223
22PF
L26
1
2
FBM-11-160808-121

C192

C191

330PF

330PF

C202

C227

C226

C201

330PF

270PF

270PF

270PF

@470PF

CRT CONNECTOR
*

JP3
CRT-15P

22PF

100K

C3
22PF

R5
2.2K

1
Q1
2N7002

5VDDCCL

1
2

C6
22PF

C5
220PF

Q11
2N7002

R8
R6
2.2K

100K

CRT_DDCDATA 14

L1
1
2
CHB1608B121

+CRT_VCC

+12VS

5VDDCDA

2
R185

Q12
2N7002

2
+12VS
4

22PF

C183

L2
1
2
CHB1608B121

14 CRT_VSYNC1

22PF

C184

10PF

C185

14 CRT_HSYNC1

75

10PF

C198

1
2

75

C196 R184

10PF

R182
75

C197 R183

+CRT_VCC

L15
1
2
FCM2012C80_0805

CRT_B

14

CRT_G

14

L13
1
2
FCM2012C80_0805
L14
1
2
FCM2012C80_0805

CRT_R

14

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

C7
.1UF
3

FUSE_1A

RB491D

+CRT_VCC

@DAN217

@DAN217

@DAN217

*
2

+R_CRT_VCC
F1
1
1

D7

+5VS

D4

D5

D6

+3VS

**

C228

R201
75

75

75

R200

R202
2

S CONN._SUYIN

C182
220PF

CRT_DDCCLK 14

Q3
2N7002

COMPAL ELECTRONICS, INC

Title

SCHEMATIC, M/B LA-1331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE
Size
Document Number
Custom 401207
Date:
A

, 18, 2004

Sheet
E

15

TRANSFERRED FROM THE CUSTODY OF

Rev
2A
of

83

C306
2

13
13

+1.8VS

HUB Interface VSwing Voltage

J1
JOPEN

GATEA20 32
H_A20M# 5

1
R43

2
1

PCIRST#

7,14,19,20,21,22,23,24,27,28,34

C637
@10PF

+CPU_CORE

R217 (for use if CPU unable

@10K to support DPSLP#)
1
R298

H_FERR#

2
0

H_DPSLP# 5

H_IGNNE# 5
H_INIT# 5
H_INTR
5
H_NMI
5
H_PWRGD 5
RC#
32
H_SLP#
5
H_SMI#
5
H_STPCLK# 5

R327
300
2

R326
470
2

HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10

+3VS

2
Q25
3904

2
Q24
3904

HUB_PD[0..10]

HUB_PD[0..10] 7
5

+VS_HUBREF

1
R325

H_F_FERR#

2
470

+VS_HUBVSWING

CLK_ICHHUB 13
HUB_PSTRB 7
HUB_PSTRB# 7

CLK_ICHHUB
1
R315

2
100K

C29

.1UF

2
36.5_1%

R309
10

1
C394
.01UF

C393
.01UF

C395
5PF

Close to ICH3-M.

IRDY#
18,20,21,22,27,28
PAR
18,20,21,22,27,28
PERR#
18,20,21,22,27
PLOCK# 18,22
ICH_WAKE_UP# 32
1
2
R467
SERR#
18,20,22,27
33
STOP#
18,20,21,22,27,28
TRDY#
18,20,21,22,27,28

C405
@10PF

L22
M21
M23
N20
P21
R22
R20
T23
M19
P19
N19

C27
@15PF

HubLink
Interface

PM_LANPWROK

R312
@33

HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10

CLK_ICHHUB

+3VS

CLK_ICHAPIC

1
Y22
V23
AB22
J22
AA21
AB23
AA23
Y21
W23
U22
W21
Y23
U23

R63
@0

R253
1K

HUB Reference Voltage

R_K
R88
301_1%

Place R_K and R_L

Closely ICH3
2

1. Place R_G and R_H in middle of Bus.

1 2

CPU_A20GATE
CPU_A20M#
CPU_DPSLP#
CPU_FERR#
CPU_IGNNE#
CPU_INIT#
CPU
CPU_INTR
Interface
CPU_NMI
CPU_PWRGOOD
CPU_RCIN#
CPU_SLP#
CPU_SMI#
STPCLK#

GNTA#

1
C301
1UF_10V_0603

+3VS
+3VALW

2
SM_INTRUDER# 18
SMLINK0 18
SMLINK1 18
SMB_CLK 13,18
SMB_DATA 13,18
SMB_ALERT# 18

HUB_ICH_RCOMP

2
15K

12PF

R85
301_1%

R_G

PIRQA#
PIRQB#
PIRQC#
PIRQD#
ICH_PID0
ICH_PID1
ICH_PID2
ICH_PID3

Y6
AC3
AB2
AC4
AB5
AC5

CLK_ICHPCI 13
DEVSEL# 18,20,21,22,27,28
FRAME# 18,20,21,22,27,28
PCI_REQA# 18
PCI_REQB# 18

1
R258

C327

+1.8VS

R_L

+VS_HUBREF

COMPAL ELECTRONICS, INC

R91
301_1%

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

R_H

C79
.1UF

+VS_HUBVSWING
R86
301_1%
2

IDE_PATADET
ECSMI#
ECSCI#
LID#
GPIO_25
PIDEPWR

J19
J20
J21
B1
C1
B2
A2
A6
B5
C5
A5
AB14
W19
H22
SM_INTRUDER#
SMLINK0
System
SMLINK1
Managment SMB_CLK
Interface SMB_DATA
SMB_ALERT#/GPIO11

1
2

12PF

32.768KHZ

CLK_ICH14
CLK_ICH48

CLK_ICH14
CLK_ICH48

+RTCVCC
C336

T5
M3
F1
C4
D4
B6
B3
N3
G5
M2
M1
W1
Y1
L5
H2
H1

R264
2.4M

CLK_ICHPCI

PCI_CLK
PCI_DEVSEL#
PCI_FRAME#
PCI_GPIO0/REQA#
PCI_GPIO1/REQB#/REQ5#
PCI_GPIO16/GNTA#
PCI_GPIO17/GNTB#/GNT5#
PCI_IRDY#
PCI_PAR
PCI_PERR#
PCI_LOCK#
PCI
PCI_PME#
Interface
PCI_RST#
PCI_SERR#
STOP#
PCI_TRDY#

R271 10M_0603
X2

EEPROM
Interface

@10

R272 10M

RTC_X1
RTC_X2

LAN
Interface

22M

R261

V2
W2
Y4
Y2
W3
W4
Y3

V1
U3
T3
U2
T2
U4
U1

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
RTC_VBIAS

.047UF_0603
1
2

A1
A13
A16
A17
A20
A23
B8
B10
B13
B14
B15
B18
B19
B20
B22
C3
C6
F19
C14
C15
C16
C17
C18
C19
C20
C21
C22
D9
D13
D16
D17
D20
D21
D22
E5

ICH3-M

1K

GPIO_7
GPIO_8
GPIO_12
GPIO_13
GPIO_25
GPIO_27
GPIO_28

2 0
2 33

IAC_BITCLK 2
IAC_RST#
IAC_SDATAI0
IAC_SDATAI1
R55
1
R54
1

Clocks

+RTCVCC

R259

CLK_ICHPCI

H_FERR#

VSS

@10K
2
2
@10K

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4

1
1 2
2
1 2
2
3

R49
GNTA#
1
GPIO_25 1
R39

R308
0

D3
F4
A3
R4
E4

20,21,22,27,28
20,21,22,27,28
20,21,22,27,28
20,21,22,27,28

ICH3-M (1/2)

ICH_PID0
ICH_PID1
ICH_PID2
ICH_PID3

8
7
6
5

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4

@15PF

PCI
Interface

R306
1K

18,21
18,27
18,22
18,20
18,27

C399

+3VS

R50

HUB_VSWING
HUB_VREF
HUB_RCOMP
HUB_PSTRB#
HUB_PSTRB
HUB_PAR
HUB_CLK

PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4

@10

Interrupt
Interface

1
2
3
4

Place closely to ICH3

L19
L20
K19
P23
N22
R19
T19

A4
E3
D2
D5
B4

R307

unMUX
GPIO

EEP_SHCLK
EEP_DOUT
EEP_DIN
EEP_CS

GNT#0
GNT#1
GNT#2
GNT#3
GNT#4

INT_IRQ14 18,19
INT_IRQ15 18,29
INT_SERIRQ 18,22,24,32

INT_APICCLK
INT_APICD0
INT_APICD1
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
INT_PIRQE#/GPIO2
INT_PIRQF#/GPIO3
INT_PIRQG#/GPIO4
INT_PIRQH#/GPIO5
INT_IRQ14
INT_IRQ15
INT_SERIRQ

18,21
18,27
18,22
18,20
18,27

CLK_ICH48

LPC
Interface

D10
E8
D8
E9

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

@15PF

AC'97
Interface

Geyserville

RP14

14,18,21,22
18,20,22
18,27,28
18,27,28

8P4R_4.7K

R305
1K

LAN_RSTSYNC
LAN_JCLK
LAN_TXD2
LAN_TXD1
LAN_TXD0
LAN_RXD2
LAN_RXD1
LAN_RXD0

K2
K5
N1
R2

C406

Power Management

PIRQA#
PIRQB#
PIRQC#
PIRQD#

CLK_ICHAPIC
H_PICD0
H_PICD1

SIDEPWR 19

CLK_ICHAPIC
H_PICD0
H_PICD1

D7
C9
A10
C10
B9
A9
A8
C8

C/BE#0
C/BE#1
C/BE#2
C/BE#3

@10

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ#0
LPC_DRQ#1
LPC_FRAME#

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

R304

IAC_SDATAO
IAC _SYNC

@ 10PF

J2
K1
J4
K3
H5
K4
H3
L1
L2
G2
L4
H4
M4
J3
M5
J1
F5
N2
G4
P2
G1
P1
F2
P3
F3
R1
E2
N4
D1
P4
E1
P5

CLK_14
CLK_48
CLK_RTEST#
CLK_RTCX1
CLK_RTCX2
CLK_VBIAS

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CLK_ICH14

PIRQA#
PIRQB#
PIRQC#
PIRQD#

Place closely to ICH3

B7
D11
B11
C11
C7
A7

U29A

20,21,22,27,28 AD[0..31]

AC_BITCLK
AC_RST#
AC_SDATAIN0
AC_SDATAIN1
AC_SDATAOUT
AC_SYNC

2
@ 10K

U20
Y20
V19

1
R278

PM_LANPWROK

AGP_BUSY#

PM_GMUXSEL/GPIO23
PM_CPUPREF#/GPIO22
PM_VGATE/VRMPWRGD

+3VS

C44

R58
@ 33

2
R26

PM_SUSCLK

14

V4
Y5
AB3
V5
AC2
AB21
AB1
AA6
AA1
AA7
W20
AA5
AA2
V21
U21
AA4
AB4
U5

14,30 IAC_RST#
30 IAC_SDATAI0
14 IAC_SDATAI1
14,30 IAC_SDATAO
14,30 IAC_SYNC
14,30 IAC_BITCLK

PM_AGPBUSY#/GPIO6
PM_AUXPWROK
PM_BATLOW#
PM_C3_STAT#/GPIO21
PM_CLKRUN#/GPIO24
PM_DPRSLPVR
PM_PWRBTN#
PM_PWROK
PM_RI#
PM_RSMRST#
PM_SLP_S1#/GPIO19
PM_SLP_S3#
PM_SLP_S5#
PM_STPCPU#/GPIO20
PM_STPPCI#/GPIO18
PM_SUS_CLK
PM_SUS_STAT#
PM_THRM#

22,23,28 RTCCLK

LPC_AD0 24,32
LPC_AD1 24,32
LPC_AD2 24,32
LPC_AD3 24,32
LPC_DRQ#0 18,32
LPC_DRQ#1 18,24
LPC_FRAME# 24,32

J23
F20
RTC_RST# Y7
RTC_X1 AC7
RTC_X2 AC6
RTC_VBIAS
AB7

35
ICH_VGATE
5 PM_CPUPERF#
42 PM_GMUXSEL
32
ATF_INT#
14,24,34 SUS_STAT#
13 PM_STPPCI#
2
1 PM_SUSCLK
13,42 PM_STPCPU#
R44
0
32 PM_SLP_S5#
13,32 PM_SLP_S3#
IAC_RST#
13,32 PM_SLP_S1#
IAC_SDATAI0
35 PM_RSMRST#
IAC_SDATAI1
18
ICH_RI#
IAC_SDATAO
35 PM_PWROK
IAC _SYNC
18
PBTN#
IAC_BITCLK
42 PM_DPRSLPVR
18,22,24,27,28,32 PM_CLKRUN#
2
1
14
C3_STAT#
R351
10K
32 PM_BATLOW#

ECSMI#
ECSCI#
LID#
IDE_PATADET

18
ECSMI#
18
ECSCI#
18
LID#
19 IDE_PATADET

Size
Document Number
Custom
Date:

TRANSFERRED FROM THE CUSTODY OF THE COMPE

Rev
2A

401207

, 18, 2004

Sheet
D

16

of

83

+5VALW

R284
0

USB_D_PN0
USB_D_PN1
USB_D_PN3

*
+3V

RP20
8P4R_10K

1
2
3
4

8
7
6
5

USB_OC#2
USB_OC#4
USB_OC#5

26
26

USB_OC#0
USB_OC#1

26

USB_OC#3

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5

19 ICH_IDE_PRST#
19 ICH_IDE_SRST#

1
R90
18
18
33

2
@0

FWH_WP#
FWH_TBL#
EC_FLASH#

ICH_ACIN

2
VCC5REFSUS

+1.8VS

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5

H20
G22
F21
G19
E22
E21
H21
G23
F23
G21
D23
E23

USB_LEDA#0/GPIO32
USB_LEDA#1/GPIO33
USB_LEDA#2/GPIO34
USB_LEDA#3/GPIO35
USB_LEDA#4/GPIO36
USB_LEDA#5/GPIO37
USB_LEDG#0/GPIO38
USB_LEDG#1/GPIO39
USB_LEDG#2/GPIO40
USB_LEDG#3/GPIO41
USB_LEDG#4/GPIO42
USB_LEDG#5/GPIO43

B21

USB_RBIAS

H23

SPKR

U19

VCCA

F17
F18
K14

VCCPSUS3/VCCPUSB0
VCCPSUS4/VCCPUSB1
VCCPSUS5/VCCPUSB2

E10
V8
V9

VCCPSUS0
VCCPSUS1
VCCPSUS2

E11
K6
K18
P6
P18
V10
V14

J18
M14
R18
T18
VCCPHL0
VCCPHL1
VCCPHL2
VCCPHL3

P12
V15
V16
V17
V18
VCCPIDE0
VCCPIDE1
VCCPIDE2
VCCPIDE3
VCCPIDE4

G18
H18
VCCP0
VCCP1

F6
G6
H6
J6
M10
R6
T6
U6
VCCPPCI0
VCCPPCI1
VCCPPCI2
VCCPPCI3
VCCPPCI4
VCCPPCI5
VCCPPCI6
VCCPPCI7

A21
A22
VSS102
VSS103

N/C0
N/C1
N/C2
N/C3
N/C4

C23

P14
U18
V22

C13
W5

E6
W8

AB6
VCC_RTC

VCCCORE0
VCCCORE1
VCCCORE2
VCCCORE3
VCCCORE4
VCCCORE5
VCCCORE6

E12
D12
C12
B12
A12
A11

VCCUSBBG/VCC_SUS8

USB_PP0
USB_PP1
USB_PP2
USB_PP3
USB_PP4
USB_PP5
USB_PN#0
USB_PN#1
USB_PN#2
USB_PN#3
USB_PN#4
USB_PN#5

VCCPCPU0
VCCPCPU1
VCCPCPU2

D19
A19
E17
B17
D15
A15
D18
A18
E16
B16
D14
A14

F9
F10

+3VS
+1.8VA_ICH

Power

USB
Interface

ICH3-M (2/2)

IDE
Interface

USB_RBIAS

R310
0_0805

VCCUSBPLL/VCC_SUS9

USB_D_PP3

+1.8VALW

+CPU_CORE

VCCPAUX0/VCCLAN3_3
VCCPAUX1/VCCLAN3_3

C361
.1UF

R279
0_0805

VCC5REFSUS1
VCC5REFSUS2

USB_D_PP0
USB_D_PP1

VCC5REF1
VCC5REF2

U29B

USB_D_PP3
USB_D_PN3

F7
F8
K10

USB_PP3
USB_PN3

VCC_AUX0/VCCLAN1_8
VCC_AUX1/VCCLAN1_8
VCC_AUX2/VCCLAN1_8

26
26

+3VS

+RTCVCC

0_0805

USB_D_PP1
USB_D_PN1

F15
F16

USB_PP1
USB_PN1

VCC_USB0/VCC_SUS6
VCC_USB1/VCC_SUS7

26
26

USB_D_PP0
USB_D_PN0

E13
F14
K12
P10
V6
V7

USB_PP0
USB_PN0

CHB2012U170

VCC_SUS0
VCC_SUS1
VCC_SUS2
VCC_SUS3
VCC_SUS4
VCC_SUS5

26
26

L37
1

*
1
R294

C330
1UF_10V_0603

+V1.8_ICHLAN

+1.8VS

1
C43
.1UF

+V5S_ICHREF

B23

+V5S_ICHREF

D27
1SS355

+1.8VALW

**

R59
1K

DEL:C73, C87, C371.

E7
T21
D6
T1
C2

+3VS

+5VS

31

R293
18.2_1%

ICH_SPKR

ICH_SPKR
+1.8VS

+3VALW

Disable Timeout Feature

1
R313

0_0805

+V3A_ICH

2 ICH_SPKR
@1K

Power

VSS

AC15
AB15
AC21
AC22

IDE_PDCS1#
IDE_PDCS3#
IDE_SDCS1#
IDE_SDCS3#

IDE_PDA0
IDE_PDA1
IDE_PDA2
IDE_SDA0
IDE_SDA1
IDE_SDA2

AA14
AC14
AA15
AC20
AA19
AB20

IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

W12
AB11
AA10
AC10
W11
Y9
AB9
AA9
AC9
Y10
W9
Y11
AB10
AC11
AA11
AC12

IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

IDE_PDA0 19
IDE_PDA1 19
IDE_PDA2 19
IDE_SDA0 29
IDE_SDA1 29
IDE_SDA2 29
IDE_PDD[0..15] 19

IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15

Y17
W17
AC17
AB16
W16
Y14
AA13
W15
W13
Y16
Y15
AC16
AB17
AA17
Y18
AC18

IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15

IDE_PDDACK#
IDE_SDDACK#
IDE_PDDREQ
IDE_SDDREQ
IDE_PDIOR#
IDE_SDIOR#
IDE_PDIOW#
IDE_SDIOW#
IDE_PIORDY
IDE_SIORDY

Y13
Y19
AB12
AB18
AC13
AC19
Y12
AA18
AB13
AB19

19
19
29
29

IDE_SDD[0..15] 29

IDE_PDDACK# 19
IDE_SDDACK# 29
IDE_PDDREQ 19
IDE_SDDREQ 29
IDE_PDIOR# 19
IDE_SDIOR# 29
IDE_PDIOW# 19
IDE_SDIOW# 29
IDE_PIORDY 19
IDE_SIORDY 29

VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101

+3VS

R288

Misc

IDE_PDCS1#
IDE_PDCS3#
IDE_SDCS1#
IDE_SDCS3#

+3VS

ICH3-M

E14
E15
E18
E19
E20
F22
G3
G20
H19
AA22
J5
K11
K13
K20
K21
K22
K23
L3
L10
L11
L12
L13
L14
L21
L23
M11
M12
M13
M20
M22
N5
N10
N11
N12
N13
N14
N21
N23
P11
P13
P20
P22
R3
R5
R21
R23
T4
T20
T22
V3
AC23
V20
W6
W7
W10
W14
W18
W22
Y8
AA3
AA8
AA12
AA16
AA20
AB8
AC1
AC8

R295
100K

Title

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331
TRANSFERRED

37

1
D32

ACIN

2
RB751V

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE
Size
Document Number
Custom
401207

ICH_ACIN

Date:
A

, 18, 2004

Sheet
E

17

of

83

FROM THE CUSTODY OF

Rev
2A

+3VS PULL-UP/BY-PASS

+3VS
+3VS

47PF

C131

C130
.1UF

C84
.1UF

1
C82
.1UF

47PF

C71

1
C70
.1UF

C76
.1UF

1
C75
.1UF

47PF

C63

1
C50
.1UF

C42
.1UF

47PF

C41

1
C40
.1UF

C34
.1UF

47PF

C31

1
C32
.1UF

C35
.1UF

C287
22UF_16V_1206

+
C269
22UF_16V_1206

16,20,22,27
16,20,21,22,27,28
16,20,21,22,27
16,22

SERR#
DEVSEL#
PERR#
PLOCK#

10
9
8
7
6

RP12

1
2
3
4
5

16,20,21,22,27,28 FRAME#
16,20,21,22,27,28 IRDY#
16,20,21,22,27,28 TRDY#
16,20,21,22,27,28 STOP#

+3VS

C60
.1UF

10P8R_8.2K

+3VS

+3VS

+3VS
RP19

16
16
16,21
16,27

RP22

1
2
3
4
5

PCI_REQA#
PCI_REQB#
REQ#0
REQ#1

10
9
8
7
6

1
2
3
4

17
FWH_WP#
17
FWH_TBL#
16,22,24,27,28,32 PM_CLKRUN#

REQ#2
16,22
REQ#3
16,20
REQ#4
16,27
INT_SERIRQ 16,22,24,32

8
7
6
5

+3VS

8P4R_10K

10P8R_8.2K

16,20 GNT#3

RP13

1
2
3
4
5

16,27 GNT#1
16,22 GNT#2
16,27,28 PIRQD#
16,19 INT_IRQ14

1
R41
1
R47
1
R42

16,21 GNT#0
+3VS

+3VS

+3VS

1
R32
1
R40

16,32 LPC_DRQ#0

10
9
8
7
6

INT_IRQ15 16,29
PIRQA#
14,16,21,22
PIRQB#
16,20,22
PIRQC# 16,27,28

16,24 LPC_DRQ#1

2
10K
2
10K

16,27 GNT#4

2
8.2K
2
8.2K
2
8.2K

10P8R_8.2K

+3VALW PULL-UP

R57

16,20,21,22,27,28 PAR

@100

+3V PULL-UP/BY-PASS
+3V

+3V

1
R466

C357
.1UF

C354
.1UF

C355
.1UF

16 SM_INTRUDER#

2
100K

47PF

PBTN#

PBTN#

16

+V5S_ICHREF BY-PASS

+V1.8S_ICHLAN BY-PASS

+1.8VS

+V5S_ICHREF

+V1.8_ICHLAN

C78
.1UF

C61
47PF

C80
.1UF

C81
.1UF

C39

.1UF

.1UF

C47

.1UF

+
C321
1UF_10V_0603

C33
.1UF

C77
.1UF

C36
47PF

C67
.1UF

C241
150UF_6.3V_D2

C54

2
@0

1
R468

ON/OFF

2
0

+1.8SV BY-PASS

32,34

ON/OFF

10K

PBTN_OUT#

C267
22UF_16V_1206

4.7K

1
R256

+3VALW

PBTN_OUT#

32
3

R45

SMB_CLK

C356

4.7K

*
16 SMB_ALERT#

4.7K

1
R263

13,16

4.7K

SMLINK1

16

1
R250
1
R246

SMLINK0

+RTCVCC
R46

13,16 SMB_DATA

16

+RTCVCC PULL-UP

+3VALW

C48
.1UF

RP135
16
16
16
16

+V3A_ICH BY-PASS

+CPU_CORE BY-PASS

8P4R_0

+1.8VA_ICH

+CPU_CORE

.01UF

C53

.01UF

+
C376
1UF_10V_0603

C83
.1UF

C88
.1UF

C389
22UF_16V_1206

C85

.1UF

C51

.1UF

C46

.1UF

C66

.1UF

C74

+V3A_ICH

+1.8VA_ICH BY-PASS

ICH_RI#
ECSMI#
ECSCI#
LID#

C396
.1UF

C397
.1UF

ICH_RI#
ECSMI#
ECSCI#
LID#

5
6
7
8

4
3
2
1

EC_SWI#
EC_SMI#
EC_SCI#
EC_LID_OUT#

32
EC_SWI#
32
EC_SMI#
32
EC_SCI#
32 EC_LID_OUT#

C398
.1UF

Title

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE
Size
Document Number
Custom 401207
Date:
A

, 18, 2004

Sheet
E

18

TRANSFERRED FROM THE CUSTODY OF

Rev
2A
of

83

IDE,CD-ROM Module CONN.

+5VS

.1UF

IDE_PDD[0..15]

ATA33 : populate R31, de-populate R33.

ATA66/100 : populate R33, de-populate R31.
R31

+5VCD

Place component's closely IDE CONN.

Q8
SI3456DV

@10K
JP7

2
100K

29

R152

2
@10K

IDE_PDA2 17
IDE_PDCS3# 17

16

CD_SIOW#
CD_SIORDY
CD_IRQ
CD_SBA1
CD_SBA0
CD_SCS1#
SHDD_LED#

24
24
24
24
24
24
24
24,33

CD _SIORDY
CD_IRQ

SHDD_LED#
EXTCSEL
RDATA#
WP#
TRACK0#
WDATA#
STEP#
MTR0#
DSKCHG#
DRV0#

RDATA#
WP#
TRACK0#
WDATA#
STEP#
MTR0#
DSKCHG#
DRV0#

SIDEPWR

G1

2 IDE_PDD7
@10K
2 CDD7
10K

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

INT_CD_R 30

CD_AGND
CD D8
CD D9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15
CD_DREQ

+3VS
+5VMOD

1
R76

2 IDE_PIORDY
4.7K

1
R406

2 CD_SIORDY
4.7K

1
R69

1
R141

C114

+5VS

.1UF

WGATE#

FDD IR#
3MODE#

WGATE#

24

FDDIR#
3MODE#

24
24

U9

1
4

PIDE_RST#

17 ICH_IDE_PRST#

7SH08FU

+5VS
INDEX#

INDEX#
+5VMOD

24
C113

5
8
7
6
5

EXTID0
EXTID1
EXTID2

U10

PCIRST#1

4
17 ICH_IDE_SRST#

8P4R_100K

SIDE_RST# 29

2
7SH08FU

DRV0#

2 EXTCSEL
470

1000PF

C148

+5VS

W=80mils

+5VMOD
STEP#
MTR0#
RDATA#

5
4
3
2
1

6
7
8
9
10
10P8R_1K

1
R154

PCIRST#

7,14,16,20,21,22,23,24,27,28,34 PCIRST#

1
2
3
4

RP1
WDATA#
WGATE#
HDSEL#
FDD IR#

+5VS
CD_DREQ 29
CD_SIOR# 29
CD_DACK# 29
CD_SBA2 29
CD_SCS3# 29
EXTID0
33
EXTID1
33
EXTID2
33
HDSEL# 24

EXTID0
EXTID1
EXTID2
HDSEL#

2
1K

RP3
DSKCHG#
INDEX#
WP#
TRACK0#

8P4R_1K

1
R235

SI3456DV: N CHANNEL
VGS: 4.5V, RDS: 65 mOHM
Id(MAX): 5.1A
VGS,+-20V

.1UF

RP2

1
2
3
4

C140
.01UF

2 CD_DREQ
5.6K

+3VALW

8
7
6
5

Q37A
SI1906DL

2 IDE_PDDREQ
@5.6K

HEADER 2X30
+5VS

47K

29
29
29
29
29
29
33

1K

+5VS

JP17
CD_AGND
CD_RSTDRV#
CD D7
CD D6
CD D5
CD D4
CD D3
CD D2
CD D1
CD D0

R398

EXTIDE_EN#
G2

Q37B
SI1906DL

1
R302

33 EXTIDEPWR#

2
470

1
R73

47K

PCSEL

Q36
DTC144EKA

100K

1
R61

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

1
1

1
R407

30
INT_CD_L
30
CD_AGND
29 CD_RSTDRV#

+12VALW

C137
R150
4.7UF_16V_1206
<1st Part Field>
1K

@10K

CDD[0..15]

CDD[0..15]

HDD 44P SUYIN 20225A-44G5-A

2 SHDD_LED#
100K

1
R155

+5VMOD

+
R33

S1

1
R89

+5VS

+5VS

D1

INT_IRQ14

IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

S2

IDE_PIORDY

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

IDE_PDDREQ

17 IDE_PDDREQ
17 IDE_PDIOW#
17 IDE_PDIOR#
17 IDE_PIORDY
17 IDE_PDDACK#
16,18 INT_IRQ14
17
IDE_PDA1
17
IDE_PDA0
17
IDE_PDCS1#
33
PHDD_LED#

IDE_PATADET 16

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

D2

PIDE_RST#
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0

+5VMOD

6
5
2
1

17 IDE_PDD[0..15]

HDD Manual ATA Type Selection:

C89

C93
C379
10UF_16V_1206
1UF_25V_0805

1000PF

C90

+5VS

C149
C147
C145
1UF_25V_0805 .1UF
10UF_16V_1206

COMPAL ELECTRONICS, INC

Place component's closely CD-ROM CONN.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

Size
B

Document Number

Date:

, 18, 2004

TRANSFERRED FROM THE CUSTODY OF T

Rev
2A

401207
Sheet

19

of

83

+3VLAN To +2.5VLAN Transfer

+3V

1
L32

2
4.7UH

AVDD-2

1
L31

2
4.7UH

+3VLAN
Q15
VCTRL

AD29
AD28
AD27
AD26
AD25
AD24

+2.5VLAN

16,21,22,27,28 C/BE#3

1
1

C10
0.1UF

AD23
AD17

1
R243

2
100

1
2

AD0
AD1

8
7
6
5

VCC
NC
NC
GND
9346

AD2
AD3

C248

0.1UF

C/BE#0

16,21,22,27,28

C255
4.7UF_10V_1206
RTL8100-B(L)

R179
510_0603
2

PR2-

PR3-

PR3+

RJ45_RX+

PR2+

RJ45_TX-

PR1-

RJ45_TX+

PR1+

C11

2
510_0603

1
2

15

10

Green LED-

Green LED+

SHLD2

14

SHLD1

13

R166
75

C180
1000P_2KV_1206
LAN_GND

LANGND

16

SHLD3

AMP RJ45/RJ11 with LED

R165
75
Q16
DTA114YKA

SHLD4
PR4-

+3V

C181
0.1UF

C187

Termination plane should be copled to chassis ground

R174
75

C13
0.1UF

4.7UF_10V_0805

R175
75

R13
50

2
1

RJ45_TX+
RJ45_TX-

R12
50

C8
0.1UF

Amber LED-

AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8

1
2
1

1
2

LINK10_100#
RJ45_RX+
RJ45_RX-

16
15
14
13
12
11
10
9

Pulse H0013

***

LAN_TD+
LAN_TD-

0.1UF

1 2
2

50

11

PR4+

RJ45_RX-

U18

50

Amber LED+

R15

12

Layout Note
The H0013 pls close to JP5

R14

C272

1000PF

JP5

+3V

RX+
RXCT
NC
NC
CT
TX+
TX-

C262

AD7

Q14
DTA114YKA

RD+
RDCT
NC
NC
CT
TD+
TD-

0.1UF

2
0_1206

AD4
AD5
AD6

R167

1
2
3
4
5
6
7
8

C271

1000PF

+2.5V

1
R189

0.1UF

C264
0.1UF

LAN_RD+
LAN_RD-

0.1UF

+3VLAN

47K

@10PF

1
C260

C15

C246

C253

1000PF

CS
SK
DI
DO

1
2
3
4

U3
LAN_EECS
LAN_EECLK
LAN_EEDI
LAN_EEDO

AUX

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

10K

@22

C252

2
0_1206

+2.5VLAN

16,21,22,27,28 C/BE#2
16,18,21,22,27,28 FRAME#
16,18,21,22,27,28 IRDY#
16,18,21,22,27,28 TRDY#
16,18,21,22,27,28 DEVSEL#
16,18,21,22,27,28 STOP#
16,18,21,22,27 PERR#
16,18,22,27 SERR#
16,18,21,22,27,28 PAR
16,21,22,27,28 C/BE#1

R227

0.1UF

C275

1000PF

C273

0.1UF

+3V

+3VLAN

CLK_PCI_LAN

C254

1
2

18PF

R207
5.6K

ACTIVITY#
STOP#
PERR#
SERR#
PAR

AD18
AD17
AD16
C/BE#2
FRAME#
IRD Y#
TRDY#
DEVSEL#

AD[0..31]

AD21
AD20
AD19

AD22

16,21,22,27,28 AD[0..31]

U4

AUX
EECS
EESK
EEDI
EEDO
AD0
AD1
GND
AD2
AD3
VDD25
VDD
AD4
AD5
AD6
VDD25
VDD
AD7
CBE0B
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

C274
0.1UF

+3V

1
R228

+3VLAN

C236

AD31
AD30

INTAB
RSTB
CLK
GNTB
REQB
AD31
AD30
GND
AD29
VDD
AD28
AD27
AD26
AD25
AD24
VDD25
VDD
CBE3B
IDSEL
AD23

18PF

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

C237

13 CLK_PCI_LAN
16,18 GNT#3
16,18 REQ#3

+3VLAN
LAN_X2

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
14,22,23,27,28 CBRST#

2
0
2
@0
CLK_PCI_LAN

ACTIVITY#
LINK10_100#

+3V

LED0
LED1
NC
LED2
AVDD25
AVDD
ISOLATEB
GND
TXD+
TXDAVDD
AVDD25
RXIN+
RXINGND
RTSET
RTT2
RTT3
GND
X1
X2
AVDD
AVDD25
PMEB
GND
VCTRL
NC
NC
NC
VDD25

1
R23
1
R22

Y2
25 MHz

+2.5VLAN

AD22
GND
AD21
AD20
AD19
VDD
VDD25
AD18
AD17
AD16
CBE2B
FRAMEB
IRDYB
TRDYB
DEVSELB
GND
STOPB
PERRB
SERRB
PAR
CBE1B
VDD
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8

16,18,22 PIRQB#
7,14,16,19,21,22,23,24,27,28,34 PCIRST#

***
LAN_X1

R205
15K

0.1UF

C214
@ 10UF_10V_1206

@ 0.1UF

+2.5VLAN

LAN_X1
LAN_X2
VCTRL

D43
RB751V

5.6K_1%
R204

4.7UF_10V_1206

2
1K

C213

0.1UF

47K

1
R208

+2.5VLAN

C224

1
L23
C218

C234

10K

***

0.1UF

@ 2SB1197K

+3VS

LAN_TDLAN_TD+

0.1UF

2
4.7UH

LAN_PME#
LAN_RDLAN_RD+

C235

C233

32

1
L30

AVDD-3

AVDD-1

LAN_GND

COMPAL ELECTRONICS, INC

0.1UF
Title
PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
3

SCHEMATIC, M/B LA-1331

Document Number

Rev
2A

401207
, 18, 2004

Sheet
1

20

of

83

IEEE1394 Controller/PHY

+3VS

R437
1M_0402

.1UF

C599

C612
.1UF

.1UF

C533

.1UF

C525

.1UF

C515

.1UF

C514

.1UF

C611
.1UF

Enable I2C EEPROM

10PF_0402

R436
1K

C509

C506

+3VS

R438

AD[0..31]

16,20,22,27,28 AD[0..31]

.1UF

2
C507
10PF

C508

.1UF

C504

24.576MHz
+3VS

X4

2K
+3VS

R426
1K

+3VS
C503
.1UF

C590

C512
.1UF

C517

C520

.1UF

.1UF

.1UF

CLK_PCI_1394
R449

GNT#0
REQ#0

AD31
AD30
AD29
AD28
AD27

1 2

33

1
2

AD5
AD6
AD7
C/BE#0

16,20,22,27,28

AD13
AD14
AD15

R411
56.2_1%
C/BE#1
PAR
PERR#

16,20,22,27,28
16,18,20,22,27,28
16,18,20,22,27

XTPBIAS0
XTPA0+
XTPA0XTPB0+
XTPB0-

AD8
AD9
AD10
AD11
AD12

R410
56.2_1%

C489
3

1UF_25V_0805
1
L52
1
L53
1
L54
1
L55

R408
56.2_1%

1394 VT6306
56.2_1%

*
*
*
*

2
0

JP12
4
3
2
1

2
0
2
0
2
0

4
3
2
1

Molex SD-54030-0411

2
AD16
AD17
AD18
AD19
AD20

AD21

AD22
AD23

AD24
AD25
AD26

STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
C/BE#2

16,20,22,27,28 C/BE#3
AD16
4

1
R452

R418
5.11K

C487
220PF

22PF

AD2
AD3
AD4

R409

103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

C600

R439
510

1/20 EECK,EEDI RENAMED TO EECK_LAN,EEDI_LAN

CLK_PCI_1394

EECK_LAN
EEDI_LAN

AD0
AD1

16,18
16,18

8
7
6
5

VCC
WC#
SCL
SDA

24C02-27
EECK_LAN
EEDI_LAN

14,16,18,22 PIRQA#
7,14,16,19,20,22,23,24,27,28,34 PCIRST#
13 CLK_PCI_1394

1394_PME# 32

A0
A1
A2
GND

.1UF

LPS/CMC
PME#
VSSC2
VDDC2
VSS9
VDD6
SCL/EECK
SDA/EEDI
EEDO
EECS
AD0
AD1
VSS8
RAMVSS
RAMVDD
AD2
AD3
AD4
VDD5
AD5
AD6
AD7
VSS7
CBE0#
AD8
AD9
AD10
AD11
AD12
VSS6
VDD4
AD13
AD14
AD15
CBE1#
PAR
PERR#
VSS5

1
2
3
4

C610

VDDARX0
XREXT
NC
GNDARX1
GNDATX1
XTPB0M
XTPB0P
XTPA0M
XTPA0P
XTPBIAS0
VDDARX1
VDDATX1
XTPB1M
XTPB1P
XTPA1M
XTPA1P
XTPBIAS1
GNDARX2
GNDATX2
XTPB2M
XTPB2P
XTPA2M
XTPA2P
XTPBIAS2
VDDARX2
VDDATX2
INTA#
PCIRST#
PCICLK
VSS1
GNT#
REQ#
AD31
AD30
AD29
AD28
AD27
VDD1

+3VS
U44
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

XTPB0XTPB0+
XTPA0XTPA0+
XTPBIAS0

65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102

.1UF

C513
47PF

GNDARX0
XCPS
VDDATX0
XO
XI
GNDATX0
PHYRESET
LINKON/TSIJMP
LREQ/TSOJMP
CTL1/PC1JMP
CTL0/PC0JMP
D7/PC2JMP
D6/CMCJMP
D5
PGND2
PVDD2
D4
D3
D2
D1
D0
MODE0
MODE1
PGND1
SCLK
PVDD1

C603
2

VSS2
AD26
AD25
AD24
CBE3#
IDSEL
AD23
AD22
VSS3
AD21
VDD2
VDDC1
VSSC1
AD20
AD19
AD18
AD17
AD16
VSS4
CBE2#
FRAME#
IRDY#
VDD3
TRDY#
DEVSEL#
STOP#

.1UF

R442
6.34K 1%

U45

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39

C597

2
100

16,18,20,22,27,28
16,18,20,22,27,28
16,18,20,22,27,28
16,18,20,22,27,28
16,18,20,22,27,28
16,20,22,27,28

@X3

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331 TRANSFERRED

Size
Document Number
Custom
Date:
A

FROM THE CUSTODY OF THE COMPE

Rev
2A

401207

, 18, 2004

Sheet
E

21

of

83

+3VS

CardBus Controller
OZ6933T (uBGA)

+3VS

CBRST#

+3VS

B14
A4
V9
K19
J19
E8

16,18,24,32 INT_SERIRQ

C5
E6

IRQ5/SERIRQ
IRQ7/SIN#/B_VPP_PGM

GND
GND

GND
GND
GND
GND
GND
NC
NC

S2_D10
S2_D9
S2_D1
S2_D8
S2_D0
S2_A0
S2_A1
S2_A2
S2_A3
S2_A4
S2_A5
S2_A6
S2_A25
S2_A7
S2_A24
S2_A17

P2
W5
V15
K18
E11
B15
E5

C631
.1UF

C630
.1UF

C534
.1UF
1

+S1_VCC

L18
M19
M18
M15
M17
N17
P18
R19
N14
R17
T19
R14
U15
P14
W15
U11
P10
W11
U10
V10
P9
R9
U9
W9
U8
R8
W7
V7
U7
W6
P8
U6

IRQ12/PME#
IRQ14/CLKRUN#
IRQ15/RING_OUT
SPKR_OUT#
LED_OUT/SKT_ACTIVITY
SKTB_ACTV

H3
K5

CardBus-OZ6933T-1

N18

Slot B

R450
@33

C604
@10PF

GRST#

R10
J18
B10
CORE_VCC
CORE_VCC
CORE_VCC

F2
J5
M6
P5
PCI_VCC
PCI_VCC
PCI_VCC
PCI_VCC

IDSEL
PCI_CLK
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PERR#
SERR#
PCI_REQ#
PCI_GNT#
IRQ9/INTA#
IRQ4/INTB#
LOCK#
RST#

32 PCM_PME#
16,18,24,27,28,32 PM_CLKRUN#
28
PCM_RI#
31 PCM_SPK#
33 PCM1_LED
33
PCM2_LED

C626
.1UF

A_SOCKET_VCC
A_SOCKET_VCC

R7
R13

A_REG#/CCBE3#
A_A12/CCBE2#
A_A8/CCBE1#
A_CE1#/CCBE0#

N15
V14
V11
W8

A_A16/CCLK
A_A23/CFRAME#
A_A15/CIRDY#
A_A22/CTRDY#
A_A21/CDEVSEL#
A_A20/CSTOP#
A_A13/CPAR
A_A14/CPERR
A_WAIT#/CSERR#
A_INPACK#/CREQ#
A_WE#/CGNT#
A_RDY_IRQ#/CINT#
A_A19/CBLOCK#
A_WP/CCLKRUN#
A_RST/CRESET#
A_D2/RFU
A_D14/RFU
A_A18/RFU
A_VS1/CVS1
A_VS2/CVS2
A_CD1#/CCD1#
A_CD2#/CCD2#
A_BVD2/CAUDIO
A_BVD1/CSTSCHG

V13
U14
P13
W14
U13
W13
R11
V12
R18
P17
R12
P12
U12
L17
P15
L19
V8
P11
W10
W16
V6
L14
M14
N19

B_BVD1/CSTSCHG
B_BVD2/CAUDIO
B_CD2#/CCD2#
B_CD1#/CCD1#
B_VS2/CVS2
B_VS1/CVS1
B_A18/RFU
B_D14/RFU
B_D2/RFU
B_RESET/CRESET#
B_WP/CCLKRUN#
B_A19/CBLOCK#
B_RDY_IRQ#/CINT#
B_WE#/CGNT#
B_INPACK#/CREQ#
B_WAIT#/CSERR#
B_A14/CPERR#
B_A13/CPAR
B_A20/CSTOP#
B_A21/CDEVSEL#
B_A22/CTRDY#
B_A15/CIRDY#
B_A23/CFRAME#
B_A16/CCLK

F8
C8
C6
J15
A10
E18
C14
G17
F7
C10
A5
A14
F12
E13
C9
A9
A15
C15
C13
B13
A13
C12
B12
E12

B_CE1#/CCBE0#
B_A8/CCBE1#
B_A12/CCBE2#
B_REG#/CCBE3#

G14
A16
A12
F9

B_SKT_VCC
B_SKT_VCC
B_SKT_VCC

G19
F13
E7

C632

C633

C634

.1UF

.1UF

.1UF

S1_REG# 23

S1_A12
S1_A8

S1_A[0..25]
S1_CE1#

R457
1

S1_A23
S1_A15
S1_A22
S1_A21
S1_A20
S1_A13
S1_A14

2 33

S1_A19
S1_D2
S1_D14
S1_A18

S2_A18
S2_D14
S2_D2
S2_A19

S2_A14
S2_A13
S2_A20
S2_A21
S2_A22
S2_A15
S2_A23
1
R446
S2_A8
S2_A12

S1_A[0..25] 23

23
S1_D[0..15] 23

S1_A16

S2_A[0..25]
S1_WAIT# 23
S1_INPACK# 23
S1_WE# 23
S1_RDY# 23
S1_WP
S1_RST

23
23

S1_VS1
S1_VS2
S1_CD1#
S1_CD2#
S1_BVD2
S1_BVD1

23
23
23
23
23
23

S2_BVD1
S2_BVD2
S2_CD2#
S2_CD1#
S2_VS2
S2_VS1

23
23
23
23
23
23

S2_RST
S2_WP

23
23

S2_A[0..25] 23

S2_D[0..15]

S2_D[0..15] 23

S2_RDY# 23
S2_WE# 23
S2_INPACK# 23
S2_WAIT# 23

2
33

S2_A16

S2_CE1#

23

S2_REG# 23
+S2_VCC

C537

C535

C536

.1UF

.1UF

.1UF

SLATCH
SLDATA
RTCCLK

23
23
16,23,28

S2_A10
S2_D15
S2_D7
S2_D13
S2_D6
S2_D12
S2_D5
S2_D11
S2_D4
S2_D3

CLK_PCI_CB

H5
E3
L3
K6
L1
L2
L5
M2
L6
M1
G6
F5
B5
F6
V5
D1

S2_A9

100
2

C/BE3#
C/BE2#
C/BE1#
C/BE0#

Slot
A

S2_A11

13 CLK_PCI_CB
16,18,20,21,27,28 DEVSEL#
16,18,20,21,27,28 FRAME#
16,18,20,21,27,28 IRDY#
16,18,20,21,27,28 TRDY#
16,18,20,21,27,28 STOP#
16,18,20,21,27,28 PAR
16,18,20,21,27 PERR#
16,18,20,27 SERR#
16,18 REQ#2
16,18 GNT#2
14,16,18,21 PIRQA#
16,18,20 PIRQB#
16,18 PLOCK#
7,14,16,19,20,21,23,24,27,28,34 PCIRST#

R451
AD20 1
CLK_PCI_CB

G1
K3
M3
R1

O 2 MICRO
CARDBUS CONTROLLER
OZ6933 209PIN CSP

B_D10/CAD31
B_D9/CAD30
B_D1/CAD29
B_D8/CAD28
B_D0/CAD27
B_A0/CAD26
B_A1/CAD25
B_A2/CAD24
B_A3/CAD23
B_A4/CAD22
B_A5/CAD21
B_A6/CAD20
B_A25/CAD19
B_A7/CAD18
B_A24/CAD17
B_A17/CAD16
B_IOWR#/CAD15
B_A9/CAD14
B_IORD#/CAD13
B_A11/CAD12
B_OE#/CAD11
B_CE2#/CAD10
B_A10/CAD9
B_D15/CAD8
B_D7/CAD7
B_D13/CAD6
B_D6/CAD5
B_D12/CAD4
B_D5/CAD3
B_D11/CAD2
B_D4/CAD1
B_D3/CAD0

C/BE#3
C/BE#2
C/BE#1
C/BE#0

C622
.1UF

B6
A6
B7
C7
A7
B8
A8
E9
B9
F10
E10
F11
C11
B11
A11
E14
D19
F15
E17
F14
G15
E19
F18
F17
G18
H15
H14
H17
H18
H19
J14
J17

16,20,21,27,28
16,20,21,27,28
16,20,21,27,28
16,20,21,27,28

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

IRQ3/VCC3#
SCLK/A_VCC_5#
SDATA/B_VCC_3#
SLATCH/B_VCC_5#
IRQ9/A_VPP_VCC
IRQ10/B_VPP_VCC

E1
E2
F3
F1
G5
H6
G3
G2
H2
H1
J1
J2
J3
J6
K1
K2
M5
N2
N1
N3
N6
P1
P3
N5
P6
R2
R3
T1
W4
R6
U5
P7

W12
K14
K15
K17
P19
F19

S1_IOWR# 23
S1_IORD# 23
S1_OE#
23
S1_CE2# 23

AUX_VCC

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

PCI

S1_IOWR#
S1_IORD#
S1_OE#
S1_CE2#

L15

.1UF

A_D10/CAD31
A_D9/CAD30
A_D1/CAD29
A_D8/CAD28
A_D0/CAD27
A_A0/CAD26
A_A1/CAD25
A_A2/CAD24
A_A3/CAD23
A_A4/CAD22
A_A5/CAD21
A_A6/CAD20
A_A25/CAD19
A_A7/CAD18
A_A24/CAD17
A_A17/CAD16
A_IOWR/CAD15
A_A9/CAD14
A_IORD#/CAD13
A_A11/CAD12
A_OE#/CAD11
A_CE2#/CAD10
A_A10/CAD9
A_D15/CAD8
A_D7/CAD7
A_D13/CAD6
A_D6/CAD5
A_D12/CAD4
A_D5/CAD3
A_D11/CAD2
A_D4/CAD1
A_D3/CAD0

C617

U49

C620
.1UF

+3VS

16,20,21,27,28 AD[0..31]

C607
.1UF

14,20,23,27,28

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

+3V

C616
4.7UF_10V_0805

S2_CE2#
S2_OE#
S2_IORD#
S2_IOWR#

S2_CE2# 23
S2_OE#
23
S2_IORD# 23
S2_IOWR# 23

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, M/B LA-1331

Size
Document Number
Custom
Date:

COMPAL ELECTRONICS, INC

Rev
2A

401207

, 18, 2004

Sheet
E

22

of

83

PCMCIA POWER CTRL.

CARDBUS
SOCKET

+5V
+3V

+12V

+S1_VPP

+S1_VPP

W=40mils

JP19

+S1_VCC

1
1
1
1
1
1
1

7
24

12V
12V

2 C177
.1UF
2 C179
.1UF
2 C178
.1UF
2 C170
.1UF
2 C172
.1UF
2 C171
.1UF

1
2
30

5V
5V
5V

15
16
17

3.3V
3.3V
3.3V

33

3
5
4

22
SLDATA
22
SLATCH
16,22,28 RTCCLK

13
19
18

OCCB#
+3V

AVPP
AVCC
AVCC
AVCC

8
9
10
11

BVPP
BVCC
BVCC
BVCC

23
20
21
22

RESET
RESET#

6
14

NC
NC
NC
NC

26
27
28
29

CBRST#

DATA
LATCH
CLOCK
APWR_GOOD#
BPWR_GOOD#
OC#

GND

C174

VCC_5V

22
22

4.7UF_10V_0805

+S2_VPP

S1_CD2#
S1_WP

+S2_VPP

W=40mils

+S2_VCC

25
C176
2 1UF_25V_0805

U15

C175

22

S1_BVD1

4.7UF_10V_0805
22

S1_BVD2

22

S1_REG#

22

S1_INPACK#

12

2
TPS2206AI/TPS2216
R162
100K

22

S1_WAIT#

22

S1_RST

22

S1_VS2

1
R322

CBRST#

CBRST#

14,20,22,27,28

+S1_VCC

+3V POWER

R323

1
R318

2
@0

S1_RDY#
S1_WE#

22

S1_IOWR#

22

S1_IORD#

C521

.01UF

1UF_25V_0805

22
22
22

S1_VS1
S1_OE#
S1_CE2#

22

S1_CE1#

W=30mils

+S1_VPP

22
22

+3V

W=30mils
C523

C522

C524
.01UF

S1_WAIT#
S1_A4
S1_RST
S1_A5
S1_VS2
S1_A6
S1_A25

S1_A16

2
G_RST#

S1_A0
S1_BVD2
S1_A1
S1_REG#
S1_A2
S1_INPACK#
S1_A3

+S1_VPP

U33A
74LVC125

10K

32

+S2_VPP

S1_A[0..25]
S1_D[0..15]
S2_A[0..25]
S2_D[0..15]

S1_A[0..25]
S1_D[0..15]
S2_A[0..25]
S2_D[0..15]

1UF_25V_0805

22

+S1_VCC

S1_CD1#

S1_A21
S1_RDY#
S1_A20
S1_WE#
S1_A19
S1_A14
S1_A18
S1_A13
S1_A17
S1_A8
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_VS1
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_CE1#
S1_D14
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_CD1#
S1_D3

a68
a34
a67
a33
GND
a66
a32
a65
a31
a64
a30
a63
GND
a29
a62
a28
a61
a27
a60
a26
GND
a59
a25
a58
a24
a57
a23
a56
GND
a22
a55
a21
a54
a20
a53
GND
a19
a52
a18
a51
a17
a50
a16
a49
a15
a48
a14
a47
a13
GND
a46
a12
a45
a11
a44
GND
a10
a43
a9
a42
a8
GND
a41
a7
a40
a6
a39
a5
GND
a38
a4
a37
a3
a36
a2
a35
a1

b68
b34
b67
b33
GND
b66
b32
b65
b31
b64
b30
b63
GND
b29
b62
b28
b61
b27
b60
b26
GND
b59
b25
b58
b24
b57
b23
b56
GND
b22
b55
b21
b54
b20
b53
GND
b19
b52
b18
b51
b17
b50
b16
b49
b15
b48
b14
b47
b13
GND
b46
b12
b45
b11
b44
GND
b10
b43
b9
b42
b8
GND
b41
b7
b40
b6
b39
b5
GND
b38
b4
b37
b3
b36
b2
b35
b1

B77
B76
B75
B74
B73
B72
B71
B70
B69
B68
B67
B66
B65
B64
B63
B62
B61
B60
B59
B58
B57
B56
B55
B54
B53
B52
B51
B50
B49
B48
B47
B46
B45
B44
B43
B42
B41
B40
B39
B38
B37
B36
B35
B34
B33
B32
B31
B30
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1

S2_CD2#
S2_WP

S2_CD2# 22
S2_WP
22

S2_D10
S2_D2
S2_D9
S2_D1
S2_D8
S2_D0
S2_BVD1

S2_BVD1 22

S2_A0
S2_BVD2
S2_A1
S2_REG#
S2_A2
S2_INPACK#
S2_A3
S2_WAIT#
S2_A4
S2_RST
S2_A5
S2_VS2
S2_A6
S2_A25

S2_BVD2 22
S2_REG# 22
S2_INPACK# 22
S2_WAIT# 22
S2_RST

22

S2_VS2

22

S2_A7
S2_A24
S2_A12
S2_A23
S2_A15
S2_A22
S2_A16
+S2_VPP
+S2_VCC
S2_A21
S2_RDY#
S2_A20
S2_WE#
S2_A19
S2_A14
S2_A18
S2_A13

S2_RDY# 22
S2_WE#

S2_A17
S2_A8
S2_IOWR#
S2_A9
S2_IORD#

22

S2_IOWR# 22
S2_IORD# 22

S2_A11
S2_VS1
S2_OE#
S2_CE2#
S2_A10
S2_D15
S2_CE1#
S2_D14
S2_D7
S2_D13
S2_D6
S2_D12
S2_D5
S2_D11
S2_D4
S2_CD1#
S2_D3

S2_VS1
S2_OE#
S2_CE2#

22
22
22

S2_CE1#

22

S2_CD1# 22

.1UF

C526

56PF

C527

C625
C528

C529
10UF_16V_1206

1000PF

S1_CD1# 1
@1000PF

+S2_VCC

PCMC154PIN

C486
S1_CD2# 1
@1000PF

C624
S2_CD1# 1
2
@1000PF

.1UF

56PF

C531

C532

C587
10UF_16V_1206

C530

C485

22
22
22
22

14

1
2
7,14,16,19,20,21,22,24,27,28,34 PCIRST#

PCMRST# 33

.1UF

S1_D10
S1_D2
S1_D9
S1_D1
S1_D8
S1_D0
S1_BVD1

S1_A7
S1_A24
S1_A12
S1_A23
S1_A15
S1_A22

+3V

C94

S1_CD2#
S1_WP

A77
A76
A75
A74
A73
A72
A71
A70
A69
A68
A67
A66
A65
A64
A63
A62
A61
A60
A59
A58
A57
A56
A55
A54
A53
A52
A51
A50
A49
A48
A47
A46
A45
A44
A43
A42
A41
A40
A39
A38
A37
A36
A35
A34
A33
A32
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1

1000PF

S2_CD2# 1
@1000PF

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

TRANSFERRED
SCHEMATIC, M/B LA-1331

Size
B

Document Number

Date:

, 18, 2004

FROM THE CUSTODY OF T

Rev
2A

401207
Sheet

23

of

83

.1UF
C276
1
2

U28

+3V
7,14,16,19,20,21,22,23,27,28,34 PCIRST#
LPCRST1

2
R251
10K

20
21
22
23

LAD0
LAD1
LAD2
LAD3

24
25

LFRAME#
LDRQ#

LPC_RST#

26
27

PCIRST#
LPCPD#

2
10K

CLK_LPC_SIO

50
17
30
28
29

GPIO12/IO_SMI#
IO_PME#
SIRQ
CLKRUN#
PCICLK

CLK_SIO14

19

CLK14

48
54
55
56
57
58
59
6
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

GPIO10
GPIO15
GPIO16
GPIO17
GPIO20
GPIO21
GPIO22
GPIO24
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47

51
52
64

GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO23/FDC_PP

18

VTR

53
65
93

VCC
VCC
VCC

7
31
60
76

VSS
VSS
VSS
VSS

16,32 LPC_FRAME#
16,18 LPC_DRQ#1
14,16,34 SUS_STAT#
+3VS
16,18,22,32 INT_SERIRQ
16,18,22,27,28,32 PM_CLKRUN#
13 CLK_LPC_SIO

13

CLK_SIO14

14
14
14
14

PID0
PID1
PID2
PID3

+3VS

1
R177
1
R178

1
R192

1
R3

1
R233

2
10K

2
10K

2
10K
2
10K

+3VS

CLK_LPC_SIO

2
2 1

C257
.1UF

C230

4.7UF_10V_0805 .1UF
10V

2 1

C232

C258

C209

@33

10

R211

R234

A1

A2

C277

1
R248

LPCRST

Y2

GND

D23
RB751V

2
10K

+3VS

LPC_RST#

LPC_RST# 32

.1UF

U24
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

15PF

Y1

LPC_AD[0..3]

16,32 LPC_AD[0..3]

CLK_SIO14

VCC

NC7WZ14

SUPER I/O SMsC FDC47N227

@22PF

C208
.1UF

PD0/INDEX#
PD1/TRK0
PD2/WRTPRT#
PD3/RDATA#
PD4/DSKCHG#
PD5
PD6/MTR0#
PD7

68
69
70
71
72
73
74
75

LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7

BUSY/MTR1#
PE/WDATA#
SLCT/WGATE#
ERROR#/HDSEL#
ACK#/DS1#
INIT#/DIR#
AUTOFD#/DRVDEN0#
STROBE#/DS0#
SLCTIN#/STEP#

79
78
77
81
80
66
82
83
67

LPTBUSY
LPTPE
LPTSLCT
LPTERR#
LPTACK#

DTR2#
CTS2#
RTS2#
DSR2#
TXD2
RXD2
DCD2#
RI2#

100
99
98
97
96
95
94
92

DTR1#
CTS1#
RTS1#
DSR1#
TXD1
RXD1
DCD1#
RI1#

89
88
87
86
85
84
91
90

IRMODE/IRRX3
IRRX2
IRTX2

63
61
62

RDATA#
WDATA#
WGATE#
HDSEL#
DIR#
STEP#
DS0#
INDEX#
DSKCHG#
WRTPRT#
TRK0#
MTR0#
DRVDEN0

16
10
11
12
8
9
5
13
4
15
14
3
1

DRVDEN1
GPIO11/SYSOPT

LPD[0..7]

LPTBUSY
LPTPE
LPTSLCT
LPTERR#
LPTACK#
INIT#
LPTAFD#
LPTSTB#
SLCTIN#

25
25
25
25
25
25
25
25
25

LPD[0..7] 25

RP9
DCD#1
RI#1
CTS#1
DSR#1

CTS#2

1
2
3
4

+3VS

8
7
6
5

RP10
CTS#2
DSR#2
DCD#2
RI#2

+3VS

1
2
3
4

8
7
6
5
2

DSR#2

DCD#2
RI#2

8P4R_4.7K

1
R206

2
1K

8P4R_4.7K
+5V
JP24

2
49

DTR#1
CTS#1
RTS#1
DSR#1
TXD1
RXD1
DCD#1
RI#1

1
R197

28
28
28
28
28
28
28
28

2
1K

IRMODE 25
IRRX
25
IRTXOUT 25
RDATA#
WDATA#
WGATE#
HDSEL#
FDD IR#
STEP#
DRV0#
INDEX#
DSKCHG#
WP#
TRACK0#
MTR0#

2
R232
1
R191

RDATA#
WDATA#
WGATE#
HDSEL#
FDDIR#
STEP#
DRV0#
INDEX#
DSKCHG#
WP#
TRACK0#
MTR0#
3MODE#

19
19
19
19
19
19
19,33
19
19
19
19
19
19

1
10K
2
1K

+5VS

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7
8
9
10
@96212-1011S

Base I/O Address

* 0 = 02Eh
1 = 04Eh

SMsC LPC47N227

COMPAL ELECTRONICS, INC

Title
PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

SCHEMATIC, M/B LA-1331

Document Number

Rev
2A

401207
, 18, 2004

Sheet
E

24

of

83

FIR Module
2

+3VS

C190

1
R2

2
3.3_1206

1
R1

2
@3.3_1206

+IR_ANODE

4.7UF_1206

+3VS

2
R164

R163
47_1206

1
@ 10K
2

1UF_0805

24

IRRX

IRRX

1
2

+IR_ANODE

IRED Anode

Txd

IRTXOUT

SD/Mode

IRMODE

Mode

IRED Cathode
Rxd
Vcc

IRTXOUT 24
IRMODE

24

GND

.1UF
FIR TFDU6101E

+IR_GND

SD/MODE: SHUTDOWN MODE, HIGH ACTIVE

MODE: HIGH/LOW SPEED SELECT

+5V_PRN

PARALLEL PORT

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

10
9
8
7
6

+5V_PRN
CP2
RP4
10P8R_2.7K

D3
+5VS

1
RB420D

1
2
3
4
5

100PF

4
6

C4

+5V_PRN
24

AFD#/3M#
LPTERR#
LPTINIT#
LPTSLCTIN#

LPTSTB#

24

INIT#

24

SLCTIN#

R171
33
2

+5V_PRN

LPTINIT#

24

LPTAFD#

24

LPTERR#

LPTSLCTIN#

F D4

RP7
LPD0
LPD1
LPD2
LPD3

RP5
10P8R_2.7K

LPD7
LPD6
LPD5
LPD4

+5V_PRN
F D3
F D2
F D1
F D0

F D0
LPTERR#
F D1
LPTINIT#
F D2
LPTSLCTIN#
F D3

1
2
3
4

8
7
6
5

1
2
3
4

8P4R_68
RP6
8
7
6
5

F D0
F D1
F D2
F D3

F D5
F D6
F D7

F D7
F D6
F D5
F D4

24

LPTACK#

24

LPTBUSY

24

LPTPE

24

LPTSLCT

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

R170
2.2K

C186
220PF

R169

AFD#/3M#
LPTERR#
LPTINIT#
LPTSLCTIN#

1
2
3
4

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

4
3
2
1

8P4C_220PF
CP1
5
6
7
8

F D0
F D1
F D2
F D3

1
2
3
4

8P4C_220PF
CP4
8
7
6
5

F D4
F D5
F D6
F D7

1
2
3
4

8P4C_220PF
CP3
8
7
6
5

33
R168

R172
33

F D4
F D5
F D6
F D7

LPTSTB#

AFD#/3M#

10
9
8
7
6

C1

1
2
3
4
5

+IR_VCC

U1
C188

33

1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13

8
7
6
5

8P4C_220PF
JP4
LPTCN-25

8P4R_68

24

LPD[0..7]

LPD[0..7]

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

Size

TRANSFERRED FROM THE CUSTODY OF T

Document Number

Rev
2A

401207
Date:

, 18, 2004

Sheet

25

of

83

USB PORT

+USB_VCCA

F4

+USB_VCCC

F2

150UF_D2_6.3V

150UF_D2_6.3V

POLYSWITCH_0.75A

C413

.1UF

R176

R180

1000PF

560K

C204

JP9

L5
FBM-11-160808-121
1
2
1
2
L4
FBM-11-160808-121
C103

1
2
3
4

C96

17
17

USB3_DUSB3_D+

USB_PN3
USB_PP3

L22
FBM-11-160808-121
1
2
1
2
L21
FBM-11-160808-121

C211

C212

47PF

.1UF

C203

.1UF

1
1

L16
CHB4516G750_1806
4516

C391

47PF

+USB_VCCB

F3

150UF_D2_6.3V

+5V

R186

POLYSWITCH_0.75A

C205

C217

.1UF

470K

USB_BGND

USB_OC#1

1
C206

R187

JP1

1000PF

560K

1
2
3
4
5
6
7
8

USB_PN1
USB_PP1

USB1_DUSB1_D+

1
1

2
2
L18
FBM-11-160808-121

C207

L17
CHB4516G750_1806

17
17

C193
47PF

L19
FBM-11-160808-121

17

L38
CHB4516G750_1806
4516

47PF

SUYIN USB Connector 2569A-04G3T-B

47PF

560K

USB_PN0
USB_PP0

USB_CGND

1
R321

1000PF

C408

2
17
17

USB_OC#3

17

USB0_DUSB0_D+

C199

.1UF

470K

USB_OC#0

17

C195

USB_AGND

470K

C400

R324

POLYSWITCH_0.75A

+5V

+5V

SUYIN 2553A-0BG5T-A
C194
47PF

.1UF

4516

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

Size
B

Document Number

Date:

, 18, 2004

TRANSFERRED FROM THE CUSTODY OF T

Rev
2A

401207
Sheet

26

of

83

Q38
@SI2301DS

+3V
+5VS_MINIPCI

1
R153
1
R151

PCIRST#
2
0
2
@0

PCIRST#

7,14,16,19,20,21,22,23,24,28,34

CBRST#

14,20,22,23,28

C136
@1000PF

C138
@.1UF

MINI_RST#

C456
@1UF_25V_0805

C491
@1UF_25V_0805

R366

1
1

+3.3VAUX

+3VALW

C168
C142
@10UF_16V_1206

@.1UF

R420

EN_WOL#

+5VALW

@100K

+3V
C126

1
LAN RESERVED

7SH08FU

L12

***

@.1UF

C165

REQ#4

16,18 REQ#4

C146

CLK_MINIPCI

13 CLK_MINIPCI

.1UF

REQ#1

16,18 REQ#1

AD31
AD29

16,20,21,22,28 AD31
16,20,21,22,28 AD29
AD27
AD25

16,20,21,22,28 AD27
16,20,21,22,28 AD25

CLK_MINIPCI

1 2

R156
@10

C139
@33PF

PIRQD#

16,18,28 PIRQD#

W=40mils

1
CHB1608B121
0603

D42
RB751V

C/BE#3
AD23

16,20,21,22,28 C/BE#3
16,20,21,22,28 AD23

AD21
AD19

16,20,21,22,28 AD21
16,20,21,22,28 AD19

AD17
C/BE#2
IRDY#

16,20,21,22,28 AD17
16,20,21,22,28 C/BE#2
16,18,20,21,22,28 IRDY#

PM_CLKRUN#
SERR#

16,18,22,24,28,32 PM_CLKRUN#
16,18,20,22 SERR#

PERR#
C/BE#1
AD14

16,18,20,21,22 PERR#
16,20,21,22,28 C/BE#1
16,20,21,22,28 AD14

AD12
AD10

16,20,21,22,28 AD12
16,20,21,22,28 AD10

AD8
AD7

16,20,21,22,28 AD8
16,20,21,22,28 AD7

AD5

16,20,21,22,28 AD5

AD3

16,20,21,22,28 AD3
+5VS_MINIPCI
16,20,21,22,28 AD1

+5VS

1
L10

2
0_0603
0603

+5VS_MINIPCI

W=30mils
AD1

W=30mils

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123

1
KEY
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123

2
KEY
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

C141
10UF_16V_1206

@.1UF

LAN RESERVED

W=30mils
PIRQC#

+5VS_MINIPCI
PIRQC# 16,18,28
GNT#4
16,18
+3.3VAUX

W=40mils
MINI_RST#

+3VS_MINIPCI
L11
W=40mils

GNT#1

16,18

WLANPME# 32

.1UF

AD30

MINI_IDSEL
1
R35
AD22
AD20
PAR
AD18
AD16

AD28
AD26
AD24
AD18
2
100

FRAME#
TRDY#
STOP#
DEVSEL#
AD15
AD13
AD11
AD9
C/BE#0
AD6
AD4
AD2
AD0

W=20mils

1
C144

AD30

16,20,21,22,28

AD28
AD26
AD24

16,20,21,22,28
16,20,21,22,28
16,20,21,22,28

AD22
AD20
PAR
AD18
AD16

16,20,21,22,28
16,20,21,22,28
16,18,20,21,22,28
16,20,21,22,28
16,20,21,22,28

FRAME#
TRDY#
STOP#

16,18,20,21,22,28
16,18,20,21,22,28
16,18,20,21,22,28

KILL_SW

C164

RING

+3V

C153 CHB1608B121
0603
.1UF

DEVSEL# 16,18,20,21,22,28
AD15
AD13
AD11

16,20,21,22,28
16,20,21,22,28
16,20,21,22,28

AD9
C/BE#0

16,20,21,22,28
16,20,21,22,28

AD6
AD4
AD2
AD0

16,20,21,22,28
16,20,21,22,28
16,20,21,22,28
16,20,21,22,28

+3.3VAUX

TIP

+3VS_MINIPCI

+3V

***

JP18

33,34

.1UF

WL_OFF#

C143

Mini-PCI SLOT

33

+3VS_MINIPCI

U13

11,32

.1UF

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

Size
B

Document Number

Date:

, 18, 2004

TRANSFERRED FROM THE CUSTODY OF T

Rev
2A

401207
Sheet

27

of

83

@.1UF

INPUT OUTPUT

+SMC_VCC

5
3

VCC
GND

SM_LED

.1UF

NC

6
17
28
39
49
60
70
81
92
103
113
124

+SMC_VCC
+SMC_VCC

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

+3V

FCMODE

2
10K

1
R372

2
@10K

2
22

1
R328

C433

+3V

10PF

IDSEL0

16,20,21,22,27 C/BE#0
16,20,21,22,27 C/BE#1
16,20,21,22,27 C/BE#2
16,20,21,22,27 C/BE#3
16,18,20,21,22,27 PAR
16,18,20,21,22,27 FRAME#
16,18,20,21,22,27 IRDY#
16,18,20,21,22,27 TRDY#
16,18,20,21,22,27 STOP#
AD22
AD22

+3V

2 IDSEL1
@100K

1
R349

14,20,22,23,27 CBRST#

1
R104

7,14,16,19,20,21,22,23,24,27,34 PCIRST#

PCTRST#1
R105

R335 1
1
R350

16,18,22,24,27,32 PM_CLKRUN#
16,18,20,21,22,27 DEVSEL#
13 CLK_PCI_SD/SM
2
0
16,18,27 PIRQC#
16,18,27 PIRQD#
2
32 SM/SD_PME#
@0

1
1
1
1
1

CLK_PCI_SD/SM

2
2
2
2
2
1
R371

100K
100K
100K
100K
100K
0

SDCD0
SDCD1
SDCD2
SDCD3
SDCMD
2

13
120

IDSEL0
IDSEL1

55
27
125
123
121
122
128

CLKRUN#
DEVSEL#
PCICLK
PCIRST#
INTA#
INTB#
PME#

101
102
83
85
89
98
104
105
69

SDCD0
SDCD1
SDCD2
SDCD3
SDCMD
SDCLK
SDCD#
SDWP
SDPWR

CLK32
PWRST#
SUSPEND#
FCMODE
ROM_CS
ROM_SK
ROM_D

59
56
57
58
68
67
66

SMD0
SMD1
SMD2
SMD3
SMD4
SMD5
SMD6
SMD7
SM_CLE
SM_ALE
SM_CE#
SMWE#
SM_RE#
SM_WP#
SM_R/B#
SMCD#
SM_LVD
SMWPD#
SMEJSW#
R395 1
R373 1
R403 1
SMVC3EN

GND

C494
0.1UF

C481

C452

1000PF

10UF_16V_1206

R311

RT9701-CB

1K
2

SMD0
SMD1
SMD2
SMD3
SMD4
SMD5
SMD6
SMD7
SMCLE
SMALE
SMCE#
SMWE#
SMRE#
SMWP#
SMRB#
SMCD#
SMLVD
SMWPD#
SMEJSW#
SMLED#
SMLOCK#
SMEJCT#
SMVC3EN
SMVC5EN

86
90
93
95
99
96
94
91
75
78
77
80
79
84
82
100
88
73
74
107
109
106
72
71

SMCD# 1
R423

C496 @1000PF
1
2

SMEJSW#

+3V

2 100K
2 100K
2 100K

1
R422

2
100K

JP14
12
11
13
10
14
9
15
8
16
7
17
6
18
5
19
4
20
3
21
2
22
1
23
24

SMCD#
SMD4
SMD5
SMD3
SMD6
SMD2
SMD7
SMD1
SM_LVD
SMD0

+3V
+3V
+3V

SM_WP#
SM_R/B#
SMWE#
SM_RE#
SM_ALE
SM_CE#
SM_CLE
+SMC_VCC

PWRST#
SUSP#
FCMODE

RTCCLK

16,22,23

SUSP#

29,32,36,40,41

+3V

1
R136

2
10K

SMWPD#

SmartMedia Slot
1
R296

2
100K

+3V

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7

110
111
112
114
115
116
117
119

NC
NC

126
127

R368
R369
R363
R364
R358
R359
R353
R354

1
1
1
1
1
1
1
1

100K
100K
100K
100K
100K
100K
100K
100K

2
2
2
2
2
2
2
2

SMD0
SMD1
SMD2
SMD3

+3V
+3V

When the serial

ROM interface is
not applied need
pull up.

+3V

1
2
3
4

8
7
6
5

8P4R_100K*
RP80
SMD4
SMD5
SMD6
SMD7

1
2
3
4

8
7
6
5

8P4R_100K*
RP77
SM_CLE
SM_ALE
SM_WP#
SM_LVD

TEST0
TEST1
TEST2
TEST3

61
62
63
64

1
R383

1
2
3
4

8
7
6
5

8P4R_100K*

GND

+3V

1
2
3
4

SM_R/B#

1
R365

+3V

8
7
6
5

TXD1
RTS#1
RI#1
COM_RI#

8P4R_100K*
+3V

R319
@10K
TXD1
RTS#1
RI#1

24
24
24

22

PCM_RI#

R320
@10K
D34

RING#

@RB751V
COM_RI#

@SD/COM

TC6371AF

+5V

SDCD1
SDCD3
SDCLK
SDWP
SDLED

SM_CE#
SMWE#
SM_RE#

2
10K

RXD1
DSR#1
CTS#1
DTR#1
DCD#1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

RP78

24
24
24
24
24

RXD1
DSR#1
CTS#1
DTR#1
DCD#1
SUSP#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

1
12
23
33
44
54
65
76
87
97
108
118

JP15
SDCD0
SDCD2
SDCMD
SDCD#
SDPWR

+SMC_VCC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SD Transfer Conn.

VCC
PCD#
I/O4
VSS
I/O5
I/O3
I/O6
I/O2
I/O7
I/O1
LVD
I/O0
GND
WP#
RDY
WE#
RD#
ALE
CE#
CLE
VCC
VSS
GND
WPRO#

RP79

SD CARD I/F

+3V

R384
R412
R385
R396
R370

IDSEL0
IDSEL1

2 @100
2
100

PCI I/F

1
R382

CLK_PCI_SD/SM 1
R343

+3V

SmartMedia I/F

1
R352

System I/F

1
0.1UF

GPIO I/F

2
C447

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
PAR
FRAME#
IRDY#
TRDY#
STOP#

Test Pins

PWRST#

53
52
51
50
48
47
46
45
42
41
40
38
37
36
35
34
22
21
20
19
18
16
15
14
10
9
8
7
5
4
3
2
43
32
31
11
30
24
25
26
29

1
5

VIN
VOUT
VIN/CE VOUT

3
4

SMVC3EN

U43

Power
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE#0
C/BE#1
C/BE#2
C/BE#3

Q26
DTC114YKA

47K

AD[0..31]

16,20,21,22,27 AD[0..31]

+5VS

1
110

1K

U37

2
R314

10K
SM_LED
R299

@NC7S14

D37
HSMB-C110 BLUE

34

C478

.1UF 1000PF

SM_LED

+3V

C479

C437

.1UF 1000PF

C462

.1UF

C458

C450

.1UF 1000PF

C442

C424

1
2

.1UF 1000PF
2

1
2

C425

1
C423

1
U31

C370

+3V

+3V

R292 @1M
2

32

Q27
@2N7002

2
G

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

TRANSFERRED FROM THE CUSTODY OF THE COM

Size
Document Number
Custom

Rev
2A

401207

Date:

, 18, 2004

Sheet

28

of

83

**

1
R329

33,34 STOPBTN#

2
0

D36

+5VOZ

33 CD_STOPBTN#

OZ_STOPBTN#

2
@RB751V

X3
OSC1

OSC2

HCS0
HCS1

CCS0
CCS1

64
62

CD_SCS1#
CD_SCS3#

HDIOR#
HDIOW#
HIOCS16#
HIORDY

CDIOR#
CDIOW#
CIOCS16#
CIORDY

100
5
73
94

CD_SIOR#
CD_SIOW#
CIOCS16#
CD_ SIORDY

HINTRQ
HDMARQ
HDMACK#

CHINTRQ
CDMARQ
CHDMACK#

75
13
89

CD_IRQ
CD_DREQ
CD_DACK#

24
59

HRESET#
HDASPN

CRESET#
CDASPN

23
60

48
53
55
50
46

HSYNC
HBIT_CLK
HDATA_OUT
HDATA_IN
HACRSTN

SSYNC
SBIT_CLK
SDATA_OUT
SDATA_IN
SACRSTN

47
52
54
49
45

IDE_SDIOR#
IDE_SDIOW#

IDE_SDIOR#
IDE_SDIOW#

17

IDE_SIORDY

99
6
72
93

16,18 INT_IRQ15
17 IDE_SDDREQ
17 IDE_SDDACK#

74
IDE_SDDREQ 12
IDE_SDDACK# 88

DM_ON
PLAYBTN#
FRDBTN#
REVBTN#
OZ_STOPBTN#

PLAYBTN#
FRDBTN#
REVBTN#

10UF_16V_1206
10K

33

DM_ON
INTN

CD_INTA#

58

63
61

IDE_SDCS1#
IDE_SDCS3#

17
17

C407
10PF

44

CD_SBA0
CD_SBA1
CD_SBA2

IDE_SDCS1#
IDE_SDCS3#

SIDE_RST#

VDD

69
71
67

17
17

34
34
34

28
36
35
34
37
29
25
30

PAV_EN
PLAY/PAUSE
FFORWARD
REWIND
STOP/EJECT

PWR_CTL

PCSYSTEM_OFF
INTN
RESET#

D1

5,32

EC_SMD2

S1
1
Q31A
SI1906DL

26

SDATA

27

SCLK

G2

+5VALW
1

+5VCD

+5VALW

31
32

OSCI
OSCO

R119
200K

8P4R_10K
RP24
GPIO_0
GPIO_1
INTN

CD_SIORDY 19

1
2
3
4

8
7
6
5

8P4R_10K

CD_IRQ 19
CD_DREQ 19
CD_DACK# 19

RP23
PLAYBTN#
REVBTN#
FRDBTN#
STOPBTN#

CD_RSTDRV# 19

2
@10K
2
10K

56
57

R344
@1K
1
2
MODE1

+5VCD

1
R400

ISCDROM

R399

2
@0

MEDIA_DETECT 33
R249
100K

1
2
3
4

1
R332

2
@10K

1
R331

2
10K

CDD3
CDD1
CDD2
CDD0
CDD4
CDD6
CDD5
CDD7

1
2
3
4
5
6
7
8

CDD8
CDD9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15

8
7
6
5
4
3
2
1

8
7
6
5

STUFF
R399, R249
R400

RP25

CHIP
OZ165
0Z168

+5VCD

9
10
11
12
13
14
15
16
@16P8R_4.7K

Select SM BUS ADDRESS

STUFF

SMBus ID

R331
R332

B4h
34h

16
15
14
13
12
11
10
9
@16P8R_4.7K

Select OZ165 / OZ168

+5VCD

100K

C417
1UF_25V_0805

CIOCS16#

1
R393

2
47K

+5VMOD

+5VCD

U34
1
2
3
4

+5VALW
R109
1

R336
200K

R339
C414
10UF_16V_1206

OSC1
OSC2

Q31B
SI1906DL

4 S2

16
33
65
85
92

D2 3

EC_SMC2

5,32

1
R334
1
R340

GPIO_1
GPIO_0

38

8
7
6
5

@8P4R_10K

80

41
42
43

1
2
3
4

RP81

39
40

CSN
INCN
UDN

RP76
ISCDROM
CD_IRQ
CDASPN
MODE1

CD_SIOR# 19
CD_SIOW# 19

CD_RSTDRV#
CDASPN

ISCDROM

PAVMODE

+5VCD

C420
.1UF

CD_SCS1# 19
CD_SCS3# 19

GND
GND
GND
GND
GND

G1

RB751V

C473
.1UF

+5VCD

GPIO[1]/VOL_UP
GPIO[0]/VOL_DN
MODE0
MODE1

D39

51

C419
.1UF

CD_SBA0 19
CD_SBA1 19
CD_SBA2 19

240K
2

S
S
S
G

D
D
D
D

8
7
6
5

C403

C109
.1UF

10UF_16V_1206
+5VCD
+5VCD

SI4425DY
C412
1

CD_PLAY

22K

DM_ON#

CD_PLAY 33

DM_ON#

30

Q19
DTC124EK

DM_ON 5
G2

DM_ON

30

D2

Q21
DTC124EK

DM_ON

22K

Q5B
SI1906DL

SUSP#
2
G1

Q5A
SI1906DL
1

22K
22K

R333
100K

R126
100K

SUSP#

10K

D1

28,32,36,40,41 SUSP#

R111

1UF_25V_0805

2
1

S1

+5VCD

CDA0
CDA1
CDA2

68
70
66

1M

C402
R330
1

HDA0
HDA1
HDA2

IDE_SDA0
IDE_SDA1
IDE_SDA2

IDE_SDA0
IDE_SDA1
IDE_SDA2

19

C404
10PF

CDD0
CDD1
CDD2
CDD3
CDD4
CDD5
CDD6
CDD7
CDD8
CDD9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15

17
17
17

8MHZ
R337

C440
.1UF

77
79
82
84
87
91
96
98
1
3
7
10
14
17
19
21

HDD0
HDD1
HDD2
HDD3
HDD4
HDD5
HDD6
HDD7
HDD8
HDD9
HDD10
HDD11
HDD12
HDD13
HDD14
HDD15

IDE_SDD[0..15] 17

U39
OZ165/OZ168

CDD0
CDD1
CDD2
CDD3
CDD4
CDD5
CDD6
CDD7
CDD8
CDD9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15

76
78
81
83
86
90
95
97
2
4
8
11
15
18
20
22

CDD[0..15] 19

IDE_SDD[0..15]

VDD

IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15

VDD

9
CDD[0..15]

CHB1608U301
1
2
L44
1
2
L45
CHB1608U301

+5VOZ

S2

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

TRANSFERRED
SCHEMATIC, M/B LA-1331

Size
Document Number
Custom
Date:

, 18, 2004

FROM THE CUSTODY OF THE COMPETEN

Rev
2A

401207
Sheet

29

of

83

AC97 Codec
C498

DELAY

SENSE

ERROR

CNOISE

GND

ON/OFF#

Q34
2N7002

C410

1 1

LEFT

Q35
2N7002
input to AMPLIFY

1UF_25V_0805

.1UF

+VDDA

4.7UF_10V_0805
C502

C427

R_INT_CD_R

19 INT_CD_R

SI9182
.1UF

DM_ON

29 DM_ON

R431
22K

+5VAMP_PU
R432
10K
2
2

R_INT_CD_L

1 1

+3VS

3
Q42
2N7002

1UF_25V_0805

Q50
2N7002

R435
@10K

RIGHT

Q43
2N7002

C434

R_INT_CD_L

19 INT_CD_L

+VDDA

1 1

CDROM_L

Q45
2N7002

VOUT

VIN

1
2

C416
4.7UF_10V_0805

U35

+5VS

+5VS

C501
10UF_10V_1206

input to CS 4297A

+AVDD_AC97

R433
10K

CHB2012U170
+VDDC

DM_ON#

MIC1

22

MIC2

13

PHONE

12

PC_BEEP

XTL_IN

1
2
R345 @ 10K

IAC_SDATAI0 16

Y3
24.576MHz

R346
@ 1M

XTL_OUT

AFLT1

29

AFLT2

30

VREFOUT

28

REFFLT

27

FLT3D

32

BPCFG
FLTI
FLTO
NC
NC

31
33
34
43
44

NC
AGND
AGND

40
26
42

RESET#
SYNC

1
C445

2
1000PF NPO
1
2
C449
1000PF
NPO

C439
NPO
22PF

1
R379

C435
NPO
22PF

+AUD_VREF

SDATA_OUT
ID0#
ID1#

47

EAPD#

48

S/PDIF_OUT

GND
GND

C441 @ 1000PF
AGND

C428
1UF_0805

C106
1UF_0805

C444
.01UF

C448
.1UF

C455
1UF_25V_0805

C438

+AUD_VREF

1UF_25V_0805
L46
1
2
CHB2012U170
L41
1
2 AGND
CHB2012U170

ALC101/201

DGND

DGND

C461
4.7UF_10V_0805

AGND

R401

**

.1UF

CD_GNA

1
R402
6.8K

AGND

C460

CD_AGND

R430
0

Compal Electronics, Inc.

6.8K

Title

19

14.318MHz External
24.576MHz Crystal
or External Colck

R348
2 22

CD_GNA

21

SDATA_IN

IAC_BITCLK 14,16

22
2

19

R341
1

CD_R

CD_L

20

BIT_CLK

14

18

4
7

R338
@0

LIN_IN_R

45
46

MODE

VCC

24

No-Stuff

VCC

41

14,16 IAC_SDATAO

Stuff

38

39

HP_OUT_R

10

R740

25

HP_OUT_L

LIN_IN_L

14,16 IAC_SYNC

EAPD

AVCC

VIDEO_R

23

11

31

17

31

MD_MIC

1
100

VIDEO_L

CDROM_R

Q46
2N7002

31

RIGHT

2
R356

IAC_RST#

37

16

LEFT

RIGHT

MONO_IN

MONO_OUT

AUX_R

LEFT

31

2
R387
2
R376

MD_SPK

14,16

MIC

MIC

14

1
20K
1
20K

LINE_OUT_R

LINER

31

2
R390
2
R391

36

15

CDROM_R

LINEL

CDROM_L

1
2
C470
1UF_25V_0805
1
2
C465
1UF_25V_0805
CD_L_R 1
2
C464
1UF_25V_0805
CD_R_R 1
2
C467
1UF_25V_0805
CD_GNA 1
2
C471
1UF_25V_0805
1
2
C463
1UF_25V_0805
1
+AUD_VREF
2.4K
1
1
2
10K
C466
1UF_25V_0805

35

LINE_IN_R

LINE_OUT_L

AUX_L

31

.1UF

1
6.8K
1
6.8K
1
6.8K
1
6.8K

14

LINE_IN_L

2
R404
2
R394
2
R389
2
R392

C457

C432
1 1000PF
C436
2 1000PF
C431
2 4.7UF_10V_0805
C430
2 4.7UF_10V_0805
C411
2 1UF_25V_0805
C418
1 1000PF

31

1
6.8K
1
6.8K

AVCC

2
R405
2
R367

C429
10UF_1206
29 DM_ON#

U38

1 1

.1UF

10UF_1206

C443

3
Q47
2N7002

R434
@10K

+3VS

C459

1
2

1
2

.1UF

R_INT_CD_R

+VDDC

+AVDD_AC97
C426

+5VAMP_PU

L39

+VDDA

PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:

SCHEMATIC, M/B LA-1331

Document Number

Rev
2A

401207
, 18, 2004

Sheet

30

of

83

+5VCD

AMP & Audio Jack

+5VCD

Q48
INTSPK_R2 1
U42

.47UF_0603

C483

1
1

INTSPK_L2 1

DTC314TK

2 1

R428

10K

2
Q41

.47UF_0603

C497
4.7UF_10V_0805

10K

C488

.47UF_0603

33

33

JP20

TPA0132

.047UF_0805

@.1UF
JP16
INTSPK_R1
INTSPK_R2
INTSPK_L1
INTSPK_L2

30

LINE_IN_R

30

LINE_IN_L

FBM-11-160808-700T
1
2
L47
1
2
L48
FBM-11-160808-700T

1
2
3
4

LINE_IN JACK

3
6
2
1
C606

C511 .47UF_0603

DTC314TK

C499

2
2

DAN217

C601
PHONEJACK

330PF

17

C495

.47UF_0603

+5VCD

R427
C492

DTC314TK

C510
C476 .47UF_0603
1
2

1
100K

INTSPK_L1 1

1
12
13
24

R419 2.2K

R421
C490
4.7K
10UF_16V_1206

33

Q40

2
R425

RIGHT

U3-5
U3-23
U3-6
U3-20

NBA_PLUG
C505 1
2
.1UF
INTSPK_L2
INTSPK_R2

30

VOL_OP
INTSPK_L1
INTSPK_R1
1
2
C484 .47UF_0603
2

2
3
4
21
5
23
6
20

22
15
14
11
9
16
10
8
1

LEFT

PVDD SHUTDOWN#
PVDD
SE/BTL#
VDD
PC-BEEP
BYPASS
PC-ENABLE LOUTVOLUME
ROUTLOUT+
LIN
ROUT+
RIN
LLINEIN
RLINEIN
GND
LHPIN
GND
RHPIN
GND
GND
CLK

30

7
18
19

100K

R429

1
R416
1

+5VCD

R415
10K

10K

33

2.2K

1 2

R424

INTSPK_R1 1

R413

1
1

30

3
1

2
EAPD

3
2SB1188

DTC314TK

Q29
2N7002

4.7UF_10V_0805

Q49

EC_AMPPD# 33

10K

1
1

C480

2
@0

.1UF

1
R469

R414
1.65K
2

C468

2 Q39

**

SHUTDOWN#

W=40Mil

C482
@1000PF

VOL_AMP 32

D41

+5VCD

VOL_OP

U41

LM7111

R386
100K

330PF

ACES 85205-0400

JP23

1
R458
NBA_PLUG

+VDDA
C415
2

R380
10K

C477
10UF_16V_1206
+AVDD_AC97

+AVDD_AC97

1
2

Q44
2SC2411K

**

+3V

C516
1UF_10V_0603

R454

2.2K

2.2K

4
1

C451
2

R378

1UF_10V_0603
+3V POWER

560

30

JP21

R388
10K

1
2
L49
FBM-11-160808-700T

D33
RB751V

EXT.
MICPHONE
JACK

3
6
2
1
PHONEJACK

C629
220PF

MIC

MIC

ICH_SPKR

R465

U32B
74LVC14

14

R445
100K_1%

1
R440
18K_1%

R397
2.4K

Q32
2SC2411K

1UF_10V_0603 560

MONO_IN 30

1UF_10V_0603

R441
18K_1%
1

MONO_IN

R377

C454
2

C453
2

PCM_SPK#

17

330PF

+3V POWER

22

C635

560

.22UF_0603

C401

R303

1UF_10V_0603

+3V POWER

C392
2

SPEAKER OUT JACK

3
6
2
1

2
8.2K

330PF

1
R317

PHONEJACK

R375
10K

U32A
74LVC14

14

C493
150UF_6.3V_D2

L50
1
2 INTSPK_R1-3
FBM-11-160808-700T
1
2 INTSPK_L1-3
L51
FBM-11-160808-700T
C636

2
47
2
47

.1UF
U33B
74LVC125

INTSPK_L1 1

R316
100K

1
R463
1
R464

BEEP#

INTSPK_R1 1

32

+3V

2
1K

+3V

+ +

C500
150UF_6.3V_D2

COMPAL ELECTRONICS, INC

Title
PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

SCHEMATIC, M/B LA-1331

Document Number

Rev
2A

401207
, 18, 2004

Sheet
E

31

of

83

1
RB751V

D19

21

1394_PME#

22

PCM_PME#

+3VALW

27

WLANPME#

LAN_PME#

G_RST#
EC_SWI#

VGA_SUSP#

40

BATT_TEMPA

38

BATT_OVP

BATT_TEMPA
BATT_TEMPB

ALI/MH#
BATT_CHGI
ADP_I

D12
1

16 ICH_WAKE_UP#

23
18

40

18,34
ON/OFF
16 PM_SLP_S5#

RB717F

ECAGND

EC_SMI#

VBATTB
RB717F
D21

20

18

13,16 PM_SLP_S1#

R240 10K

D20

**

PACIN
RING#

RB751V
2

OEM
OEM
PCI_PME#
14
31
38
34

BATT_TEMPA
2
.01UF
BATT_TEMPB
2
.01UF

1
C386
1
C387

+3VALW
RP16
1
2
3
4

DAC_BRIG
VOL_AMP
IREF
EN_DFAN
EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS

16,24 LPC_AD[0..3]

8P4R_10K

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
16,24 LPC_FRAME#
16,18 LPC_DRQ#0
16,18,22,24 INT_SERIRQ
34

1
R267

1
R226
1
R225

81
82
83
84

AD0
AD1
AD2
AD3

87
88
89
90
2
44

IOPE0AD4
IOPE1/AD5
IOPE2/AD6
IOPE3/AD7
IOPE4/SWIN
IOPE5/EXWINT40

93
94

DP/AD8
DN/AD9

99
100
101
102

DA0
DA1
DA2
DA3

105
106
107
108
109

TINT#
TCK
TDO
TDI
TMS

15
14
13
10

LAD0
LAD1
LAD2
LAD3

18

EC_SMC2
2
4.7K
EC_SMD2
2
4.7K

@0

9
8
7

51RST# 19
22
23
24
25

EC_RST#

34
LPCPD#
16,18,22,24,27,28 PM_CLKRUN#

+5VALW

IOPJ2/BST0
IOPJ3/BST1
IOPJ4/BST2
IOPJ5/PFS#
IOPJ6/PLI
IOPJ7/BRKL_RSTO#

95

34
45
123
136
157
166

161
VBAT

IOPL0/A16
IOPL1/A17
IOPL2/A18
IOPL3/A19
IOPL4/WR1#

113
112
104
103
48

KBA16
KBA17
KBA18
KBA19

IOPI0/D0
IOPI1/D1
IOPI2/D2
IOPI3/D3
IOPI4/D4
IOPI5/D5
IOPI6/D6
IOPI7/D7

138
139
140
141
144
145
146
147

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

IOPJ0/RD#
IOPJ1/WR0#

150
151

FR D#

SELIO#

152

SELIO#

SEL0#
SEL1#

173
174

FSEL#

IOPM0/D8
IOPM1/D9
IOPM2/D10
IOPM3/D11
IOPM4/D12
IOPM5/D13
IOPM6/D14
IOPM7/D15

148
149
155
156
3
4
27
28

SYSON
SUSP#
MMO_ON

PSCLK1/IOPF0
PSDAT1/IOPF1
PSCLK2/IOPF2
PSDAT2/IOPF3
PSCLK3/IOPF4
PSDAT3/IOPF5
PSCLK4/IOPF6
PSDAT4/IOPF7

110
111
114
115
116
117
118
119

KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA
TP_CLK
TP_DATA

KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

71
72
73
74
77
78
79
80

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15

49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

32KX1/32KCLKOUT

158

C RY1

32KX2

160

C RY2

LPC_AD[0..3]

G_RST#
FR D#
SELIO#
FSEL#

8
7
6
5

62
63
69
70
75
76

KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15

EC_SCI#

G20
RCL#

31
5
6
18

13 CLK_LPC_EC

LREST#
SMI#
PWUREQ#
IOPE6/LPCPD#/EXWIN45
IOPE7/CLKRUN#/EXWINT46
IOPD3/ECSCI#
GA20/IOPB5
KBRST#/IOPB6
LCLK

CLK

1
C350

2
1
@22PFR281

2
@33

1
R236

MMO_ON
FRD#
FWR#

33
33

SELIO#

33

FSEL#

33

SYSON
SUSP#

36,41
28,29,36,40,41

2
10K

+3VS

VR_ON

D22

RB751V

2
R255

1
10K

ATFOUT# 1

D24

42

ATF_INT# 16

RB751V

+3VALW

EC_RSMRST# 35
CK408_PWRGD# 13,35
ENVEE
14
ENBKL
14

ENVEE
ENBKL

KBA0
KBA1

1
R120
1
R121

2
@1K
2
1K

R122
1
R123

@1K
2
1K

R124
1
R125

@1K
2
1K

KBA2
TP_CLK
TP_DATA
LID_SW#
CDON#

14
14
34
34

KBA3
KBA4

KBA5

I/O Address
Index

BADDR1(KBA3) BADDR0(KBA2)

Data

2E

2F

4E

4F

(HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1

Reserved

R241
C RY1

2
20M

X1

47

PC87591VPC
L36

ECAGND

38

+3V

LFRAME#
LDRQ#
SERIRQ

FSTCHG

SM/SD_PME#

NUM_LED#
CAPS_LED#
PADS_LED#

IOPD0/RI1#/EXWINT20
IOPD1/RI2#/EXWINT21
IOPD2/EXWINT24
IOPD4
IOPD5
IOPD6
IOPD7

PC7

143
142
135
134
130
129
121
120

11
12
20
21
85
86
91
92
97
98

28

RB751V
2

34
34
34

26
29
30
SCR_LED# 41
42
54
55

PCI_PME#
ATFOUT#

MP3#
PC7

34,37,38,39 PACIN
28
RING#
13,16 PM_SLP_S3#

RCL#

IOPC0
IOPC1/SCL2
IOPC2/SDA2
IOPC3/TA1
IOPC4/TB1/EXWINT22
IOPC5/TA2
IOPC6/TB2/EXWINT23
IOPC7/CLKOUT

IOPK0/A8
IOPK1/A9
IOPK2/A10
IOPK3/A11
IOPK4/A12
IOPK5/A13/BE0
IOPK6/A14/BE1
IOPK7/A15/CBRD

KBA[0..18]
ADB[0..7]
KSI[0..7]
KSO[0..15]

KBA[0..18]
ADB[0..7]
KSI[0..7]
KSO[0..15]

C RY2

G20

168
169
170
171
172
175
176
1

EC_SMC2
EC_SMD2

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7

ENV0 (KBA0)
IRE
R242
* OBD
120K_0603
DEV
PROG

IOPB0/URXD
IOPB1/UTXD
IOPB2/USCLK
IOPB3/SCL1
IOPB4/SDA1
IOPB7/RING#/PFAIL#

124
125
126
127
128
131
132
133

32.768KHZ
C280
10PF

153
154
162
163
164
165

IOPH0/A0/ENV0
IOPH1/A1/ENV1
IOPH2/A2/BADDR0
IOPH3/A3/BADDR1
IOPH4/A4/TRIS
IOPH5/A5/SHBM
IOPH6/A6
IOPH7/A7

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10

34
34

D26

R257
10K

RC#

EC_URXD
EC_UTXD
EC_USCLK
EC_SMC1
EC_SMD1

EC_URXD
EC_UTXD
EN_WOL#
EC_SMC1
EC_SMD1
LPC_RST#

18
PBTN_OUT#
5,29
EC_SMC2
5,29
EC_SMD2
34 FAN_SPEED

RB751V
D25
16

PCM_SUSP#

IOPA0/PWM0
IOPA1/PWM1
IOPA2/PWM2
IOPA3/PWM3
IOPA4/PWM4
IOPA5/PWM5
IOPA6/PWM6
IOPA7/PWM7

33
33
14
14

11
11
11,27
33,40
33,40
24

+3VS

GATEA20

32
33
36
37
38
39
40
43

For PWM EN_DFAN

KSO16
KSO17

16

U30

INVT_PWM

INVT_PWM
BEEP#

38
ACOFF
16 PM_BATLOW#
34
EC_ON
18 EC_LID_OUT#

.1UF
ECAGND

R266
10K

.1UF

AGND

L35
1
2
CHB1608U800
C372

+EC_AVCC +RTCVCC

AVCC

14
31

+3VALW

C38

16

**
2

C282

1000PF 1000PF

C72

96

1
2

1
2

.1UF

.1UF

+EC_AVCC

C279

C91

+3VALW
51VDD

GND1
GND2
GND3
GND4
GND5
GND6
GND7

+RTCVCC

.1UF

**

17
35
46
122
137
159
167

C318

.1UF

C281

.1UF

C278

+3VS

2
@0
2
0

VDD

+3VALW

1
R64
1
R60

+3VALW

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6

C259
12PF

0
0
1
1

ENV1 (KBA1)

TRIS (KBA4)
0
0
0
0

0
1
0
1

SHBM(KBA5)=1: Enable shared memory with host BIOS

TRIS(KBA4)=1: While in IRE and OBD, float all the
signals for clip-on ISE use

COMPAL ELECTRONICS, INC

1
2
CHB1608U800

Title
PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
3

SCHEMATIC, M/B LA-1331

Document Number

Rev
2A

401207
, 18, 2004

Sheet
1

32

of

83

+3VALW
C239

+5VALW

+3VALW

19 SHDD_LED#
19 PHDD_LED#
19,24
DRV0#
23
OCCB#
+3VALW

SELIO#

SELIO#

20

8P4R_100K

2
.1UF

KBA2

SELIO#

U20A
74LVC32

74LVC244

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

3
4
7
8
13
14
17
18

D0
D1
D2
D3
D4
D5
D6
D7

AA
LARST#

11
1

CLK
CLR

CC

R244
+5VALW

EXTIDEPWR# 19
MDC_DN# 14

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

CD_PLAY 29
HDD_LED# 34
2ND_CHGI_CD_FDD_LED# 34

74HCT273

C263

U22
2
5
6
9
12
15
16
19

VCC

C220

+3VALW

1G
2G

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

32

KBA1

1
19

18
16
14
12
9
7
5
3

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

10

14

U20B
74LVC32

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

8
7
6
5

10

PCM_LED

2
4
6
8
11
13
15
17

VCC

BUTTON1#
INTERNET#
CD_INTA#

1
2
3
4

GND

34
34
29

RP11
DD
AA
BB
CC

GND

20

.1UF
U26

.1UF
C225

14

20K

R229

1UF_25V_0805

100K

D11

1
0_0402

+3VALW

KBA3

12

SELIO#

13

1G
2G

VCC

1
19

11

2
.1UF

20

18
16
14
12
9
7
5
3

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

10

14

U20D
74LVC32

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

C219

DAN202U

.1UF
U27

20
HOT#

29 MEDIA_DETECT
34
VOL_UP#
34
VOL_DW#
27,34 KILL_SW

2
4
6
8
11
13
15
17

+5VALW

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

+3VALW

KBA4

U20C
74LVC32

9
8

SELIO#

GND

EXTID0
EXTID1
EXTID2

PCM_LED

C240

19
19
19

10

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

3
4
7
8
13
14
17
18

D0
D1
D2
D3
D4
D5
D6
D7

BB
LARST#

11
1

CLK
CLR

74LVC244

U21
2
5
6
9
12
15
16
19

VCC

+3VALW

22 PCM2_LED

PWR_LED# 34
2nd_BATT_LOW_LED# 34
BATT_LOW_LED# 34
BATT_CHGI_LED# 34
WL_OFF# 27
CD_STOPBTN# 29
PCMRST# 23
EC_AMPPD# 31

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND

1
@0_0402

22 PCM1_LED

10

2
R276

THRM#

HOT#

14

2
R277

PROCHOT#

**
74HCT273

DD

BOARD ID

7SH32FU

C121
1
2

R18

U25
4

**

+3VALW

1
R149
1
R147
FLASH_VCC

2
@0
2
0

1 R16
1
1
R19
1
R20
2
R17
2
R21

2 100K
2 @100K
B ID
2
@100K
2
100K
1
100K
1
@100K

KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4

32
32

KBA[0..18]
ADB[0..7]

A11
A9
A8
A13
A14
A17
WE#
VCC
A18
A16
A15
A12
A7
A6
A5
A4

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3

@SST39VF040_TSOP
KBA[0..18]
ADB[0..7]

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

2
4

U40
7SH32FU

Q33
3

2N7002

R190

R198

.1UF

4.7K

4.7K

8
7
6
5

R188
100K

U16
EC_FLASH# 17
FWR#

32

32,40
32,40

EC_SMC1
EC_SMD1

VCC
WC
SCL
SDA

2
G
1

+12VS

FWE#

2
100K

R417
R381
100K

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

A0
A1
A2
GND

1
2
3
4

NM24C16

R181
100K

74LVC244

1
C128

+3VALW

2
.1UF

U14

U11

U12

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

18
16
14
12
9
7
5
3

+5VALW

.1UF
KBA11
KBA9
KBA8
KBA13
KBA14
KBA17
FWE#

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

2
.1UF

1G
2G

1
C474

1
19

2
.1UF
U19

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

C215

5
2

SELIO#

.1UF

KBA5

2
4
6
8
11
13
15
17

+5VALW

C249

MP3_STOPBTN#
MP3_PLAYBTN#
MP3_FRDBTN#
MP3_REVBTN#

34 MP3_STOPBTN#
34 MP3_PLAYBTN#
34 MP3_FRDBTN#
34 MP3_REVBTN#
29,34 STOPBTN#

+5VALW +5VALW

+3VALW

+3VALW +3VALW

C229

0
1
0
0

20

0
0
1
0

VCC

0
0
0
1

+5VALW
+3VALW

2A4

GND

0.1
0.2
0.3
1.0

2A3

10

REV 2A2

FR D#
KBA10
FSEL#
ADB7
ADB6
ADB5
ADB4
ADB3
ADB2
ADB1
ADB0
KBA0
KBA1
KBA2
KBA3

FRD#

32

FSEL#

32

KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1
KBA0
ADB0
ADB1
ADB2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS

VCC
WE*
A17
A14
A13
A8
A9
A11
OE*
A10
CE*
DQ7
DQ6
DQ5
DQ4
DQ3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

FWE#
KBA17
KBA14
KBA13
KBA8
KBA9
KBA11
FR D#
KBA10
FSEL#
ADB7
ADB6
ADB5
ADB4
ADB3

KBA11
KBA9
KBA8
KBA13
KBA14
KBA17
FWE#

FLASH_VCC

FLASH_VCC

KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

A11
A9
A8
A13
A14
A17
WE#
VCC
A18
A16
A15
A12
A7
A6
A5
A4

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

FR D#
KBA10
FSEL#
ADB7
ADB6
ADB5
ADB4
ADB3
ADB2
ADB1
ADB0
KBA0
KBA1
KBA2
KBA3

COMPAL ELECTRONICS, INC

@29F040_TSOP
Title
29F040/SST39VF040_PLCC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

Size
B

Document Number

Date:

, 18, 2004

TRANSFERRED FROM THE CUSTODY OF T

Rev
2A

401207
Sheet

33

of

83

+3VS

1
2
3
4

+3VALW

MP3_STOPBTN#
MP3_PLAYBTN#
MP3_FRDBTN#
MP3_REVBTN#

8
7
6
5

+3VALW

RP8

8P4R_10K

R74
R245

33 MP3_FRDBTN#

470K

EC_RST#

2
PC7

33 MP3_STOPBTN#

Q20
@2N7002

33 MP3_PLAYBTN#

32

33 MP3_REVBTN#

EC_RST# 32

@470K

7,14,16,19,20,21,22,23,24,27,28 PCIRST#

U23
@7SH08FU

1
4

LPCPD#

LPCPD#

MP3_REVBTN#

2
D28

1
RB751V

REVBTN#

MP3_STOPBTN#

2
D30

1
RB751V

STOPBTN#

MP3_PLAYBTN#

2
D31

1
RB751V

PLAYBTN#

27,33 KILL_SW
32 PADS_LED#
33
INTERNET#
33
VOL_DW#
32,37,38,39 PACIN
33 BATT_LOW_LED#
33
HDD_LED#
32
CDON#
29
FRDBTN#
29,33 STOPBTN#

32

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

**

For PC87591 REV 0.A Only

FRDBTN#

JP6

LPCPD#
R219

1
RB751V

18,32
ON/OFF
32
EC_ON
33 2nd_BATT_LOW_LED#

14,16,24 SUS_STAT#

2
D29

+3VALW

2
@.1UF
5

1
C243

MP3_FRDBTN#

FRDBTN#
STOPBTN#

+5VALW

1
2

C638
1000PF

+3V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

51ON#
37
LID_SW# 32
MP3#
32
SM_LED 28
CAPS_LED# 32
NUM_LED# 32
BUTTON1# 33
VOL_UP# 33
PWR_LED# 33
BATT_CHGI_LED# 33
2ND_CHGI_CD_FDD_LED# 33

SMLED

REVBTN#
PLAYBTN#

REVBTN# 29
PLAYBTN# 29
C

+3VALW
+3VS

SUYIN-80065A-040G2T
C639
1000PF

FAN CONN.
+5V

+12V

R355

EN_DFAN

EN_DFAN

U36

1
4
2

3
VEE LMV321_SOT23-5

1
2

JP10
D38
1N4148

1
2
3
53398-0310-FAN

+3V

1
R347
13K_1%

+5VFAN
.1UF

Q30
2SA1036K

32

1N4148

@10UF_16V_1206

1SS355

VCC

2
.1UF

C409

D35

E
C446

1
C422

.1UF

D40

Q28
FMMT619

2
B

+5V
C421

3.6K

1
R342
7.32K_1%

R132

10K
32

FAN_SPEED

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

Size
B

Document Number

Date:

, 18, 2004

TRANSFERRED FROM THE CUSTODY OF

Rev
2A

401207
Sheet
1

34

of

83

RTC Batt. Connector

W=30mils

@.1UF

GND

EC_RSMRST# 32
1

U32D

74LVC14
C388

1
R92

2
@0

PM_RSMRST# 16

74LVC14

R52
10K

GND

CHGRTC

+3V
C105
.1UF

Place near ICH3-M

2
20K

11

10

14

+3V
U32F
74LVC14

13

12

+3V

PM_PWROK 16

C107
1UF_0805_X7R

1
R297

U32E
74LVC14

VGATE

+3V

42

U33C
74LVC125

10

R98
10K

14

W=30mils

U32C

1
R48

+3V

1
@1M

2
R300

+3V

D44
HSM1265

*
1

**

+RTCVCC

R301
@150K

14

RTCBATT

14

.1UF

Power ON Circuit
+3V

+RTC_BATT
C111
1
1
2

BATT1

+3V
H8

ST2

ST3

ST4

H2

R95
10K

U33D
74LVC125

13

ST1

Screw Boss 070

Stand-Off 115

Stand-Off 053

Stand-Off 053

H27

11

Stand-Off 053

Stand-Off 090

H10

1
R96

ICH_VGATE 16

+3V
+3VS

H9

H12

12

R93

CK408_PWRGD# 13,32
Q4

2
1

H26

L Screw Hold

M Screw Hold

N Screw Hold

O Screw Hold

O Screw Hold

O Screw Hold

O Screw Hold

O Screw Hold

O Screw Hold

FD1
FIDUCAL

FD2
FIDUCAL

FD3
FIDUCAL

FD5
FIDUCAL

FD4
FIDUCAL

CF10
CF6
CF7
CF8
CF2
CF4
CF17
CF19
CF18
CF12
SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80

H19

H21

H17

H7

H13

H14

H24

CF5
CF1
CF3
CF9
SMD40M80 SMD40M80 SMD40M80 SMD40M80

M Fixed Position Hold

I Fixed Position Hold F Fixed Position Hold

H11

CF11
CF16
CF14
CF13
CF15
SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80

I Screw Hold

3904

100PF

G Screw Hold

C95

F Screw Hold

H22

H5

D Screw Hold

2
100K

C Screw Hold

H20

1
R97

A Screw Hold

J CPU Thermal Plane Screw Hold

H29

H4

H1

H23

H28

J CPU Thermal Plane Screw Hold

H3

J CPU Thermal Plane Screw Hold

J CPU Thermal Plane Screw Hold

10K

FD6
FIDUCAL

H6

H16

H15

H25

COMPAL ELECTRONICS, INC

Title

SCHEMATIC, M/B LA-1331

E HDD Frame Hold

E HDD Frame Hold

E HDD Frame Hold

PROPRIETARY NOTE

E HDD Frame Hold

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
Document Number
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
Custom 401207
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
, 18, 2004
C

Rev
2A
Sheet
E

35

of

83

+1.8VALW To +1.8VS Transfer

+1.8VALW

+1.8VS
U2

SUSP# 5
G2

28,29,32,40,41 SUSP#

1
2

10UF_16V_1206

1
R195

R461
470

10UF_16V_1206

+5VALW To +5VS Transfer

3
4
8
1

Q13
2N7002

4.7UF_10V_0805

.1UF

4.7UF_25V_1206

C613
4.7UF_25V_1206

+5VS

C614

C615

R453
470

4.7UF_25V_1206

SI4702DY

R459
1K

2N7002

330K

+12VALW To +12VS Transfer

SYSON# 2
G
SUSP

SUSP
3

C519
.01UF

2N7002
2
G

Q54
2N7002

2
G

Q55
2N7002
3

1 2

1
Q2

R443

+5VS_GATE

.01UF

C588
4.7UF_10V_0805

SYSON#

Q51
2
G

D
C621

ON_GATE
1

SYSON#

SI4702DY

C602

+5V
C605

SUSP

S2
S2
VHV
S1
VON/OFF

1UF_25V_0805

VIN
VIN
VIN

7
6
5

C608

C618
4.7UF_10V_0805

2
G

+5V & +5VS Discharge

3
4
8
1

S2
S2
VHV
S1
VON/OFF

SUSP
Q57
2N7002

+5VS

U46

4.7UF_10V_0805

VIN
VIN
VIN

7
6
5

C589

+5VALW

U47

+5V

+5VALW

SYSON# 2
G

R194
1M

C18
.1UF

+12V

R173
1K

.01UF

2
100K

+3VS

C189

1 2

+5VS_GATE

+5VALW To +5V Transfer

1
2

+12VALW

R447
100K

R448
1M

10UF_16V_1206

C210

SI4702DY

C242
4.7UF_10V_0805

1
2

10UF_16V_1206

C2

C216

C596

+3V
C200

ON_GATE
1

SYSON#

3
4
8
1

SI4702DY

S2
S2
VHV
S1
VON/OFF

1UF_25V_0805

VIN
VIN
VIN

7
6
5

C619
SUSP

4.7UF_10V_0805

+3V & +3VS Discharge

1UF_10V_0603

C609

S2
S2
VHV
S1
VON/OFF

Q18B
SI1906DL

+3VS

U17

3
4
8
1

VIN
VIN
VIN

7
6
5

+3VALW

S2

+3V

SUSP

Q18A
SI1906DL

S1

41

G1

U48

C598
4.7UF_10V_0805

SYSON#

+3VALW To +3VS Transfer

+3VALW

2
6

2
1

SYSON

Q17
2N7002

+3VALW To +3V Transfer

4.7K

SYSON#

D2

32,41

2
G

R199

10K

1K

SUSP

R193

R11

+5VS_GATE

+3VALW

C16
C9
C17
1UF_10V_0603 4.7UF_10V_0805 4.7UF_10V_0805
2

SI4800
C14
4.7UF_10V_0805

1
2
3
4

S
S
S
G

D1

+3VALW

D
D
D
D

8
7
6
5

+12V & +12VS Discharge

+12VALW To +12V Transfer

C166
1UF_25V_0805

R460

SYSON# 2
G

Q58
2N7002

1K
1 2

1 2
3

C623
1UF_25V_0805

1K

1
2

SUSP# 2
Q52 G
2N7002

+12VS

R462

+12VS

1
2

Q10
2N7002

1
R456
51K
1 2

1
1 2
3

1
2

+12V

1UF_25V_0805

Q53
NDS352P

2
G
C167

1
2
3

1UF_25V_0805

+12V

SYSON

C628

R160
47K

R455
100K

.1UF_25V_0805

Q9
NDS352P

C627

.1UF_25V_0805

C169

R161
100K

C173

+12VALW

+12VALW

+12VALW

+12VALW

SUSP 2
G

Q56
2N7002

COMPAL ELECTRONICS, INC

1000PF

Title

SCHEMATIC, M/B LA-1331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
Document Number
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
Custom
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
, 18, 2004
A

Rev
2A

401207
Sheet
E

36

of

83

VS

VIN

VIN

PR1
1M_1%

PU1A

PR5
22K

PC6
0.1UF_50V

PR6
20K_1%

PC5
1000PF_50V

PC4
100PF_50V

PZD1
RLZ4.3B

PC3
1000PF_50V

ACIN

17

PACIN

32,34,38,39

PR7
10K

Vin Detector

High 18.764 17.901 17.063

Low 17.745 16.903 16.038

RTCVREF

1
PR8
10K

PC2
100PF_50V

PC1
1000PF_50V

PACIN

PD1
EC10QS04

2
2DC-S026B201 2.5D 5P

LM393M

3
3

PR4
1K

10K

PR2

PR3
84.5K_1%

PCN1

VS

PL1
CHC4532U800_1812

PF1
@7A 32V UL/CSA FAST
1

2
1

Build 0 ohm for ACL10

3.3V

VIN

VSB

PD2
RB751V
PD3
RLS4148

BATT+

PR9
1K_1206

PD4
RB751V

1
PR10

**

33_1206

VS

VIN

PQ1
TP0610T
3
1

PR162
200_0805

PR11
1K_1206

PC7
0.22UF_1206_25V

PC8
0.1UF_0805_25V

PR12
100K

B+

PR13
1K_1206

CHGRTCP

PD5
RLS4148
2
1

3.3V
PZD3
RLZ6.2C

PC12
1UF_0805_25V

PZD4
RLZ16B

PR23
47K

(6A,240mils ,Via NO.= 12)

+1.5VS

(2A,80mils ,Via NO.= 4)

+1.25VSP

PAD-OPEN 3x3m

+1.25VS

PAD-OPEN 3x3m

PJP4

(3A,120mils ,Via NO.= 6)

Precharge detector
15.34
15.90
16.48
13.13
13.71
14.20

PQ3
DTC115EUA

+1.8VALW

(3A,120mils ,Via NO.= 6)

+12VALW

(120mA,20mils ,Via NO.= 1)

100K

+1.8VALWP

PACIN

+5VALWP

100K

PAD-OPEN 3x3m
PJP5

+2.5V

2
G
3

+1.5VSP

PQ2
2N7002

PJP3

3.3V

PJP2

RTCVREF

+2.5VP

PC9
1000PF

PR19
499K_1%
PR21
215K_1%

PC13
10UF_1206_10V

PR22
200

PR20
10K

CHGRTC

PC10
1000PF

RB715F

200_0805

S-81233SG (SOT-89)

PR17
499K_1%

ACON

38

PU1B
LM393M

PD6

1
3

PR18

PU2

PC11
0.1UF_16V

RTCVREF

PR16
1M_1%

6.0V

39,40 MAINPWON

PR15
10K
VS

2
PR14
22K

51ON#

34

PAD-OPEN 3x3m
PJP6
4

+12VALWP

PJP7

+1.2VPP

PAD-OPEN 2x2m
PJP8
+5VALWP

+5VALW

(5A,200mils ,Via NO.= 10)

+1.2VP

(300mA,40mils ,Via NO.= 2)

COMPAL ELECTRONICS, INC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY

OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
Size
Document Number
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
B
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
Date: , 18, 2004

PAD-OPEN 3x3m
PJP9
+3VALWP

1
PAD-OPEN 2x2m

+3VALW

SCHEMATIC, M/B LA-1331

(5A,200mils ,Via NO.= 10)

PAD-OPEN 3x3m
A

Rev

401207

2A
Sheet

37

of

83

8
7
6
5

PL3
FBM-L11-453215-900LMAT_1812
1
2

PQ6
SI4835DY

4.7UF_1210_25V

ACOFF#

1
PU3
MB3878

-INC2

+INC2

24

OUTC2 GND

23

PC16
220PF_50V

+INE2

CS

22

-INE2 VCC(o)

21

FB2

OUT

20

VREF

VH

19

FB1

VCC

18

2
PQ9
2N7002

VIN

3
2
1

PR28 47K

4
PQ7
SI4835DY

100K

ACOFF

32

PC21
0.1UF_16V

PC22
2200PF_50V

2
PR36
10K

PR38
162K_1%
1
2
PR40 10K
2
1

PC25
0.1UF_16V

+INE1

RT
-INE3

17

16

10

OUTC1

FB3

15

11

OUTD

CTL

14

12

-INC1

+INC1

13

2
PR37
68K

2
PR41
47K

CC=0.5~2.52A
CV=16.84V(8 CELLS LI-ION)

32

PL4
22UH_SPC-1205P-220A
1
2
1

PD8
1SS355

PC24
1500PF_50V

PR42
100K_1%

IREF=1.31*Icharge
IREF=0.73~3.3V

BATT+

PR39
0.02_2512_1%

PD9
RB051L-40

PR43
47K

IREF

-INE1

FSTCHG

5
6
7
8
LXCHRG

PC23
0.1UF_0805_25V
1
2

PC19
PR35
4700PF_50V 10K

PC17
0.1UF_0805_25V
PC20
0.1UF_50V
1
2

PC27
4.7UF_1210_25V
2
1

PQ8
DTC115EK

PC26
4.7UF_1210_25V
2
1

PR34
10K_1%

PC18
0.1UF_16V

100K

PR33
21K_1%

ACON

32

2
G
3

1
PR31
10K

32,34,37,39 PACIN

PR32
10K

PR27 10K

PR30
150K

PR29
0

1
PD7
1SS355
ACOFF# 1

37

8
7
6
5
4

4.7UF_1210_25V

PC15

PR26
200K

PR25
10K

PC14

1
2
3

1
2
3

B++

B+
PR24
0.02_2512_1%

1
2
3
1

Iadp=0~3.5A

P3
PQ5
SI4835DY

8
7
6
5

VIN

P2
PQ4
SI4835DY

1
PR44
47.5K_1%

1
PR45
143K_1%

4.2V

VMB

VS

PR46
340K_1%

8 CELL : 18V--> BATT_OVP= 2.0V

+SDREF

+2.5V
1

OVP voltage : LI-MH

PC28
0.1UF_50V

PR47
499K_1%

PR49
0

2.2K

PC32
0.01UF

PR52
105K_0.5%

PC31
@0.1UF_16V

PC30
10UF_1206

1
1

PR51

PC29
0.1UF_16V

PR50
100K_0.5%

PR48
100K_0.5%
PU4B
LM358

32 BATT_OVP

PU4A
LM358

(BAT_OVP=0.1111 *VMB)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY

OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
A

COMPAL ELECTRONICS, INC

Title

SCHEMATIC, M/B LA-1331

Size

Document Number

B
Date:

Rev

401207
, 18, 2004

2A
Sheet

38

of

83

PC33
2.2UF_1206_25V
1
2

1
2

2
3

5
6
7
8

PC40
4.7UF_1210_25V

5
6
7
8

2
1

1
2

VL

PD13
EP10QY03

SPOK

10K_1%

PR73

PR75

+
PC53
100PF

PR71
10K

3
2
1
PR67
0

PR72
47K

1
PR68
10.5K_1%

2
PR66
@0

680PF

1
2

2
1

VL

PR70
10K_1%

+5VALWP
PC50

VS

+5VALWP
PC49
4.7UF_1206_10V
PC52
150UF_D_6.3V_KO

RUN/ON3

TIME/ON5

28

2.5VREF

PR62
0.012_2512_1%

PC51
150UF_D_6.3V_KO

MAX1632

PR61
2M

CSH3
CSL3
FB3
SKIP#
SHDN#

CSH5

3
2
1

1
2
3
10
23

PC45
47PF

PLX5

LX3
DL3

PQ13
SI4810DY

PDL5

PU5

VL

V+

DH3

26
24

4
5
18
16
17
19
20
14
13
12
15
9
6
11

GND

PC48
100PF

PR63
10K
PR65
@300K

27

PDH51

2
PR58
0

12OUT
VDD
BST5
DH5
LX5
DL5
PGND
CSH5
CSL5
FB5
SEQ
REF
SYNC
RST#

PT1
SDT-1205P-100

21

22
2

BST3

3.57K_1%

PR64

PD12
EP10QY03

FLYBACK

PDH5

1
2
3
1

32,34,37,38 PACIN

25

PC39
4.7UF_1210_25V

PC41
4.7UF_1206_10V

1
2

PR57
0

2
2
1

CSH3

PC47

150UF_D_6.3V_KO
2
1

PC46
150UF_D_6.3V_KO
2
1

PR59
1M

PQ11
SI4800DY

+12VALWP

PC43
4.7UF_1210_25V

PDL3

B+++

2
PC42
0.1UF_0805_25V

8
7
6
5
1
1
2

VL

PR56
10_1206

1
2
3

PLX3

PQ12
SI4810DY
47PF
PC44

PD11

PDH31 1

PDH3

PL6
SLF12565T-100M

PD10
EC11FS2

8
7
6
5
4

+3VALWP

PR53
22_1206
SNB 2

PC38
0.1UF_0805_25V
1
2

DAP202U

VS
PR54
0

PC37
4.7UF_1210_25V

PQ10
SI4800DY

PR55
0

PR60
0.012_2512_1%

BST51

BST31

B+++

FBM-L11-322513-151LMAT
PL5
2
1

PC36
4.7UF_1210_25V

B+

PC35
0.1UF_0805_25V

PC34
470PF_0805_100V

0.047UF_16V

40

SPOK

+5V Ipeak = 6.66A ~ 10A

MAINPWON 37,40

+3.3V Ipeak = 6.66A ~ 10A

47K_1%

PC56

PC57
0.047UF_16V

COMPAL ELECTRONICS, INC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY

OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
Size
Document Number
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
B
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
Date: , 18, 2004

SCHEMATIC, M/B LA-1331

Rev

401207

2A
Sheet

39

of

83

PF2
7A 24V UL/CSA FAST

PR76
1K

2
1

PR78
47K
PR77
1K

+3VALWP

VL

**
PH1
10K_1%

PC60
0.1UF_50V

ALI/MH#

TM_REF1

PD15
@BAS40-04

**

1
1SS355

VL
PR86
100K_1%

**

PU6A
LM393M

PC61
1000PF_50V

**
3

PC62
0.22UF_0805_16V

PR81
3K_1%

PD33

+3VALWP

PR85
1K

**
1

PR83
16.9K_1%

32

PR163
47K_1%

**

PR82
47K_1%

PD14
@BAS40-04

PR84
25.5K_1%
2

VL

VS

3
1

PC59
0.01UF_50V

PR80
100

SUYIN 25063A-07G1-E 7P P2.5

PH1 under CPU botten side :

CPU thermal protection at 87 degree C
Recovery at 48 degree C

BATT+

1
PR79
100

PL7
BLM41P600S_1806
2
1

ALI/NIMH#
AB/I
TSA

**
VMB

PJP10

1
2
3
4
5
6
7

PC58
1000PF_50V

37,39

BATT_TEMPA 32

PQ45
DTC115EK

EC_SMC1 32,33

100K

PH2 near main Battery CONN :

BAT. thermal protection at 73 degree C
Recovery at 50 degree C

100K

**

PD17
@BAS40-04

PD16
@BAS40-04

PR87
100K_1%

EC_SMD1 32,33
EC_SMC1

EC_SMD1

MAINPWON

**

+5VALWP
VL
VL

**

VIN

**
2

PD18

PH2
10K_1%

+12VALWP

PR89
47K_1%

PD19
1SS355
SBAT_VCC

PR91
6.2K

1
PR96

SBAT_CON_2P

39

SPOK

SPOK

2
1

PQ16
DTC115EK

28,29,32,36,41 SUSP#

SUSP# 2

**

B+

100K

PD34

PU6B
LM393M

1
1SS355

VL
PR94

100K_1%

PR95
100K_1%

EC10QS04
100K

PD21

100K

**
PR88
3.24K_1%

PQ15
DTC115EK

PC64 1000PF_50V

PQ14
IRLML5103

EC10QS04

1
2

**

PR92
100K

4.7K

PC65
0.22UF_0805_16V

TM_REF2

PR93

PD20

**

PR90
10K_1%

1SS355

PJP11

PR164
47K_1%

VSB

100K

COMPAL ELECTRONICS, INC

100K

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY

OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
Size
Document Number
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
B
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
Date: , 18, 2004

SCHEMATIC, M/B LA-1331

Rev

401207

2A
Sheet

40

of

83

+2.5VP
D
PQ17
@SI3445DV
+2.5VP
PL8

1
PC66
0.1UF_0805_25V

1
VCC2

16

PVDD1

PVDD2

15

VL1

VL2

14

PGND1

PGND2

13

AGND1

AGND2

12

PQ21
DTC115EUA

SD

VIN/2

VCCQ

10

+2.5VP

1
2

AGSEN

AGND

1
2

PC79
0.1UF_0805_25V

PR109
1K

PC78
1000PF

PC80
2

SUSP#

100K

100K

SYSON

11

100K

100K

VFB

VL

2
PR108
100K

PQ22
DTC115EUA

100K

Layout : "Compensation network close to FB pin"

PQ23
DTC115EUA

2
2

PU8B
LM393M
7

100K

PR106
100K

PR107

+2.5VP

PR105
200K

100K

PD25
@EP10QY03

1
4

PC77
1000PF

PC75
4.7UF_1206_16V

2.5VREF

1000PF
1

8
3

LX1.25

CM8500

PQ20
2SA1036K

PU7

PR104
@11.8K_1%

+1.25VSP

PL9
5UH_SPC_06704

PC73
4.7UF_1206_16V

2
3

PU8A
LM393M
1

PC68
0.1UF_0805_25V

PC76
220UF_D_4V_KO

1
2

PC72
@0.1UF_16V

VCC1

1.25VIN

VS
PC74
0.1UF_50V

1
2
2

PC67
@470P

PD23
RB051L-40

1
1

PR101
100

PC69
220UF_D_4V_KO

SPC-5R0M
PR100
@2M

PQ18
SI3445DV

PC71
2200PF

2
PR103
1K

1
1

PR102
10K

PQ19
HMBT2222A

PD22
RB751V

PC70
10UF_1206_10V
2
1

PR99
10

**

LX2.5

6
5
2
1

2.5VIN

PR98
0_1206

PR97
0_1206

+2.5V +-5%

6
5
2
1

+5VALWP

5.1K

PR113
0

PQ27
DTC115EK

8
3

2
PR122

2.5VREF

200K

39

PR119
100K

PR120

PU9B
LM358

2.5VREF

PQ28
DTC115EK

SUSP#

100K
+

PR121

3
PQ29
2SA1036K

2.5VREF

PC89
68PF

100K
PU13A
LM393M
1

PR114
200K_1%
1

+5VALWP

2
2

PC84
220PF

2
PR112
5.1K

PC83
0.1UF_16V

2
8
3

PC81
150UF_D_6.3V_KO

PC116
0.1UF_50V

PR118
300K_0.5%

PR117
100

PU9A
LM358

PC87
0.01UF

1
2

VS

PR116
1K

+1.5VSP
VS

PC88
2200PF_50V

PD27
RB051L-40

PR115
10K

PQ26
HMBT2222A

2
1
2

PD26
RB751V

PC86
4.7UF_1206_16V

PC85
150UF_D_6.3V_KO

6
5
2
1

1.8VIN

+1.8VALWP

PL10
5UH-SPC-06704
LX1.8 1
2

PQ25
SI3445DV

+1.5V+-5%

+1.8V+-5%

PR111
0_1206

6
5
2
1
G

PC82
4.7UF_1206_16V

+1.8VALWP

PQ24
SI3442DV
+3VALWP

100K

2
PR123

28,29,32,36,40

1
0

1
@0

SYSON

32,36

100K
4

PR124
511K_1%

PC90
1000PF

SYSON#

SYSON# 36

100K

PU13B
LM393M
7

100K

PQ30
@DTC115EK

COMPAL ELECTRONICS, INC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY

OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
Size
Document Number
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
B
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
Date: , 18, 2004

SCHEMATIC, M/B LA-1331

Rev

401207

2A
Sheet

41

of

83

B+

PC93

PC94
5
6
7
8

PC92

4.7UF_1210_25V

+5VALWP

PR125

PQ32
IR7811A

IR7811A
PD28
1SS355

17
PR139
180K_1%

PC99
47PF_0603

PC100
PC101
2VREF
1UF_0805

1UF_0805
2

PR143
100K_1%

+2VREF

TIME

VCC

FB

SDN/SKIP

POS

13

VDD

NEG

CC

ZMODE

1
2

PD29
EC31QS04

0.01UF

PR135
2.8K_1%
1
PR137

PC97
4.7UF_0805_10V

2
100

PC98
+5VALWP
PR140
49.9K_1%

1000PF_0603

19

20

OVP

SUS

11

REF

S1

12

ILIM

S0

15

GND

TON

PR142
68K_1%

18

10

D
+5VALWP

CPUB+

5
6
7
8

PQ37
2N7002
2
G

13,16
2
G

PC121
1000P

PQ40
IR7811A

IR7811A
3
2
1

3
2
1

PL13
SSC-1305-0R5 0.5UH
CS+ 2

VTT2LX

14

CM--

CM-

LX

13

CS--

CS-

DH

12

CS++

CS+

VDD

11

DL

10

2.7_0805

PC104 0.1UF_0805
PD31
C PUVDD
2
1

2.2
PR152

PC119

PQ43
2N7002
2
G

PM_DPRSLPVR

S
+CPU_CORE

PR161

PR149
2mR
1

PQ41
SI4362DY

PQ42
SI4362DY

PD30
EC31QS04

15

BST

5
6
7
8

V+

CM+

5
6
7
8

TRIG

0.01UF

CPUB+

PQ44
2N7002
2
G
PC122
1000P

2
CM++

PR151
1K_1%

16

PR150
20K_1%

PC103
0.1UF_0805

LIMIT

+CPU_CORE

PU11MAX1887
ILIM

PC102
470P

GND

PGND

1SS355

PC105

3
2
1

COMP

3
2
1

PC106

PC107

PC108

PC109
1UF_0805

4.7UF_1210_25V

4.7UF_1210_25V

4.7UF_1210_25V

4.7UF_1210_25V

0 PR154

PR157
200 2

CS++

PR156
0

PU12

VR_ON

DELAY

SENSE

ERROR

CNOISE

GND

32 VR_ON
PR160
0

PR158
200 2

VIN

ON/OFF#

GMUXSEL

CPUSTP#

DPRSLPVR

PM D-S

BM

BM D-S

Deeper

VCORE'
1.30V

Offset
0%
4.62%

1.20V
1.0V
D

PR159
@10K_1%

PC115

.1UF

VCORE
1.30V
1.239V

2.0%

1.176V

4.62%

1.144V

0%

SI9182AD

CS--

PM

VOUT

CPU_ON

2200PF PC114

PC113
4700P

CS+ 1

4.7UF_1206_16V

PC112
4.7UF_1206_16V

CM--

PC111

PC110
4700P

+CPU_CORE 1

PR155
200 2

CM++

CM+ 1

+CPU_CORE 1

+1.2VPP

+3VALWP

PR153
200 2

PM_GMUXSEL 16
PC120
1000P

PM_STPCPU#

PQ39

PR148
48.7K_1%

PQ36
2N7002
2
G

PR144
100K

PQ38
2N7002S

PR141
100K

PQ35
2N7002
2
G

PM_DPRSLPVR 16

PR146
33K_1%

PD32
EC31QS04

POS

PC118
1000P

PR145
53.6K_1%

PC96
0.1UF_0805

CPUFB

PQ34
SI4362DY

150K_1%

VGATE

PC117

PQ33
SI4362DY

14

D0

CPUB+

2.7_0805

V+

PR147
PC95
0.1UF_0805

16

DL

25

0K_0603
1
120K

D1

2.2
PR130

PR138

PR134
2
PR136
CPU_ON

24

+CPU_CORE
+CPU_CORE

VGATE

26

35
+3VALWP

BST

CPU_VID0

D2

3
2
1

5,6

28

23

5
6
7
8

CPU_VID1

DH

5
6
7
8

5,6

LX

D3

CM+

3
2
1

CPU_VID2

D4

22

5,6

0
1
100K
1
100K
1
100K
1
100K

CPU_VID3

PR128
2mR

PL12
SSC-1305-0R5 0.5UH

VTT1LX

PM_DPRSLPVR

CPU_VID4

5,6

27

20
PU10 MAX1718A
21

3
2
1

PR126

3
2
1

PQ31

2
2

C PUVDD

CPU-CORE

4.7UF_1210_25V

5,6

4.7UF_1210_25V

5
6
7
8

4.7UF_1210_25V

PC91

2
PR127
2
PR129
2
PR131
2
PR132
2
PR133

CPUB+
PL11
KC-FBM-L11-322513-201LMAT

5
6
7
8

COMPAL ELECTRONICS, INC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY

OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
Size
Document Number
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
B
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
Date: , 18, 2004

SCHEMATIC, M/B LA-1331

1.0V
E

Rev

401207

2A
Sheet

42
H

of

83

ACL10 LA-1331 BLOCK DIAGRAM

4

Mobile
Northwood
Thermal Sensor
NE1617
MAX6654MEE

(uFCBGA/uFCPGA)
PAGE 45,46,47

PSB

CRT
Connector

Clock Generator
W320-04
ICS9508-05

PAGE 46

CPU VID

PAGE 54

PAGE 47

400MHz

PAGE 56

Brookdale-M

AGP
Connector

AGP Bus

PAGE 55

200MHz (2.5V)

MCH-M 845MP
625 BGA

SO-DIMM x 2(DDR)

Memory Bus

BANK 0,1,2,3

PAGE 51,52

REV B0
PAGE 48,49,50

TV-OUT
Connector

266MHz (1.8V)

Mini PCI
PAGE 68

LAN
RTL8100-B(L)

RJ-45
PAGE 61

PCI BUS
33MHz (3.3V)

FANController

USB
PAGE 67

PAGE 75

IDE HDD

ICH3-M

PAGE 60

DC/DC Interface
RTC Battery

421 BGA

CARDBUS
OZ6933

PAGE 64

48MHz (3.3V)

ATA 66/100

PAGE 61

Slot 0/1

HUB Interface

PAGE 56

Audio CD-DJ
OZ165

REV B1

PAGE 63,64

PAGE 57,58,59

IEEE1394
VT6306

PAGE 70

24.576MHz (3.3V)

LPC BUS 33MHz (3.3V)

AC-LINK

PAGE 62

AC97 CODEC
ALC 101/201

PAGE 71

Super I/O

Embedded
Controller

LPC47N227
REV B

MDC
Connector

PAGE 60

BATTERY
Charger

Audio Amplifier
TPA0132

PAGE 72

PAGE 79

RJ-11

PAGE 55

NS PC87591

PAGE 65

PAGE 78

CD-ROM/DVD

Power Interface &

TEMP. sensing circuit

PAGE 61

PAGE 73

PAGE 79,80,81,83

Searal
1

PAGE 69

Parallel
PAGE 66

FIR
PAGE 66

Scan KB

FDD

BIOS & I/O PORT

PAGE 74

PAGE 55

PAGE 60

Title

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE
Size
Document Number
Custom
401207
Date:
A

, 18, 2004

Sheet
E

43

TRANSFERRED FROM THE CUSTODY OF THE COMPE

Rev
2A
of

83

Voltage Rails

PIR
REV 0.1

Power Plane

Description

S1

S3

S5

VIN

Adapter power supply (19V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

1.2VP

1.2VP switched power rail for CPU VID

ON

OFF

OFF

+1.25VS

1.25VS power rail

ON

OFF

OFF

+1.5VS

AGP 4X

ON

OFF

OFF
ON*

+1.8VALW

1.8V always power rail

ON

ON

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+2.5V

2.5V power rail

ON

ON

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

+3V

3.3V power rail

ON

ON

OFF

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5V

5V power rail

ON

ON

OFF

+5VS

5V switched power rail

ON

OFF

OFF

+12VALW

12V always on power rail

ON

ON

ON*

+12V

12V power rail

ON

ON

OFF

+12VS

12V switched power rail

ON

OFF

OFF

RTCVCC

RTC power

ON

ON

ON

+SDREF

+SDREF power

ON

ON

OFF

Note : "ON*" means that this power plane is "ON" only with AC power available, otherwise it is "OFF".

External PCI Devices

Device

IDSEL#

REQ#/GNT#

Interrupts

IEEE 1394

AD16

PIRQA

Mini-PCI

AD18

1/4

PIRQC/PIRQD

CardBus

AD20

PIRQA/PIRQB

LAN

AD17

PIRQB

SM

AD22

PIRQC/PIRQD

Date

Page
7

Change R212,R214 & R213 to 8.2K ohm for Intel recommand

2001/12/29

14

Stuff R361=22 Ohm and no-stuff R360 for Data-IN1 of MDC module.

2001/12/29

15

Change L28 & L29 to 0 Ohm for EMI issue.

2001/12/29

16

Change R39 power-plane to +3VALW for Resume-well Power-plane(+3VALW)

2001/12/29

17

DEL C73, C87, C371 for EMI issue.

2001/12/29

17

Change L37 power-plane to +1.8VS for Intel recommand.

2001/12/29

17

Change R279 power-plane to +3VS for Intel recommand.

2001/12/29

17

Change U29 pinV22,U18 & P14 power-plane to +CPU_CORE for Intel recommand.

2001/12/29

17

Change R284 power-plane to +3VALW for Intel recommand.

2001/12/29

18

Change "SMB_ALERT#" power-plane to +3VALW for "RESUME-WELL" power-plane(+3VLAW).

2001/12/29

18

Exchang D13,D14,D16,D17,D18 and R28,R34,R30,R29 to RP135,R466,R468 for cost-down.

2001/12/29

20

Add D43 for leakage.

2001/12/29

21

Exchang L42 to L52,L53, L54, L55 for ME limitation.

2001/12/29

27

Add D42 for leakage.

2001/12/29

31

Add R465 for PC99 Spec.

2001/12/29

34

Add C368, C369 for EMI solution.

2001/12/29

35

EC control "EC_RSMRST#". ->DEL R92, Stuff R48.

2001/12/29

35

Change R97 to 100K for "VGATE" of Max1718A issue.-> Change PR134= 0 Ohm.

2002/01/07

39

Change PR68 from 10k_1% to 10.5k_1%.(increase 5valwp to 5.125v).

2002/01/07

40

Change PR81 from 2.15k_1% to 1.87k_1%.( CPU thermal OTP from 83+-3C to 85+-3C).

2002/01/07

42

Add PR147, PR161 to 2.7_0805. for EMI requirement.

2002/01/07

42

Add PC120, PC121, PC122 to 1000pf. for ESD.

2002/01/07

42

Add PQ44 to 2N7002 for CPU SPEED STEP.

2002/01/07

42

Change PR130, PR152 from 0 to 2.2. for EMI requirement.

2002/01/07

42

Change PR143 from 53.6k_1% to 100k_1%. for CPU OCP.

2002/01/07

42

Change PR145 from 100k_1% to 53.6k_1%. for CPU OCP.

2002/01/07

42

Change PR148 from 30k_1% to 48.7k_1%. for CPU OCP.

2002/01/07

42

Change PU12 VIN from +2.5VP to +3VALWP.

REV 0.2
Date

Page

2002/01/11

EC SM Bus1 address
3

EC SM Bus2 address

Device

Address

Device

Address

Smart Battery

0001 011Xb

MAX6654MEE

1001 110Xb

1010 000Xb

OZ165

1011 0100b (B4h)

1011 000Xb

Smart Battery

0001 011Xb

Docking

0011 011Xb

DOT Board

XXXX XXXXb

EEPROM(24C16/02)
(24C04)

Clock Generator
W320-04 / ICS9508-05

1101 0000

Description
Change PH1 and PH2 design by high active for AC-IN issue.

REV 0.3
Date

Page

Description

None

REV 1.0
Date

Page

None

Date

Page

2002/04/10

Address

40

REV 2.0

ICH3-M SM Bus address

Device

Description

2001/12/29

20

GCR: (For LAN Issue)

<1>Isolation U18 pin6 for Realtek application notice.
<2>Change R204 from 5.9K+-1% to 5.6K +-1%.
<3>Change L23 from 4.7UH to 0 ohm.

DDR SODIMM SM Bus address

DDR SLOT
4

SA2

SA1

SA0

DDR SODIMM0 (REVERSE)

DDR SODIMM1 (NORMAL)

Title

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE
Size
Document Number
Custom 401207
Date:
A

, 18, 2004

Sheet
E

44

TRANSFERRED FROM THE CUSTODY OF THE COMPE

Rev
2A
of

83

+CPU_CORE

K2
K4
L6
K1
L3
M6
L2
M3
M4
N1
M1
N2
N4
N5
T1
R2
P3
P4
R3
T2
U1
P6
U3
T4
V2
R6
W1
T5
U4
V3
W2
Y1
AB1

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

J1
K5
J4
J3
H3
G1

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
ADS#

AC1
V5
AA3
AC3

AP#0
AP#1
BINIT#
IERR#

H6
D2
G2
G4

BR0#
BPRI#
BNR#
LOCK#

AF22
AF23

BCLK0
BCLK1

HREQ#[0..4]

HREQ#[0..4]

HADS#

+CPU_CORE

7
7
7
7

HBR0#
HBPRI#
HBNR#
HLOCK#

13
13

CLK_HCLK
CLK_HCLK#

7
7
7

HIT#
HITM#
HDEFER#

2
10K
2
200_0603

CLK_HCLK
CLK_HCLK#

F3
E3
E2

A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35

D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8
D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63

Mobile
NorthWood

HIT#
HITM#
DEFER#

H1
H4
H23
H26
A11
A13
A15
A17
A19
A21
A24
A26
A3
A9
AA1
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
AD1
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AD4
AD8

VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56

1
R87
1
R280

A10
A12
A14
A16
A18
A20
A8
AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19
B7
B9
C10
C12
C14
C16
C18
C20
C8
D11
D13
D15
D17
D19
D7
D9
E10

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HD#[0..63]

VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74

HA#[3..31]

F13
F15
F17
F19
F9
F11
E8
E20
E18
E16
E14
E12

U7A

HA#[3..31]

VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73

B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24

HD#[0..63] 7

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

NorthWood

+CPU_CORE

Title

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE
Size
Document Number
Custom
401207
Date:
A

, 18, 2004

Sheet
E

45

TRANSFERRED FROM THE CUSTODY OF

Rev
2A
of

83

VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
SKTOCC#
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128

H_INTR

H_PWRGD

PM_CPUPERF#

1
200

Place resistor <100mils from

CPU pin

H_TRDY#

F1
G5
F4
AB2
J6

16
16
16
16
16
16
16
16
16
16
7

H_A20M#
H_F_FERR#
H_IGNNE#
H_SMI#
H_PWRGD
H_STPCLK#
H_DPSLP#
H_INTR
H_NMI
H_INIT#
H_RESET#

H_A20M#
C6
H_F_FERR#
B6
H_IGNNE#
B2
H_SMI#
B5
H_PWRGD AB23
H_STPCLK#
Y4
H_DPSLP# AD25
H_INTR
D1
H_NMI
E5
H_INIT#
W5
H_RESET# AB25

7
7
13
13

H_DBSY#
H_DRDY#
H_BSEL0
H_BSEL1

H5
H2
AD6
AD5
H_THERMDA
H_THERMDC

+1.2VP
1
R66

H_THERMTRIP#

2
56

ITP_BPM0
ITP_BPM1
ITP_PRDY#
ITP_PREQ#

ITP_TCK
ITP_TDI
+1.2VP

ITP_TMS
ITP_TRST#

Murata LQG21F4R7N00

L3

ITP_TMS
ITP_TCK
ITP_TRST#
ITP_TDI

AC26
AD26

H_VSSA

L24
P1
R215

R67

51.1_1%

+CPU_CORE

2
R82
2
R62
2
R81
2
R68

NorthWood

51.1_1%

ITP_PREQ#
1
200_0603
ITP_PRDY#
1
200_0603
ITP_BPM0
1
200_0603
ITP_BPM1
1
200_0603

+H_GTLREF1
1

All of these pin

connected inside

GTLREF0
GTLREF1
GTLREF2
GTLREF3
NC1
NC2

AA21
AA6
F20
F6
A22
A7

TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
TESTHI10
GHI#

AD24
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6

TESTTHI0_1

DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3

E22
K22
R22
W22

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3

F21
J23
P23
W23

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

ADSTB#0
ADSTB#1

L5
R5

+CPU_CORE

TESTTHI2_7

TESTTHI8_10

1
R221
1
R223

2
56
2
56

1
R70

2
56

PM_CPUPERF#
H_DSTBN#[0..3]

H_DSTBP#[0..3]

H_ADSTB#0 7
H_ADSTB#1 7

E21
G25
P26
V21

DBR#

AE25

PROCHOT#
MCERR#
SLP#

C3
V6
AB26

H_PROCHOT#

VSSA
VSSSENSE

AD22
A4

H_VSSA
1

VCCA
VCCSENSE
VCCIOPLL
NC7
NC8

ITP_CLK0
ITP_CLK1
COMP0
COMP1

+CPU_CORE

1
R79

2
56

H_SLP#

H_SLP#
2
R218

NorthWood
3

C359
6,42
6,42
6,42
6,42
6,42

+5VALW

.1UF

GTL Reference Voltage

2
16
15
14
13
12
11
10
9

2
1

49.9_1%

1
EC_SMD2 29,32
THRM#
33

R25
C20

R_B

+H_GTLREF1
EC_SMC2 29,32

Trace width>=7mila

2 H_PROCHOT#
470

1
R287

Q23
3904

C21

100_1%
1UF_0603

220PF
4

NC
STBY
SMBCLK
NC
SMBDATA
ALERT
ADD0
NC

2
Q22
3904

R_A

470

PROCHOT#

R24

1
1
2

2
R38

R37

1K

10K

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

Address:1001_110X

NE1617/ MAX6654MEE

1
1K

2
R65

NC
VCC
DXP
DXN
NC
ADD1
GND
GND

33

10K

U6
1
2
3
4
5
6
7
8

1. Place R_A and R_B near CPU.

2. Place decoupling cap 220PF near CPU.(Within
500mils)

R36

R274

1K

Layout note :

2
2

C56
.1UF

+5VALW

16

+CPU_CORE

TP2

+CPU_CORE

1
200

AD2
AD3

NC3
NC4

R275

H_THERMDA
H_THERMDC

H_DBI#[0..3] 7

H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3

DBI#0
DBI#1
DBI#2
DBI#3

CPU_VR_VID4
CPU_VR_VID3
CPU_VR_VID2
CPU_VR_VID1
CPU_VR_VID0

W =15mil

C55
2200PF_0603

H_DSTBP#[0..3] 7

+1.2VP

+5VALW

Thermal Sensor
MAX6654MEE

PM_CPUPERF# 16
H_DSTBN#[0..3] 7

H_DBI#[0..3]

C231
33UF_D2_16V

8P4R_1.5K

THERMTRIP#

TCK
TDI
TDO
TMS
TRST#

AF25
AF3

Mobile

THERMDA
THERMDC

D4
C1
D5
F7
E6

AD20
A5
H_VCCIOPLL AE23

8
7
6
5

C19
33UF_D2_16V

RP21
1
2
3
4

DBSY#
DRDY#
BSEL0
BSEL1

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5

J26
K25
K26
L25

DP#0
DP#1
DP#2
DP#3

A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#
DPSLP#
LINT0
LINT1
INIT#
RESET#

AC6
AB5
AC4
Y6
AA5
AB4

H_VCCA
TP1

A2

4.7UH_80mA_0805
2
4.7UH_80mA_0805
2

L27

B3
C4

RS#0
RS#1
RS#2
RSP#
TRDY#

2
R78

H_INIT#

H_RS#0
H_RS#1
H_RS#2

VCCVID

H_RESET#

H_NMI

7
7
7

AF4

1
51.1_1%

2
R220

H_DPSLP#

NC5
NC6

H_F_FERR#

H_STPCLK#

AE21
AF24

1
56
1
300

H_IGNNE#

VID0
VID1
VID2
VID3
VID4

2
R80
2
R224

U7B

H_SMI#

AE5
AE4
AE3
AE2
AE1

H_A20M#

VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181

1
200
1
200
1
200
1
200
1
200
1
200
1
200
1
200

F8
G21
G24
G3
G6
J2
J22
J25
J5
K21
K24
K3
K6
L1
L23
L26
L4
M2
M22
M25
M5
N21
N24
N3
N6
P2
P22
P25
P5
R1
R23
R26
R4
T21
T24
T3
T6
U2
U22
U25
U5
V1
V23
V26
V4
W21
W24
W3
W6
Y2
Y22
Y25
Y5

2
R282
2
R77
2
R84
2
R72
2
R222
2
R285
2
R71
2
R83

AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE26
AE7
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF26
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
B26
B4
B8
C11
C13
C15
C17
C19
C2
C22
C25
C5
C7
C9
D10
D12
D14
D16
D18
D20
D21
D24
D3
D6
D8
E1
E11
E13
E15
E17
E19
E23
E26
E4
E7
E9
F10
F12
F14
F16
F18
F2
F22
F25
F5

+CPU_CORE

SCHEMATIC, M/B LA-1331

Size

Rev
2A

401207
Date:

TRANSFERRED FROM THE CUSTODY OF THE COMPE

Document Number

+5VALW
B

, 18, 2004

Sheet
E

46

of

83

Layout note :

Layout note :

Place close to CPU, Use 2~3 vias per PAD.

Place .22uF caps underneath balls on solder side.
Place 10uF caps on the peripheral near balls.
Use 2~3 vias per PAD.

Place close to CPU power and

ground pin as possible
(<1inch)

Please place these cap in the socket cavity area

Used ESR 25m ohm cap total ESR=2.5m ohm

+CPU_CORE

1
C382
+
220UF_D2_4V_25m

C383
+
220UF_D2_4V_25m

C384
220UF_D2_4V_25m

C381
+
@220UF_D2_4V_25m

1
C86
+
@220UF_D2_4V_25m

C390
220UF_D2_4V_25m

C68
+
220UF_D2_4V_25m
2

C57
+
220UF_D2_4V_25m

1
C385
+
220UF_D2_4V_25m

C331
10UF_6.3V_1206_X5R

C322
10UF_6.3V_1206_X5R

1
C316
10UF_6.3V_1206_X5R

C307
10UF_6.3V_1206_X5R

C299
10UF_6.3V_1206_X5R

+CPU_CORE

+CPU_CORE

1
C380
+
220UF_D2_4V_25m

C332
10UF_6.3V_1206_X5R

C323
10UF_6.3V_1206_X5R

C317
10UF_6.3V_1206_X5R

C308
10UF_6.3V_1206_X5R

+
C300
10UF_6.3V_1206_X5R

+CPU_CORE

Please place these cap on the socket north side

C341
.22UF_X7R

C340
.22UF_X7R

C339
.22UF_X7R

C338
.22UF_X7R

1
C293
.22UF_X7R

C294
.22UF_X7R

C295
.22UF_X7R

1
C296
.22UF_X7R

1
C297
.22UF_X7R

C52
10UF_6.3V_1206_X5R

C45
10UF_6.3V_1206_X5R

1
C30
10UF_6.3V_1206_X5R

C26
10UF_6.3V_1206_X5R

C24
10UF_6.3V_1206_X5R

+CPU_CORE

+CPU_CORE

C342
.22UF_X7R

C302
10UF_6.3V_1206_X5R

C22
10UF_6.3V_1206_X5R

C65
10UF_6.3V_1206_X5R

C62
10UF_6.3V_1206_X5R

+CPU_CORE

C311
10UF_6.3V_1206_X5R

1
C344
10UF_6.3V_1206_X5R

C329
10UF_6.3V_1206_X5R

C320
10UF_6.3V_1206_X5R

+CPU_CORE

C351
10UF_6.3V_1206_X5R

CPU Voltage ID
+3VS

Please place these cap on the socket south side

C49
10UF_6.3V_1206_X5R

C37
10UF_6.3V_1206_X5R

5,42
5,42
5,42
5,42
5,42

CPU_VR_VID0
CPU_VR_VID1
CPU_VR_VID2
CPU_VR_VID3
CPU_VR_VID4

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4

5,42
5,42
5,42
5,42
5,42

C298
10UF_6.3V_1206_X5R

C286
10UF_6.3V_1206_X5R

C64
10UF_6.3V_1206_X5R

C59
10UF_6.3V_1206_X5R

+CPU_CORE

RP50
8P4R_1K
8
7
6
5

R362
1K

1
C28
10UF_6.3V_1206_X5R

C25
10UF_6.3V_1206_X5R

1
2

C23
10UF_6.3V_1206_X5R

1
2
3
4

+CPU_CORE
3

C305
10UF_6.3V_1206_X5R

1
C335
10UF_6.3V_1206_X5R

C325
10UF_6.3V_1206_X5R

C315
10UF_6.3V_1206_X5R

+CPU_CORE

C348
10UF_6.3V_1206_X5R

EMI Clip PAD for CPU

PAD1

PAD2
1

PAD3
1

COMPAL ELECTRONICS, INC

PAD-2.5X3

PAD-2.5X3

PAD-2.5X3

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331 TRANSFERRED

Size

Document Number

Rev
2A

401207
Date:
A

FROM THE CUSTODY OF THE COMPE

, 18, 2004

Sheet
E

47

of

83

HD#[0..63]

HD#[0..63] 4

HSWNG0
HSWNG1

2
1

AC2
AC13
1

R_E

ST0
ST1
ST2

AGP_ADSTB0
AGP_ADSTB0#
AGP_ADSTB1
AGP_ADSTB1#
AGP_SBSTB
AGP_SBSTB#

AGP_ADSTB0
AGP_ADSTB0#
AGP_ADSTB1
AGP_ADSTB1#
AGP_SBSTB
AGP_SBSTB#

R24
R23
AC27
AC28
AF27
AF26

AD_STB0
AD_STB#0
AD_STB1
AD_STB#1
SB_STB
SB_STB#

14
14
14
14
14
14
14
14
14

AGP_FRAME#
AGP_DEVSEL#
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_PAR
AGP_REQ#
AGP_GNT#
AGP_PIPE#

AGP_FRAME#
AGP_DEVSEL#
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_PAR
AGP_REQ#
AGP_GNT#
AGP_PIPE#

Y24
W28
W27
W24
W23
W25
AG24
AH25
AF22

G_FRAME#
G_DEVSEL#
G_IRDY#
G_TRDY#
G_STOP#
G_PAR
G_REQ#
G_GNT#
PIPE#

Trace
width>=7mila

49.9_1%

1UF_0603

220PF

GTL Reference Voltage

1. Place R_E and R_F near MCH

2. Place decoupling cap 220PF near MCH pin.(Within 500mils)

AGP_ADSTB0

2
R265

AGP_ADSTB0#
1
@8.2K

2
R247

1
8.2K

AGP_ADSTB1

2
R239

AGP_ADSTB1#
1
@8.2K

2
R230

1
8.2K

AGP_SBSTB

2
R231

Place closely
ball P26

C292
.1UF

Place closely pin P22

CLK_AGP_MCH
2

RBF#
WBF#

AE22
AE23

AGP_RBF#
AGP_WBF#

VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40

A19
A23
A27
D5
D9
D13
D17
D21
E1
E4
E26
E29
F8
F12
F16
F20
F24
G26
H9
H11
H13
H15
H17
H19
H21
J1
J4
J6
J22
J29

AGP_ST0
0=System memory is DDR
1=System memory is SDR

AGP_ST0

**

2
R213

1
2K

2
R216

RP18
AGP_FRAME# 1
AGP_TRDY# 2
AGP_PAR
3
AGP_STOP# 4

@8P4R_8.2K
8
7
6
5

RP17
AGP_GNT#
1
AGP_REQ#
2
AGP_IRDY# 3
AGP_DEVSEL# 4

@8P4R_8.2K
8
7
6
5

RP15
1
2
3
4

@8P4R_8.2K
8
7
6
5

AGP_WBF#
AGP_PIPE#
AGP_RBF#

1
8.2K

2
R262

2
R237
CLK_AGP_MCH

1
36.5_1%

R268
@33

CLK_AGP_MCH 13

AGP_RBF# 14
AGP_WBF# 14

@10PF

+1.5VS

R51
1K_1%_0603

Place this cap near AGP Conn.

+AGP_NBREF
R56
1K_1%_0603

C120
.1UF

HUB Interface Reference

+1.8VS

Layout note :
1. Place R_C and R_D in middle of Bus.
2. Place capacitors near MCH.

R290
301_1%

C313

Layout note :

R209
150_1%

P22

+1.5VS
C337

100_1%

H_DSTBN#[0..3] 5
H_DSTBP#[0..3] 5

C238
.01UF

Place this cap near MCH

+AGP_VGAREF

BROOKDALE(MCH-M)

+1.5VS
4

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

+CPU_CORE

R210
301_1%

AD25

C319
.01UF

C326

14
14
14
14
14
14

N22
K27
K5
L24
M23
K7
J26
A3
A7
A11
A15

R269

R_F

H_DSTBN#[0..3]
H_DSTBP#[0..3]

AA21

AGP_SBA[0..7] 14

1
AG25
AF24
AG26

R273

24.9_0603_1%
2

24.9_0603_1%

AGPREF

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

AGP_ST0
AGP_ST1
AGP_ST2

+CPU_CORE

BROOKDALE(MCH-M)
R252

+VS_HUBREF

14 AGP_ST[0..2]

R238

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

GRCOMP

R260
150_1%

HRCOMP0
HRCOMP1

M7
R8
Y8
AB11
AB17

AGP_SBA[0..7]
AH28
AH27
AG28
AG27
AE28
AE27
AE24
AE25

66IN

+V_MCH_GTLREF
HVREF0
HVREF1
HVREF2
HVREF3
HVREF4

+1.8VS

2
36.5_1%

1
@8.2K

AGP_ST1
AGP_ST2

AGP_SBSTB#
1
@8.2K

2
R212
2
R214

*
*

R_C

C373
@470PF

R291
@56.2_1%

+VS_HUBREF
R286
0
R289
301_1%

R_D
AGP_ST1
0=533Mhz
1=400Mhz

1
8.2K

AA7
AD13

1
R270

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

HLRCOMP

AD4
AE6
AE11
AC15
AD3
AE7
AD11
AC16

P27
P26

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

DBI#0
DBI#1
DBI#2
DBI#3

HLRCOMP
HI_REF

HUB_PSTRB 16
HUB_PSTRB# 16

H_SWNG0
H_SWNG1

C290
.01UF

AD5
AG4
AH9
AD15

N25
N24

H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3

G_C/BE#0
G_C/BE#1
G_C/BE#2
G_C/BE#3

HI_STB
HI_STB#

HUB_PD[0..10] 16

HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10

BCLK
BCLK#

V25
V23
Y25
AA23

P25
P24
N27
P23
M26
M25
L28
L27
M27
N28
M24

J8
K8

AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3

HI_0
HI_1
HI_2
HI_3
HI_4
HI_5
HI_6
HI_7
HI_8
HI_9
HI_10

1
8.2K

1 2

H_DBI#[0..3]

+CPU_CORE

R254
301_1%

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

H_DBI#[0..3]

CLK_GHT
CLK_GHT#

CLK_GHT
CLK_GHT#

U6
T7
R7
U5
U2

G_AD0
G_AD1
G_AD2
G_AD3
G_AD4
G_AD5
G_AD6
G_AD7
G_AD8
G_AD9
G_AD10
G_AD11
G_AD12
G_AD13
G_AD14
G_AD15
G_AD16
G_AD17
G_AD18
G_AD19
G_AD20
G_AD21
G_AD22
G_AD23
G_AD24
G_AD25
G_AD26
G_AD27
G_AD28
G_AD29
G_AD30
G_AD31

C368
.01UF

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

RS#0
RS#1
RS#2

R27
R28
T25
R25
T26
T27
U27
U28
V26
V27
T23
U23
T24
U24
U25
V24
Y27
Y26
AA28
AB25
AB27
AA27
AB26
Y23
AB23
AA24
AA25
AB24
AC25
AC24
AC22
AD24

13
13

HREQ#[0..4]

W2
W7
W6

14 AGP_C/BE#[0..3]

HUB_PD[0..10]

U5B
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

H_RS#0
H_RS#1
H_RS#2
HREQ#[0..4]

AGP_AD[0..31]

5
5
5
4

CPURST#
HTRDY#
DEFER#
BPRI#
HLOCK#
RSTIN#
TESTIN#
DBSY#
DRDY#
HIT#
HITM#
BREQ#0
ADS#
BNR#

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

HOST

H_DBSY#
H_DRDY#
HIT#
HITM#
HBR0#
HADS#
HBNR#

HADSTB#0
HADSTB#1

AE17
U7
Y4
Y7
W5
J27
H26
V5
V4
Y5
Y3
V7
V3
W3

5
H_RESET#
5
H_TRDY#
4
HDEFER#
2
4
HBPRI#
4
HLOCK#
14,16,19,20,21,22,23,24,27,28,34 PCIRST#
5
5
4
4
4
4
4

R5
N6

AA2
AB5
AA5
AB3
AB4
AC5
AA3
AA6
AE3
AB7
AD7
AC7
AC6
AC3
AC8
AE2
AG5
AG2
AE8
AF6
AH2
AF3
AG3
AE5
AH7
AH3
AF4
AG8
AG7
AG6
AF8
AH5
AC11
AC12
AE9
AC9
AE10
AD9
AG9
AC10
AE12
AF10
AG11
AG10
AH11
AG12
AE13
AF12
AG13
AH13
AC14
AF14
AG14
AE14
AG15
AG16
AG17
AH15
AC17
AF16
AE15
AH17
AD17
AE16

H_ADSTB#0
H_ADSTB#1

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

AGP

5
5

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

T4
T5
T3
U3
R3
P7
R2
P4
R6
P5
P3
N2
N7
N3
K4
M4
M3
L3
L5
K3
J2
M5
J3
L2
H4
N5
G2
M6
L7

HUB

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

14 AGP_AD[0..31]

U5A

HA#[3..31]

HA#[3..31]

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

Size

TRANSFERRED FROM THE CUSTODY OF THE COMPE

Document Number

Rev
2A

401207
Date:
A

, 18, 2004

Sheet
E

48

of

83

U5D
U5C

VCC1_8_0
VCC1_8_1
VCC1_8_2
VCC1_8_3
VCC1_8_4

L29
N26
L25
M22
N23

VCCGA1
VCCHA1

T17
T13

VCC_MCH_PLL1
VCC_MCH_PLL0

VSSGA2
VSSHA2

U17
U13

VSS_MCH_PLL1
VSS_MCH_PLL0

+1.5VS

L34

L33
4.7UH_30mA
2

4.7UH_30mA

"Trace A"

"Trace A"
AA4
AA8
AA29
AB6
AB9
AB10
AB12
AB13
AB14
AB15
AB16
AB19
AB22
AC1
AC4
AC18
AC20
AC21
AC23
AC26
AD6
AD8
AD10
AD12
AD14
AD16
AD19
AD22
AE1
AE4
AE18
AE20
AE29
AF5
AF7
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF25
AG1
AG18
AG20
AG22
AH19
AH21
AH23
AJ3
AJ5
AJ7
AJ9
AJ11
AJ13
AJ15
AJ17
AJ27

C310
33UF_D2_16V

C309
33UF_D2_16V

"Trace A"

Layout note :
Trace width 5mil ; Spacing
10mil
Trace A to ball U7/T13 or
U7/T7 =1.5" Max

10 DDR_CB[0..7]

DDR_SDQ0
DDR_SDQ1
DDR_SDQ2
DDR_SDQ3
DDR_SDQ4
DDR_SDQ5
DDR_SDQ6
DDR_SDQ7
DDR_SDQ8
DDR_SDQ9
DDR_SDQ10
DDR_SDQ11
DDR_SDQ12
DDR_SDQ13
DDR_SDQ14
DDR_SDQ15
DDR_SDQ16
DDR_SDQ17
DDR_SDQ18
DDR_SDQ19
DDR_SDQ20
DDR_SDQ21
DDR_SDQ22
DDR_SDQ23
DDR_SDQ24
DDR_SDQ25
DDR_SDQ26
DDR_SDQ27
DDR_SDQ28
DDR_SDQ29
DDR_SDQ30
DDR_SDQ31
DDR_SDQ32
DDR_SDQ33
DDR_SDQ34
DDR_SDQ35
DDR_SDQ36
DDR_SDQ37
DDR_SDQ38
DDR_SDQ39
DDR_SDQ40
DDR_SDQ41
DDR_SDQ42
DDR_SDQ43
DDR_SDQ44
DDR_SDQ45
DDR_SDQ46
DDR_SDQ47
DDR_SDQ48
DDR_SDQ49
DDR_SDQ50
DDR_SDQ51
DDR_SDQ52
DDR_SDQ53
DDR_SDQ54
DDR_SDQ55
DDR_SDQ56
DDR_SDQ57
DDR_SDQ58
DDR_SDQ59
DDR_SDQ60
DDR_SDQ61
DDR_SDQ62
DDR_SDQ63

G28
F27
C28
E28
H25
G27
F25
B28
E27
C27
B25
C25
B27
D27
D26
E25
D24
E23
C22
E21
C24
B23
D22
B21
C21
D20
C19
D18
C20
E19
C18
E17
E13
C12
B11
C10
B13
C13
C11
D10
E10
C9
D8
E8
E11
B9
B7
C7
C6
D6
D4
B3
E6
B5
C4
E5
C3
D3
F4
F3
B2
C2
E2
G5

SDQ0
SDQ1
SDQ2
SDQ3
SDQ4
SDQ5
SDQ6
SDQ7
SDQ8
SDQ9
SDQ10
SDQ11
SDQ12
SDQ13
SDQ14
SDQ15
SDQ16
SDQ17
SDQ18
SDQ19
SDQ20
SDQ21
SDQ22
SDQ23
SDQ24
SDQ25
SDQ26
SDQ27
SDQ28
SDQ29
SDQ30
SDQ31
SDQ32
SDQ33
SDQ34
SDQ35
SDQ36
SDQ37
SDQ38
SDQ39
SDQ40
SDQ41
SDQ42
SDQ43
SDQ44
SDQ45
SDQ46
SDQ47
SDQ48
SDQ49
SDQ50
SDQ51
SDQ52
SDQ53
SDQ54
SDQ55
SDQ56
SDQ57
SDQ58
SDQ59
SDQ60
SDQ61
SDQ62
SDQ63

DDR_CB0
DDR_CB1
DDR_CB2
DDR_CB3
DDR_CB4
DDR_CB5
DDR_CB6
DDR_CB7

C16
D16
B15
C14
B17
C17
C15
D14

SDQ64/CB0
SDQ65/CB1
SDQ66/CB2
SDQ67/CB3
SDQ68/CB4
SDQ69/CB5
SDQ70/CB6
SDQ71/CB7

J21
J9

SDREF0
SDREF1

DDR_CB[0..7]

SCK0
SCK#0
SCK1
SCK#1
SCK2
SCK#2

E14
F15
J24
G25
G6
G7

DDR_CLK0 10
DDR_CLK0# 10
DDR_CLK1 10
DDR_CLK1# 10
DDR_CLK2 10
DDR_CLK2# 10

SCK3
SCK#3
SCK4
SCK#4
SCK5
SCK#5

G15
G14
E24
G24
H5
F5

DDR_CLK3 11
DDR_CLK3# 11
DDR_CLK4 11
DDR_CLK4# 11
DDR_CLK5 11
DDR_CLK5# 11

SCK6
SCK#6
SCK7
SCK#7
SCK8
SCK#8

K25
J25
G17
G16
H7
H6

SCS#0
SCS#1
SCS#2
SCS#3
SCS#4
SCS#5

E9
F7
F9
E7
G9
G10

DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3

SDQS0
SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDQS8

F26
C26
C23
B19
D12
C8
C5
E3
E15

DDR_SDQS0
DDR_SDQS1
DDR_SDQS2
DDR_SDQS3
DDR_SDQS4
DDR_SDQS5
DDR_SDQS6
DDR_SDQS7
DDR_SDQS8

SMA0/CS#11
SMA1/CS#10
SMA2/CS#6
SMA3/CS#9
SMA4/CS#5
SMA5/CS#8
SMA6/CS#7
SMA7/CS#4
SMA8/CS#3
SMA9/CS#0
SMA10
SMA11/CS#2
SMA12/CS#1

E12
F17
E16
G18
G19
E18
F19
G21
G20
F21
F13
E20
G22

DDR_SMA0
DDR_SMA1
DDR_SMA2
DDR_SMA3
DDR_SMA4
DDR_SMA5
DDR_SMA6
DDR_SMA7
DDR_SMA8
DDR_SMA9
DDR_SMA10
DDR_SMA11
DDR_SMA12

SBS0
SBS1

G12
G13

DDR_SBS0
DDR_SBS1

SCKE0
SCKE1
SCKE2
SCKE3
SCKE4
SCKE5

G23
E22
H23
F23
J23
K23

DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3

DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3

10,11
10,11
11
11

DDR_SDQS0
DDR_SDQS1
DDR_SDQS2
DDR_SDQS3
DDR_SDQS4
DDR_SDQS5
DDR_SDQS6
DDR_SDQS7
DDR_SDQS8

10
10
10
10
10
10
10
10
10

DDR_SMA[0..12]

SMRCOMP
RCVENIN#
RCVENOUT#

J28
G3
H3

SSI_ST

H27

SRAS#
SWE#
SCAS#

F11
G11
G8

NC0
NC1

C346
.1UF_0402_X5R

DDR_SMA[0..12] 10,11
2

DDR_SBS0 10,11
DDR_SBS1 10,11
DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3
R75
2

SM_RCOMP
R CVIN#
RCVOUT# 2
R283

10,11
10,11
11
11

30.1_1%
1

1
0_0402

Layout note
Place R637
closely pinJ28

+1.25VS

C69

.1UF_0402_X5R

C358

@47PF

R_J
DDR_SRAS#
DDR_SWE#
DDR_SCAS#

DDR_SRAS# 10,11
DDR_SWE# 10,11
DDR_SCAS# 10,11

AD26
AD27

Layout note
Place R_J closely Ball
H3<40mil,Ball H3 to G3 trace
must
routing 1"

+SDREF

VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141

Murata LQG21N4R7K10

+1.8VS

VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82

N14
N16
P13
P15
P17
R14
R16
T15
U14
U16

L1
L4
L6
L8
L22
L26
N1
N4
N8
N13
N15
N17
N29
P6
P8
P14
P16
R1
R4
R13
R15
R17
R26
T6
T8
T14
T16
T22
U1
U4
U15
U29
V6
V8
V22
W1
W4
W8
W26
Y6
Y22
AA1

VCC1_5_16
VCC1_5_17
VCC1_5_18
VCC1_5_19
VCC1_5_20
VCC1_5_21
VCC1_5_22
VCC1_5_23
VCC1_5_24
VCC1_5_25

DDR_SDQ[0..63]

10 DDR_SDQ[0..63]

+1.5VS

"Trace A"

POWER/GND

VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38

R22
R29
U22
U26
W22
W29
AA22
AA26
AB21
AC29
AD21
AD23
AE26
AF23
AG29
AJ25

MEMORY

A5
A9
A13
A17
A21
A25
C1
C29
D7
D11
D15
D19
D23
D25
F6
F10
F14
F18
F22
G1
G4
G29
H8
H10
H12
H14
H16
H18
H20
H22
H24
K22
K24
K26
L23
K6
J5
J7

VCC1_5_0
VCC1_5_1
VCC1_5_2
VCC1_5_3
VCC1_5_4
VCC1_5_5
VCC1_5_6
VCC1_5_7
VCC1_5_8
VCC1_5_9
VCC1_5_10
VCC1_5_11
VCC1_5_12
VCC1_5_13
VCC1_5_14
VCC1_5_15

+2.5V

VTT_0
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18

M8
U8
AA9
AB8
AB18
AB20
AC19
AD18
AD20
AE19
AE21
AF18
AF20
AG19
AG21
AG23
AJ19
AJ21
AJ23

+CPU_CORE

BROOKDALE(MCH-M)

Layout note
Please closely pinJ21 and J9

BROOKDALE(MCH-M)
4

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331 TRANSFERRED

Size

Document Number

Rev
2A

401207
Date:
A

FROM THE CUSTODY OF THE COMPE

, 18, 2004

Sheet
E

49

of

83

Layout note : DDR Memory interface

Processor system bus

Layout note :

Distribute as close as possible

to MCH Processor Quadrant.(between VCCSM and VSS pin)

Distribute as close as possible

to MCH Processor Quadrant.(between VTTFSB and VSS pin)

+CPU_CORE

+2.5V

C369
.1UF_0402_X5R

C377
22UF_10V_1206

C347
22UF_10V_1206

1
C353
.1UF_0402_X5R

C375
.1UF_0402_X5R

1
C365
.1UF_0402_X5R

C374
.1UF_0402_X5R

1
C362
.1UF_0402_X5R

C247
.1UF_0402_X5R

1
C251
.1UF_0402_X5R

1
C270
.1UF_0402_X5R

1
C283
.1UF_0402_X5R

C284
.1UF_0402_X5R

+2.5V

1
C364
.1UF_0402_X5R

C367
.1UF_0402_X5R

C343
.1UF_0402_X5R

1
C366
.1UF_0402_X5R

C250
.1UF_0402_X5R

1
C256
.1UF_0402_X5R

1
C266
.1UF_0402_X5R

1
C261
.1UF_0402_X5R

1
C265
.1UF_0402_X5R

+CPU_CORE

C363
.1UF_0402_X5R

+2.5V

1
C360
.1UF_0402_X5R

1
C352
.1UF_0402_X5R

1
C349
.1UF_0402_X5R

1
C288
10UF_6.3V_1206_X5R

C345
.1UF_0402_X5R
C

C289
10UF_6.3V_1206_X5R

C245
10UF_6.3V_1206_X5R

+CPU_CORE

+2.5V

C378
150UF_D2_6.3V

Layout note : AGP/CORE

Distribute as close as possible
to MCH Processor Quadrant.(between VCCAGP/VCCCORE
and VSS pin)

1
C291
.1UF_0402_X5R

1
C285
.1UF_0402_X5R

1
C268
.1UF_0402_X5R

1
C304
.1UF_0402_X5R

1
C303
.1UF_0402_X5R

+1.5VS

C312
.1UF_0402_X5R

1
C334
10UF_6.3V_1206_X5R

C244
150UF_D2_6.3V

C314
10UF_6.3V_1206_X5R

+1.5VS

Layout note : Hub-Link

Distribute as close as possible
to MCH Processor Quadrant.(between VCCHL and VSS pin)

C328
.1UF_0402_X5R

1
C324
.1UF_0402_X5R

1
2

C58
10UF_6.3V_1206_X5R

+1.8VS

C333
.1UF_0402_X5R

Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

Size

TRANSFERRED FROM THE CUSTODY OF THE

Document Number

Rev
2A

401207
Date:
5

, 18, 2004

Sheet
1

50

of

83

DDR_SDQ0
DDR_SDQ6

DDR_SDQ3
DDR_SDQ2

RP47
1
2
RP46
1
2

4P2R_22
DDR_DQ0
4
DDR_DQ6
3
4P2R_22
DDR_DQ3
4
DDR_DQ2
3

RP45
1
2

4P2R_22
DDR_DQ8
4
DDR_DQ12
3

RP44
1
2

4P2R_22
DDR_DQS1
4
DDR_DQ14
3

DDR_SDQ19
DDR_SDQ17

RP43
1
2

4P2R_22
DDR_DQ19
4
DDR_DQ17
3

DDR_SDQS2
DDR_SDQ21

RP42
1
2

4P2R_22
DDR_DQS2
4
DDR_DQ21
3

DDR_SDQ23
DDR_SDQ31

RP41
1
2

4P2R_22
DDR_DQ23
4
DDR_DQ31
3

RP40
1
2

4P2R_22
DDR_DQ27
4
DDR_DQ25
3

DDR_SDQ8
DDR_SDQ12
1

DDR_SDQS1
DDR_SDQ14

DDR_SDQ27
DDR_SDQ25

DDR_SDQ26
DDR_SDQS3

RP39
1
2

4P2R_22
DDR_DQ26
4
DDR_DQS3
3

DDR_CB4
DDR_CB5

RP38
1
2

4P2R_22
DDR_F_CB4
4
DDR_F_CB5
3

RP37
1
2

4P2R_22
DDR_F_CB6
4
DDR_F_CB3
3

DDR_CB6
DDR_CB3

DDR_SDQ4
DDR_SDQ5

DDR_SDQ1
DDR_SDQS0

DDR_SMA8
DDR_SMA6

DDR_SMA3
DDR_SMA1

RP48
1
2

4P2R_10
DDR_F_SMA12
4
DDR_F_SMA9
3

RP36
1
2

4P2R_10
DDR_F_SMA8
4
DDR_F_SMA6
3

RP35
1
2

RP34
DDR_SBS0 1
DDR_SWE# 2

8,11 DDR_SBS0
8,11 DDR_SWE#

4P2R_10
DDR_F_SMA3
4
DDR_F_SMA1
3
4P2R_10
4 DDR_F_SBS0
3 DDR_F_SWE#

RP33
1
2

8,11 DDR_SCAS#
8,11 DDR_SRAS#
4P2R_22
DDR_DQ36
4
DDR_DQ37
3

DDR_SDQS4
DDR_SDQ33

RP32
1
2

4P2R_22
DDR_DQS4
4
DDR_DQ33
3

DDR_SDQ34
DDR_SDQ44

RP31
1
2

4P2R_22
DDR_DQ34
4
DDR_DQ44
3

DDR_SDQ41
DDR_SDQ43

RP30
1
2

4P2R_22
DDR_DQ41
4
DDR_DQ43
3

DDR_SDQ47
DDR_SDQ46

RP29
1
2

4P2R_22
DDR_DQ47
4
DDR_DQ46
3

RP28
1
2

4P2R_22
DDR_DQ48
4
DDR_DQ49
3

RP27
1
2

4P2R_22
DDR_DQ50
4
DDR_DQ54
3

DDR_SDQ57
DDR_SDQ60

RP26
1
2

4P2R_22
DDR_DQ57
4
DDR_DQ60
3

DDR_SDQ62
DDR_SDQ59

RP49
1
2

4P2R_22
DDR_DQ62
4
DDR_DQ59
3

DDR_SDQ36
DDR_SDQ37

DDR_SDQ48
DDR_SDQ49

DDR_SDQ50
DDR_SDQ54
4

RP74
1
2

4P2R_22
DDR_DQ7
4
DDR_DQ15
3

DDR_SDQ9
DDR_SDQ13

RP72
1
2

4P2R_22
DDR_DQ9
4
DDR_DQ13
3

DDR_SDQ11
DDR_SDQ10

RP71
1
2

4P2R_22
DDR_DQ11
4
DDR_DQ10
3

DDR_SDQ20
DDR_SDQ16

RP70
1
2

4P2R_22
DDR_DQ20
4
DDR_DQ16
3

DDR_SDQ22
DDR_SDQ18

RP69
1
2

4P2R_22
DDR_DQ22
4
DDR_DQ18
3

DDR_SDQ29
DDR_SDQ24

RP68
1
2

4P2R_22
DDR_DQ29
4
DDR_DQ24
3

DDR_SDQ28
DDR_SDQ30

RP67
1
2

4P2R_22
DDR_DQ28
4
DDR_DQ30
3

DDR_SDQS8
DDR_CB7

RP66
1
2

4P2R_22
DDR_DQS8
4
DDR_F_CB7
3

DDR_CB1
DDR_CB0

RP65
1
2

4P2R_22
DDR_F_CB1
4
DDR_F_CB0
3

DDR_SMA7
DDR_SMA11

4P2R_22
DDR_F_CB2
4
3

RP63
1
2

4P2R_10
4 DDR_F_SMA7
3 DDR_F_SMA11

DDR_SMA4
DDR_SMA5

RP62
1
2

4P2R_10
4 DDR_F_SMA4
3 DDR_F_SMA5

DDR_SMA10
DDR_SMA0

RP61
1
2

4P2R_10
4 DDR_F_SMA10
3 DDR_F_SMA0

RP60
1
2

4P2R_10
4 DDR_F_SCAS#
3 DDR_F_SRAS#

DDR_SDQ32
DDR_SDQ39

RP59
1
2

4P2R_22
DDR_DQ32
4
DDR_DQ39
3

DDR_SDQ35
DDR_SDQ38

RP58
1
2

4P2R_22
DDR_DQ35
4
DDR_DQ38
3

DDR_SDQ42
DDR_SDQS5

RP56
1
2

4P2R_22
DDR_DQ42
4
DDR_DQS5
3

RP57
1
2

4P2R_22
DDR_DQ40
4
DDR_DQ45
3

DDR_SCAS#
DDR_SRAS#

DDR_SDQ40
DDR_SDQ45

DDR_SDQ55
DDR_SDQ52

RP55
1
2

4P2R_22
DDR_DQ55
4
DDR_DQ52
3

DDR_SDQS6
DDR_SDQ53

RP54
1
2

4P2R_22
DDR_DQS6
4
DDR_DQ53
3

DDR_SDQ51
DDR_SDQ56

RP53
1
2

4P2R_22
DDR_DQ51
4
DDR_DQ56
3

DDR_SDQ61
DDR_SDQS7

RP52
1
2

4P2R_22
DDR_DQ61
4
DDR_DQS7
3

DDR_SDQ58
DDR_SDQ63

RP51
1
2

4P2R_22
DDR_DQ58
4
DDR_DQ63
3

DDR_DQ[0..63]
+SDREF
DDR_F_CB[0..7]

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

DDR_DQ4
DDR_DQ0
DDR_DQS0
DDR_DQ3
DDR_DQ7
DDR_DQ15
DDR_DQ8
DDR_DQS1
DDR_DQ9
DDR_DQ14
8
8

DDR_CLK1
DDR_CLK1#

DDR_DQ19
DDR_DQ20

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_DQS2
DDR_DQ22
DDR_DQ23
DDR_DQ29
DDR_DQ27
DDR_DQS3
DDR_DQ28
DDR_DQ30
DDR_F_CB4
DDR_F_CB6
DDR_DQS8
DDR_F_CB1
DDR_F_CB3

8
8

DDR_CLK0
DDR_CLK0#
DDR_CKE1

8,11 DDR_CKE1
RP64
1
2

+2.5V

JP26

4P2R_22
DDR_DQ1
4
DDR_DQS0
3

RP73
1
2

+2.5V

4P2R_22
DDR_DQ4
4
DDR_DQ5
3

DDR_SDQ7
DDR_SDQ15

DDR_CB2
DDR_SMA12
DDR_SMA9

RP75
1
2

DDR_F_SMA12
DDR_F_SMA9
DDR_F_SMA7
DDR_F_SMA5
DDR_F_SMA3
DDR_F_SMA1

8,11 DDR_SCS#0

DDR_F_SMA10
DDR_F_SBS0
DDR_F_SWE#
DDR_SCS#0
DDR_DQ36
DDR_DQ32
DDR_DQS4
DDR_DQ35
DDR_DQ34
DDR_DQ42
DDR_DQ41
DDR_DQS5
DDR_DQ40
DDR_DQ47

DDR_DQ55
DDR_DQ48
DDR_DQS6
DDR_DQ50
DDR_DQ51
DDR_DQ57
DDR_DQ60
DDR_DQS7
DDR_DQ62
DDR_DQ58
11,13 DIMM_SMDATA
11,13 DIMM_SMCLK
+3VS

VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID

VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS#
CAS#
S1#
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_DQS[0..8]
DDR_DQ5
DDR_DQ6

C475

DDR_SMA[0..12]

.1UF

DDR_SDQ[0..63]

DDR_DQ1

DDR_CB[0..7]

DDR_DQ2
DDR_DQ12

DDR_SDQS[0..8]

DDR_DQ[0..63] 11
DDR_F_CB[0..7] 11
DDR_DQS[0..8] 11
DDR_SMA[0..12] 8,11
DDR_SDQ[0..63] 8
DDR_CB[0..7] 8
DDR_SDQS[0..8] 8
1

DDR_DQ13
DDR_DQ11
DDR_DQ10

DDR_DQ17
DDR_DQ16
DDR_DQ21
DDR_DQ18
DDR_DQ31
DDR_DQ24
DDR_DQ25
DDR_DQ26
DDR_F_CB5
DDR_F_CB7
DDR_F_CB0
2

DDR_F_CB2

DDR_CKE0

DDR_CKE0 8,11

DDR_F_SMA11
DDR_F_SMA8
DDR_F_SMA6
DDR_F_SMA4
DDR_F_SMA2
DDR_F_SMA0
DDR_F_SBS1
DDR_F_SRAS#
DDR_F_SCAS#

2
R157

1
10

DDR_SMA2

2
R158

1
10

DDR_SBS1

DDR_SBS1 8,11

DDR_SCS#1 8,11
DDR_DQ37
DDR_DQ39
DDR_DQ33
DDR_DQ38
DDR_DQ44
DDR_DQ43
3

DDR_DQ45
DDR_DQ46
DDR_CLK2# 8
DDR_CLK2 8
DDR_DQ52
DDR_DQ49
DDR_DQ53
DDR_DQ54
DDR_DQ56
DDR_DQ61
DDR_DQ59
DDR_DQ63

DDR-SODIMM_200_REVERSE
4

DIMM0

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

Size

TRANSFERRED FROM THE CUSTODY OF THE COMPE

Document Number

Rev
2A

401207
, 18, 2004

Date:
A

Sheet

51
H

of

83

DDR_F_CB[0..7]

10 DDR_F_CB[0..7]

+2.5V

DDR_DQS[0..8]

10 DDR_DQS[0..8]

+SDREF
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

DDR_DQ5
DDR_DQ6
+1.25VS

8,10 DDR_CKE0
8,10 DDR_CKE1

+1.25VS

DDR_DQ4
DDR_DQ0

RP134
1
2

4P2R_56
4
3

RP107
4
3

4P2R_56
DDR_DQ5
1
DDR_DQ6
2

DDR_DQ3
DDR_DQ7

RP133
1
2

4P2R_56
4
3

RP106
4
3

4P2R_56
DDR_DQS0
1
DDR_DQ1
2

8,10 DDR_SBS1
8,10 DDR_SRAS#

8,10 DDR_SCS#0
8,10 DDR_SCS#1

DDR_DQS0
DDR_DQ1

DDR_SBS1
DDR_SRAS#

RP119
1
2

4P2R_56
4
3

RP92
4
3

4P2R_56
DDR_SWE#
1
DDR_SBS0
2

DDR_SCS#0
DDR_SCS#1

RP91
1
2

4P2R_56
4
3

RP117
4
3

4P2R_56
DDR_SCS#2
1
DDR_DQ37
2

DDR_DQ15
DDR_DQ8

RP132
1
2

4P2R_56
4
3

RP105
4
3

4P2R_56
DDR_DQ2
1
DDR_DQ12
2

4P2R_56
4
3

RP116
4
3

4P2R_56
DDR_DQ39
1
DDR_DQS4
2

DDR_DQ9
DDR_DQ14

RP131
1
2

4P2R_56
4
3

RP104
4
3

4P2R_56
DDR_DQ13
1
DDR_DQS1
2

DDR_DQ36
DDR_DQ32

RP90
1
2

4P2R_56
4
3

RP115
4
3

4P2R_56
DDR_DQ33
1
DDR_DQ38
2

DDR_DQ19
DDR_DQ20

RP129
1
2

4P2R_56
4
3

RP130
4
3

4P2R_56
DDR_DQ11
1
DDR_DQ10
2

RP89
DDR_DQ35
1
DDR_DQ34
2

4P2R_56
4
3

RP114
4
3

4P2R_56
DDR_DQ44
1
DDR_DQ43
2

DDR_DQ22
DDR_DQ23

RP101
1
2

4P2R_56
4
3

RP103
4
3

4P2R_56
DDR_DQ17
1
DDR_DQ16
2

DDR_DQ42
DDR_DQ41

RP88
1
2

4P2R_56
4
3

4
3

DDR_DQ29
DDR_DQ27

RP100
1
2

4P2R_56
4
3

RP102
4
3

4P2R_56
DDR_DQS2
1
DDR_DQ21
2

DDR_DQ40
DDR_DQ47

RP87
1
2

4P2R_56
4
3

RP86
4
3

4P2R_56
DDR_DQ46
1
DDR_DQ52
2

DDR_DQ28
DDR_DQ30

RP99
1
2

4P2R_56
4
3

RP128
4
3

4P2R_56
DDR_DQ18
1
DDR_DQ31
2

RP85
DDR_DQ55
1
DDR_DQ48
2

4P2R_56
4
3

RP112
4
3

4P2R_56
DDR_DQ49
1
DDR_DQS6
2

DDR_F_CB4
DDR_F_CB6

RP98
1
2

4P2R_56
4
3

RP127
4
3

4P2R_56
DDR_DQ24
1
DDR_DQS3
2

DDR_DQ50
DDR_DQ51

RP84
1
2

4P2R_56
4
3

RP111
4
3

4P2R_56
DDR_DQ53
1
DDR_DQ54
2

DDR_F_CB1
DDR_F_CB3

RP97
1
2

4P2R_56
4
3

RP126
4
3

4P2R_56
DDR_DQ25
1
DDR_DQ26
2

DDR_DQ57
DDR_DQ60

RP83
1
2

4P2R_56
4
3

RP110
4
3

4P2R_56
DDR_DQ56
1
DDR_DQ61
2

DDR_CKE0
DDR_CKE1

RP123
1
2

4P2R_56
4
3

RP125
4
3

4P2R_56
DDR_F_CB5
1
DDR_F_CB7
2

DDR_DQ62
DDR_DQ58

RP82
1
2

4P2R_56
4
3

RP109
4
3

4P2R_56
DDR_DQS7
1
DDR_DQ59
2

DDR_CKE2
DDR_CKE3

RP96
1
2

4P2R_56
4
3

RP124
4
3

4P2R_56
DDR_DQS8
1
DDR_F_CB0
2

DDR_DQ63

RP108
1
2

4P2R_56
4
3

DDR_SMA11
DDR_SMA8

RP122
1
2

4P2R_56
4
3

RP95
4
3

4P2R_56
DDR_SMA12
1
DDR_F_CB2
2

DDR_SMA6
DDR_SMA4

RP121
1
2

4P2R_56
4
3

RP94
4
3

4P2R_56
DDR_SMA7
1
DDR_SMA9
2

DDR_SMA2
DDR_SMA0

RP120
1
2

4P2R_56
4
3

RP93
4
3

4P2R_56
DDR_SMA3
1
DDR_SMA5
2

1
R444
1
R159

2
56
2
56

8,10 DDR_SCAS#

DDR_SCAS#
DDR_SCS#3

RP118
1
2

RP113

DDR_SWE# 8,10
DDR_SBS0 8,10

DDR_DQ13
DDR_DQS1
DDR_DQ11
DDR_DQ10

8
8

DDR_CLK4
DDR_CLK4#

DDR_DQ17
DDR_DQ16

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_DQS2
DDR_DQ21
DDR_DQ18
DDR_DQ31
DDR_DQ24
DDR_DQS3

4P2R_56
1
2

DDR_DQ2
DDR_DQ12

DDR_DQS5
DDR_DQ45

DDR_DQ25
DDR_DQ26
DDR_F_CB5
DDR_F_CB7
DDR_DQS8
DDR_F_CB0
DDR_F_CB2

8
8

DDR_CLK3
DDR_CLK3#

DDR_CKE3

DDR_CKE3
DDR_SMA12
DDR_SMA9
DDR_SMA7
DDR_SMA5
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SBS0
DDR_SWE#

DDR_SCS#2
DDR_DQ37
DDR_DQ39
DDR_DQS4
DDR_DQ33
DDR_DQ38
DDR_DQ44

DDR_DQ43
DDR_DQS5
DDR_DQ45
DDR_DQ46

DDR_SMA1

DDR_DQ52
DDR_DQ49

DDR_SMA10
DDR_DQS6
DDR_DQ53
DDR_DQ54
DDR_DQ56
DDR_DQ61
DDR_DQS7
DDR_DQ59
DDR_DQ63

*
For EC Tools

10,13 DIMM_SMDATA
10,13 DIMM_SMCLK

EMI Clip PAD for Memory Door

PAD4

PAD5
1

+5VALW
JP22

EC_URXD 32
EC_UTXD 32
EN_WOL# 27,32

+3VS

PAD6
1

PAD-2.5X3

PAD-2.5X3

PAD7

PAD8

PAD9

1
PAD-2.5X3

1
PAD-2.5X3

DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID

VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS#
CAS#
S1#
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

DDR_DQ4
DDR_DQ0

C518
.1UF

DDR_DQ3
1

DDR_DQ7
DDR_DQ15
DDR_DQ8
DDR_DQ9
DDR_DQ14

DDR_DQ19
DDR_DQ20

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_DQ22
DDR_DQ23
DDR_DQ29
DDR_DQ27
DDR_DQ28
DDR_DQ30
DDR_F_CB4
DDR_F_CB6
2

DDR_F_CB1
DDR_F_CB3

DDR_CKE2

DDR_CKE2 8

DDR_SMA11
DDR_SMA8
DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0
DDR_SBS1
DDR_SRAS#
DDR_SCAS#
DDR_SCS#3

DDR_SCS#3 8

DDR_DQ36
DDR_DQ32
DDR_DQ35
DDR_DQ34
DDR_DQ42

DDR_DQ41
DDR_DQ40
DDR_DQ47
DDR_CLK5# 8
DDR_CLK5 8
DDR_DQ55
DDR_DQ48
DDR_DQ50
DDR_DQ51
DDR_DQ57
DDR_DQ60
DDR_DQ62
DDR_DQ58
+3VS

PAD-2.5X3

VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS

DDR_SMA[0..12]

JP27

8,10 DDR_SMA[0..12]

EC_URXD
EC_UTXD
EC_USCLK

+2.5V

DDR_DQ[0..63]

10 DDR_DQ[0..63]

1
2
3
4
5
6

DDR-SODIMM_200_NORMAL

DIMM1
1

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

PAD-2.5X3
Size

TRANSFERRED FROM THE CUSTODY OF THE COMPE

Document Number

@ FCI SFW06R-2STE1

Rev
2A

401207
Date:
A

, 18, 2004

Sheet
E

52

of

83

Layout note :
Distribute as close as possible
to DDR-SODIMM.

1
2

1
C154
.1UF_0402_X5R

***

C161
@.1UF_0402_X5R

C112
+
150UF_D2_6.3V

C159
150UF_D2_6.3V

+
2

C160
@.1UF_0402_X5R

***

1
C162
.1UF_0402_X5R

1
C152
.1UF_0402_X5R

1
C157
.1UF_0402_X5R

1
C158
.1UF_0402_X5R

1
C135
.1UF_0402_X5R

C133
.1UF_0402_X5R

+2.5V

+2.5V

C163
.1UF_0402_X5R

C156
.1UF_0402_X5R

1
C132
.1UF_0402_X5R

C155
.1UF_0402_X5R

1
C151
.1UF_0402_X5R

C134
.1UF_0402_X5R

1
C150
.1UF_0402_X5R

+2.5V

Layout note :
Place one cap close to every 2 pull up resistors termination to
+1.25V

1
C546
.1UF_0402_X5R

1
C545
.1UF_0402_X5R

1
C544
.1UF_0402_X5R

1
C543
.1UF_0402_X5R

1
C542
.1UF_0402_X5R

1
C541
.1UF_0402_X5R

1
C540
.1UF_0402_X5R

1
C539
.1UF_0402_X5R

1
C538
.1UF_0402_X5R

+1.25VS

C547
.1UF_0402_X5R

1
C556
.1UF_0402_X5R

1
C555
.1UF_0402_X5R

1
C554
.1UF_0402_X5R

1
C553
.1UF_0402_X5R

1
C552
.1UF_0402_X5R

1
C551
.1UF_0402_X5R

1
C550
.1UF_0402_X5R

1
C549
.1UF_0402_X5R

1
C548
.1UF_0402_X5R

+1.25VS

C557
.1UF_0402_X5R

1
C566
.1UF_0402_X5R

1
C565
.1UF_0402_X5R

1
C564
.1UF_0402_X5R

1
C563
.1UF_0402_X5R

1
C562
.1UF_0402_X5R

1
C561
.1UF_0402_X5R

1
C560
.1UF_0402_X5R

1
C559
.1UF_0402_X5R

1
C558
.1UF_0402_X5R

+1.25VS

C567
.1UF_0402_X5R
3

1
C576
.1UF_0402_X5R

1
C575
.1UF_0402_X5R

1
C574
.1UF_0402_X5R

1
C573
.1UF_0402_X5R

1
C572
.1UF_0402_X5R

1
C571
.1UF_0402_X5R

1
C570
.1UF_0402_X5R

1
C569
.1UF_0402_X5R

1
C568
.1UF_0402_X5R

+1.25VS

C577
.1UF_0402_X5R

1
C586
.1UF_0402_X5R

1
C585
.1UF_0402_X5R

1
C584
.1UF_0402_X5R

1
C583
.1UF_0402_X5R

1
C582
.1UF_0402_X5R

1
C581
.1UF_0402_X5R

1
C580
.1UF_0402_X5R

1
C579
.1UF_0402_X5R

1
C578
.1UF_0402_X5R

+1.25VS

C595
.1UF_0402_X5R

+1.25VS

1
C592
.1UF_0402_X5R

1
C593
.1UF_0402_X5R

C594
.1UF_0402_X5R

C591
.1UF_0402_X5R

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331TRANSFERRED

Size

Document Number

Rev
2A

401207
Date:
A

, 18, 2004

Sheet
E

FROM THE CUSTODY OF THE COMPE

53

of

83

1
R148
1
R146
1
R108

16,32 PM_SLP_S1#
16,32 PM_SLP_S3#
16 PM_STPPCI#
16,42 PM_STPCPU#

1
R135
1
R130

+3VS
Ir ef

5.00mA

2.32mA

2
@0
2
0

DIMM_SMDATA
DIMM_SMCLK

25
34
53

VTT_PWRGD#

16

CLK_ICH14

24

CLK_SIO14

1
R144

2
475_1%
CLK_ICH48M

2
33

CLK_ICH14M

1
R101
1
R100

CLK_SIO14M

43

MULT0

2
33
2
33

29
30

SDATA
SCLK

33
35

3V66_0/DRCG
3V66_1/VCH_CLK

42

IREF

39

48MHZ_USB

38

48MHZ_DOT

56

1
2

2
1
R129

2
33

CLK_HCLK 4

1
R128

R1341

2 49.9_1%

1
R110

49.9_1%

CPU_CLKC2

44

CLK_BCLK#

CPUCLKT1

49

CLK_HT

1
R133
1
R113

2
33
2
33

CLK_HCLK# 4
CLK_GHT 7
2

49.9_1%

Place resistor near R653, R655

;Trace<=400mils
CPUCLKC1

48

CPUCLKT0

52

CPUCLKC0

51

66MHZ_IN/3V66_5

24

66MHZ_OUT2/3V66_4
66MHZ_OUT1/3V66_3
66MHZ_OUT0/3V66_2

23
22
21

PCICLK_F2
PCICLK_F1
PCICLK_F0

REF
GND_REF
GND_PCI
GND_PCI
GND_3V66
GND_3V66
GND_48MHZ
GND_IREF
GND_CPU

CLK_ICH48

CLK_BCLK

Place resistor near R645,R653

;Trace<=400mils

PWR_DWN#
PCI_STOP#
CPU_STOP#

28

Please closely pin42

16

45

SEL2
SEL1
SEL0

2
10K
2
@ 10K

1
R140

XTAL_OUT

C124
10UF_10V_1206

CLK66MCH
CLK66AGP
CLKICHHUB
CLKPCI_F2

R137
R138
R131
R127
R118
R117
R114

18
17
16
13
12
11
10

1
R116

1
R145
1
R139

2
33
2
33

1
R112

1
1
1
1
1
1
1

2
2
2
2
2
2
2

2 49.9_1%

2
33

1
R142

CLK_GHT# 7

CLK_AGP_MCH 7
CLK_AGP 14
CLK_ICHHUB 16

2
33

2
33

CLK_ICHPCI 16

33
33
33
33
33
33
33

CLK_LPC_SIO 24
CLK_PCI_LAN 20
CLK_PCI_CB 22
CLK_PCI_1394 21
CLK_PCI_SD/SM 28
CLK_LPC_EC 32
CLK_MINIPCI 27

Place caps. near

CK_Titan (U10)

4
9
15
20
31
36
41
47

W320-04

PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0

7
6
5

R1151

CLK_HT#

C115
@10PF

C119
@10PF

40
55
54

32,35 CK408_PWRGD#

MULT0

CPUCLKT2

C127
.1UF

R107
@1K

GND_CORE

27

1
10PF

R106
1K
2

R143
1K

@0

26

C118
10UF_10V_1206

2
R99

2
C101

BSEL0
1

VDD_CORE

R103
1K

H_BSEL2
H_BSEL0
2

XTAL_IN

Y1
14.318MHZ

R102
@1K

1
10PF

C123
.1UF

+3VS
L9
BLM21A601SPT
1
2

caps are internal

to CK_TITAN

+3VS

133Mhz Host CLK

2
C97

200Mhz Host CLK

+3VS_CLKVDD

+3VS

+3VS

Place Crystal within 500 mils of CK_Titan

1
L8

BLM21A601SPT

VDD_REF
VDD_PCI
VDD_PCI
VDD_3V66
VDD_3V66
VDD_48MHZ
VDD_CPU
VDD_CPU

U8

+3VS_VDD48M

100Mhz Host CLK

C108
.1UF

66Mhz Host CLK

C99
.1UF

+3VS_VDD48M

1
8
14
19
32
37
46
50

H_BSEL0
H_BSEL1

C98
.1UF

+3V_CLK = 40mils

Function

5
5

C125
.1UF

C110
.1UF

C100
.1UF

C102
.1UF

C104
22UF_10V_1206

+3VS_VDD48M = 10mils

1
2

+3V_CLK

H_BSEL0

+3V_CLK

L7
BLM21A601SPT
1
2

H_BSEL1

+3V_CLK
L6
BLM21A601SPT
1
2

+3VS

C122
@10PF

or ICS 9508-05

2
G

+5VS

DIMM_SMDATA 10,11

16,18 SMB_DATA
4

Q6

2N7002

2
G

+5VS

COMPAL ELECTRONICS, INC

3

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

DIMM_SMCLK 10,11

16,18 SMB_CLK

TRANSFERRED
SCHEMATIC, M/B LA-1331

Size
Q7

Document Number

2N7002
B

Rev
2A

401207
, 18, 2004

Date:
A

FROM THE CUSTODY OF THE COMPE

Sheet

54
H

of

83

32

KSI[0..7]

32

KSO[0..15]

KSI[0..7]
KS0[0..15]

AGP CONN.
7

JP8

AGP_SBA0
AGP_SBA2

AGP_SBSTB

13

CLK_AGP

AGP_SBA4
AGP_SBA6
CLK_AGP
AGP_AD31
AGP_AD29
AGP_AD27
AGP_AD25

AGP_ADSTB1
AGP_AD23
AGP_AD21
AGP_AD19
AGP_AD17
AGP_C/BE#2
AGP_IRDY#
AGP_DEVSEL#

7
AGP_IRDY#
7 AGP_DEVSEL#

AGP_C/BE#1
AGP_AD14
AGP_AD12
AGP_AD10
AGP_AD8
7
16

AGP_ADSTB0
C3_STAT#

AGP_AD7
AGP_AD5
AGP_AD3
AGP_AD1

+AGP_NBREF

ENBKL
ENVEE

7 AGP_C/BE#[0..3]

JP8 PIN
25,26,27,28

PCI_RST#

Int. Keyboard CONN.

JP11

ATL02/ACL00

+5VALW

NC

SQ17

NV11

+1.5V
X

KSI0
KSI2
KSI4
KSI6
KSO0
KSO2
KSO4
KSO6
KSO8
KSO10
KSO12
KSO14

PIRQA#
16,18,21,22
PCIRST# 7,16,19,20,21,22,23,24,27,28,34
AGP_GNT# 7
AGP_PIPE# 7
AGP_WBF# 7

AGP_SBA1
AGP_SBA3
AGP_SBA5
AGP_SBA7

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

+3V

VGA/B

+1.5VS

AGP_ST1

ACL10

AGP_C/BE#[0..3]

AGP_SBSTB# 7
32

NC

+3VS
+5VS
TP_DATA

AGP_C/BE#3
AGP_AD30
AGP_AD28
AGP_AD26
AGP_AD24

+12V
+3V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

KSI1
KSI3
KSI5
KSI7
KSO1
KSO3
KSO5
KSO7
KSO9
KSO11
KSO13
KSO15
+5V
TP_CLK

32
C

HEADER 2X20

AGP_ADSTB1# 7
+3.3VAUX

AGP_AD22
AGP_AD20
AGP_AD18
AGP_AD16
AGP_FRAME#

AGP_FRAME# 7
AGP_TRDY# 7
AGP_STOP# 7
AGP_PAR 7

+3VS_MDC

+5VS_MDC

AGP_RBF#

AGP_AD[0..31]
AGP_SBA[0..7]

7 AGP_SBA[0..7]

C116

C129

C117
1UF_25V_0805

1UF_25V_0805

AGP_ST0
AGP_ST2

INVT_PWM

TV_CRMA 15
TV_LUMA 15
TV_COMPS 15
TV_SYNC 15
PID0
24
PID1
24
PID2
24
PID3
24
INVT_PWM 32
+5VALW
ENBKL
32
ENVEE
32
+5VALW

16,24,34 SUS_STAT#
16 AGP_BUSY#
7
AGP_REQ#

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120

+1.5VS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120

1UF_25V_0805

AGP_AD15
AGP_AD13
AGP_AD11
AGP_AD9
AGP_ADSTB0# 7
AGP_C/BE#0
AGP_AD6
AGP_AD4
AGP_AD2
AGP_AD0

MDC_SPK

C469
1UF_25V_0805
1
2

MD_SPK

30

DAC_BRIG

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119

C472
B

+5VALW
32
DAC_BRIG
20,22,23,27,28 CBRST#
+5VALW

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119

15
CRT_R
15
CRT_G
15
CRT_B
15 CRT_HSYNC1
15 CRT_VSYNC1
15 CRT_DDCDATA
15 CRT_DDCCLK

AGP_ST[0..2]

AGP_ST[0..2]

7 AGP_AD[0..31]

1000PF

+AGP_VGAREF

HEADER 2X60

JP13
30

R94
CLK_AGP 1

C92

2
@33

MD_MIC

2
+3.3VAUX

@15PF

+3VS
16,30 IAC_SDATAO
16,30 IAC_RST#

L40

2 +3VS_MDC
CHB1608B121

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

MONO_OUT/PC_BEEP AUDIO_PWDN
GND
MONO_PHONE
AUXA_RIGHT
RESERVED
AUXA_LEFT
GND
CD_GND
+5V
CD_RIGHT
RESERVED
CD_LEFT
RESERVED
GND
RESERVED
3.3Vaux
RESERVED
GND
RESERVED
3.3Vmain
AC97_SYNC
AC97_SDATA_OUT AC97_SDATA_IN1
AC97_RESET#
AC97_SDATA_IN0
GND
GND
AC97_MSTRCLK
AC97_BITCLK

AMP-108-5424

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

MDC_DN# 33

MDC_SPK
+5VS_MDC1

+5VS

L43 CHB1608B121
1
2

+3VS

R374 10K

*
*

1
R361
1
R360

IAC_SYNC

2
22
2
@22

16,30

IAC_SDATAI1 16

1
R357

2
10K

MDC CONN.
IAC_BITCLK 16,30

COMPAL ELECTRONICS, INC

Title
PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
3

SCHEMATIC, M/B LA-1331

Document Number

Rev
2A

401207
, 18, 2004

Sheet
1

55

of

83

1
R203

+3VS

1
R196

2
@0

+5VS

R203 For CH7011/SQ17

**
2

D8
DAN217

D9
DAN217

D10
DAN217

L20
14

1
C222
14

2
22PF

L25
1
2
FBM-11-160808-121

TV_LUMA

1
C221

2
22PF

JP2

L24

1
2
FBM-11-160808-121
14

TV_CRMA

14

TV_COMPS

TV_OUT CONNECTOR

R196 For CH7007

**

1
2
@FBM-11-160808-121

TV_SYNC

1
2
3
4
5
6
7

1
2
C223
22PF
L26
1
2
FBM-11-160808-121

C192

C191

330PF

330PF

C202

C227

C226

C201

330PF

270PF

270PF

270PF

@470PF

CRT CONNECTOR
*

JP3
CRT-15P

22PF

100K

C3
22PF

R5
2.2K

1
Q1
2N7002

5VDDCCL

1
2

C6
22PF

C5
220PF

Q11
2N7002

R8
R6
2.2K

100K

CRT_DDCDATA 14

L1
1
2
CHB1608B121

+CRT_VCC

+12VS

5VDDCDA

2
R185

Q12
2N7002

2
+12VS
4

22PF

C183

L2
1
2
CHB1608B121

14 CRT_VSYNC1

22PF

C184

10PF

C185

14 CRT_HSYNC1

75

10PF

C198

1
2

75

C196 R184

10PF

R182
75

C197 R183

+CRT_VCC

L15
1
2
FCM2012C80_0805

CRT_B

14

CRT_G

14

L13
1
2
FCM2012C80_0805
L14
1
2
FCM2012C80_0805

CRT_R

14

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

C7
.1UF
3

FUSE_1A

RB491D

+CRT_VCC

@DAN217

@DAN217

@DAN217

*
2

+R_CRT_VCC
F1
1
1

D7

+5VS

D4

D5

D6

+3VS

**

C228

R201
75

75

75

R200

R202
2

S CONN._SUYIN

C182
220PF

CRT_DDCCLK 14

Q3
2N7002

COMPAL ELECTRONICS, INC

Title

SCHEMATIC, M/B LA-1331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE
Size
Document Number
Custom 401207
Date:
A

, 18, 2004

Sheet
E

56

TRANSFERRED FROM THE CUSTODY OF

Rev
2A
of

83

C306
2

13
13

+1.8VS

HUB Interface VSwing Voltage

J1
JOPEN

GATEA20 32
H_A20M# 5

1
R43

2
1

PCIRST#

7,14,19,20,21,22,23,24,27,28,34

C637
@10PF

+CPU_CORE

R217 (for use if CPU unable

@10K to support DPSLP#)
1
R298

H_FERR#

2
0

H_DPSLP# 5

H_IGNNE# 5
H_INIT# 5
H_INTR
5
H_NMI
5
H_PWRGD 5
RC#
32
H_SLP#
5
H_SMI#
5
H_STPCLK# 5

R327
300
2

R326
470
2

HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10

+3VS

2
Q25
3904

2
Q24
3904

HUB_PD[0..10]

HUB_PD[0..10] 7
5

+VS_HUBREF

1
R325

H_F_FERR#

2
470

+VS_HUBVSWING

CLK_ICHHUB 13
HUB_PSTRB 7
HUB_PSTRB# 7

CLK_ICHHUB
1
R315

2
100K

C29

.1UF

2
36.5_1%

R309
10

1
C394
.01UF

C393
.01UF

C395
5PF

Close to ICH3-M.

IRDY#
18,20,21,22,27,28
PAR
18,20,21,22,27,28
PERR#
18,20,21,22,27
PLOCK# 18,22
ICH_WAKE_UP# 32
1
2
R467
SERR#
18,20,22,27
33
STOP#
18,20,21,22,27,28
TRDY#
18,20,21,22,27,28

C405
@10PF

L22
M21
M23
N20
P21
R22
R20
T23
M19
P19
N19

C27
@15PF

HubLink
Interface

PM_LANPWROK

R312
@33

HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10

CLK_ICHHUB

+3VS

CLK_ICHAPIC

1
Y22
V23
AB22
J22
AA21
AB23
AA23
Y21
W23
U22
W21
Y23
U23

R63
@0

R253
1K

HUB Reference Voltage

R_K
R88
301_1%

Place R_K and R_L

Closely ICH3
2

1. Place R_G and R_H in middle of Bus.

1 2

CPU_A20GATE
CPU_A20M#
CPU_DPSLP#
CPU_FERR#
CPU_IGNNE#
CPU_INIT#
CPU
CPU_INTR
Interface
CPU_NMI
CPU_PWRGOOD
CPU_RCIN#
CPU_SLP#
CPU_SMI#
STPCLK#

GNTA#

1
C301
1UF_10V_0603

+3VS
+3VALW

2
SM_INTRUDER# 18
SMLINK0 18
SMLINK1 18
SMB_CLK 13,18
SMB_DATA 13,18
SMB_ALERT# 18

HUB_ICH_RCOMP

2
15K

12PF

R85
301_1%

R_G

PIRQA#
PIRQB#
PIRQC#
PIRQD#
ICH_PID0
ICH_PID1
ICH_PID2
ICH_PID3

Y6
AC3
AB2
AC4
AB5
AC5

CLK_ICHPCI 13
DEVSEL# 18,20,21,22,27,28
FRAME# 18,20,21,22,27,28
PCI_REQA# 18
PCI_REQB# 18

1
R258

C327

+1.8VS

R_L

+VS_HUBREF

COMPAL ELECTRONICS, INC

R91
301_1%

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

R_H

C79
.1UF

+VS_HUBVSWING
R86
301_1%
2

IDE_PATADET
ECSMI#
ECSCI#
LID#
GPIO_25
PIDEPWR

J19
J20
J21
B1
C1
B2
A2
A6
B5
C5
A5
AB14
W19
H22
SM_INTRUDER#
SMLINK0
System
SMLINK1
Managment SMB_CLK
Interface SMB_DATA
SMB_ALERT#/GPIO11

1
2

12PF

32.768KHZ

CLK_ICH14
CLK_ICH48

CLK_ICH14
CLK_ICH48

+RTCVCC
C336

T5
M3
F1
C4
D4
B6
B3
N3
G5
M2
M1
W1
Y1
L5
H2
H1

R264
2.4M

CLK_ICHPCI

PCI_CLK
PCI_DEVSEL#
PCI_FRAME#
PCI_GPIO0/REQA#
PCI_GPIO1/REQB#/REQ5#
PCI_GPIO16/GNTA#
PCI_GPIO17/GNTB#/GNT5#
PCI_IRDY#
PCI_PAR
PCI_PERR#
PCI_LOCK#
PCI
PCI_PME#
Interface
PCI_RST#
PCI_SERR#
STOP#
PCI_TRDY#

R271 10M_0603
X2

EEPROM
Interface

@10

R272 10M

RTC_X1
RTC_X2

LAN
Interface

22M

R261

V2
W2
Y4
Y2
W3
W4
Y3

V1
U3
T3
U2
T2
U4
U1

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
RTC_VBIAS

.047UF_0603
1
2

A1
A13
A16
A17
A20
A23
B8
B10
B13
B14
B15
B18
B19
B20
B22
C3
C6
F19
C14
C15
C16
C17
C18
C19
C20
C21
C22
D9
D13
D16
D17
D20
D21
D22
E5

ICH3-M

1K

GPIO_7
GPIO_8
GPIO_12
GPIO_13
GPIO_25
GPIO_27
GPIO_28

2 0
2 33

IAC_BITCLK 2
IAC_RST#
IAC_SDATAI0
IAC_SDATAI1
R55
1
R54
1

Clocks

+RTCVCC

R259

CLK_ICHPCI

H_FERR#

VSS

@10K
2
2
@10K

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4

1
1 2
2
1 2
2
3

R49
GNTA#
1
GPIO_25 1
R39

R308
0

D3
F4
A3
R4
E4

20,21,22,27,28
20,21,22,27,28
20,21,22,27,28
20,21,22,27,28

ICH3-M (1/2)

ICH_PID0
ICH_PID1
ICH_PID2
ICH_PID3

8
7
6
5

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4

@15PF

PCI
Interface

R306
1K

18,21
18,27
18,22
18,20
18,27

C399

+3VS

R50

HUB_VSWING
HUB_VREF
HUB_RCOMP
HUB_PSTRB#
HUB_PSTRB
HUB_PAR
HUB_CLK

PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4

@10

Interrupt
Interface

1
2
3
4

Place closely to ICH3

L19
L20
K19
P23
N22
R19
T19

A4
E3
D2
D5
B4

R307

unMUX
GPIO

EEP_SHCLK
EEP_DOUT
EEP_DIN
EEP_CS

GNT#0
GNT#1
GNT#2
GNT#3
GNT#4

INT_IRQ14 18,19
INT_IRQ15 18,29
INT_SERIRQ 18,22,24,32

INT_APICCLK
INT_APICD0
INT_APICD1
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
INT_PIRQE#/GPIO2
INT_PIRQF#/GPIO3
INT_PIRQG#/GPIO4
INT_PIRQH#/GPIO5
INT_IRQ14
INT_IRQ15
INT_SERIRQ

18,21
18,27
18,22
18,20
18,27

CLK_ICH48

LPC
Interface

D10
E8
D8
E9

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

@15PF

AC'97
Interface

Geyserville

RP14

14,18,21,22
18,20,22
18,27,28
18,27,28

8P4R_4.7K

R305
1K

LAN_RSTSYNC
LAN_JCLK
LAN_TXD2
LAN_TXD1
LAN_TXD0
LAN_RXD2
LAN_RXD1
LAN_RXD0

K2
K5
N1
R2

C406

Power Management

PIRQA#
PIRQB#
PIRQC#
PIRQD#

CLK_ICHAPIC
H_PICD0
H_PICD1

SIDEPWR 19

CLK_ICHAPIC
H_PICD0
H_PICD1

D7
C9
A10
C10
B9
A9
A8
C8

C/BE#0
C/BE#1
C/BE#2
C/BE#3

@10

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ#0
LPC_DRQ#1
LPC_FRAME#

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

R304

IAC_SDATAO
IAC _SYNC

@ 10PF

J2
K1
J4
K3
H5
K4
H3
L1
L2
G2
L4
H4
M4
J3
M5
J1
F5
N2
G4
P2
G1
P1
F2
P3
F3
R1
E2
N4
D1
P4
E1
P5

CLK_14
CLK_48
CLK_RTEST#
CLK_RTCX1
CLK_RTCX2
CLK_VBIAS

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CLK_ICH14

PIRQA#
PIRQB#
PIRQC#
PIRQD#

Place closely to ICH3

B7
D11
B11
C11
C7
A7

U29A

20,21,22,27,28 AD[0..31]

AC_BITCLK
AC_RST#
AC_SDATAIN0
AC_SDATAIN1
AC_SDATAOUT
AC_SYNC

2
@ 10K

U20
Y20
V19

1
R278

PM_LANPWROK

AGP_BUSY#

PM_GMUXSEL/GPIO23
PM_CPUPREF#/GPIO22
PM_VGATE/VRMPWRGD

+3VS

C44

R58
@ 33

2
R26

PM_SUSCLK

14

V4
Y5
AB3
V5
AC2
AB21
AB1
AA6
AA1
AA7
W20
AA5
AA2
V21
U21
AA4
AB4
U5

14,30 IAC_RST#
30 IAC_SDATAI0
14 IAC_SDATAI1
14,30 IAC_SDATAO
14,30 IAC_SYNC
14,30 IAC_BITCLK

PM_AGPBUSY#/GPIO6
PM_AUXPWROK
PM_BATLOW#
PM_C3_STAT#/GPIO21
PM_CLKRUN#/GPIO24
PM_DPRSLPVR
PM_PWRBTN#
PM_PWROK
PM_RI#
PM_RSMRST#
PM_SLP_S1#/GPIO19
PM_SLP_S3#
PM_SLP_S5#
PM_STPCPU#/GPIO20
PM_STPPCI#/GPIO18
PM_SUS_CLK
PM_SUS_STAT#
PM_THRM#

22,23,28 RTCCLK

LPC_AD0 24,32
LPC_AD1 24,32
LPC_AD2 24,32
LPC_AD3 24,32
LPC_DRQ#0 18,32
LPC_DRQ#1 18,24
LPC_FRAME# 24,32

J23
F20
RTC_RST# Y7
RTC_X1 AC7
RTC_X2 AC6
RTC_VBIAS
AB7

35
ICH_VGATE
5 PM_CPUPERF#
42 PM_GMUXSEL
32
ATF_INT#
14,24,34 SUS_STAT#
13 PM_STPPCI#
2
1 PM_SUSCLK
13,42 PM_STPCPU#
R44
0
32 PM_SLP_S5#
13,32 PM_SLP_S3#
IAC_RST#
13,32 PM_SLP_S1#
IAC_SDATAI0
35 PM_RSMRST#
IAC_SDATAI1
18
ICH_RI#
IAC_SDATAO
35 PM_PWROK
IAC _SYNC
18
PBTN#
IAC_BITCLK
42 PM_DPRSLPVR
18,22,24,27,28,32 PM_CLKRUN#
2
1
14
C3_STAT#
R351
10K
32 PM_BATLOW#

ECSMI#
ECSCI#
LID#
IDE_PATADET

18
ECSMI#
18
ECSCI#
18
LID#
19 IDE_PATADET

Size
Document Number
Custom
Date:

TRANSFERRED FROM THE CUSTODY OF THE COMPE

Rev
2A

401207

, 18, 2004

Sheet
D

57

of

83

+5VALW

R284
0

USB_D_PN0
USB_D_PN1
USB_D_PN3

*
+3V

RP20
8P4R_10K

1
2
3
4

8
7
6
5

USB_OC#2
USB_OC#4
USB_OC#5

26
26

USB_OC#0
USB_OC#1

26

USB_OC#3

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5

19 ICH_IDE_PRST#
19 ICH_IDE_SRST#

1
R90
18
18
33

2
@0

FWH_WP#
FWH_TBL#
EC_FLASH#

ICH_ACIN

2
VCC5REFSUS

+1.8VS

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5

H20
G22
F21
G19
E22
E21
H21
G23
F23
G21
D23
E23

USB_LEDA#0/GPIO32
USB_LEDA#1/GPIO33
USB_LEDA#2/GPIO34
USB_LEDA#3/GPIO35
USB_LEDA#4/GPIO36
USB_LEDA#5/GPIO37
USB_LEDG#0/GPIO38
USB_LEDG#1/GPIO39
USB_LEDG#2/GPIO40
USB_LEDG#3/GPIO41
USB_LEDG#4/GPIO42
USB_LEDG#5/GPIO43

B21

USB_RBIAS

H23

SPKR

U19

VCCA

F17
F18
K14

VCCPSUS3/VCCPUSB0
VCCPSUS4/VCCPUSB1
VCCPSUS5/VCCPUSB2

E10
V8
V9

VCCPSUS0
VCCPSUS1
VCCPSUS2

E11
K6
K18
P6
P18
V10
V14

J18
M14
R18
T18
VCCPHL0
VCCPHL1
VCCPHL2
VCCPHL3

P12
V15
V16
V17
V18
VCCPIDE0
VCCPIDE1
VCCPIDE2
VCCPIDE3
VCCPIDE4

G18
H18
VCCP0
VCCP1

F6
G6
H6
J6
M10
R6
T6
U6
VCCPPCI0
VCCPPCI1
VCCPPCI2
VCCPPCI3
VCCPPCI4
VCCPPCI5
VCCPPCI6
VCCPPCI7

A21
A22
VSS102
VSS103

N/C0
N/C1
N/C2
N/C3
N/C4

C23

P14
U18
V22

C13
W5

E6
W8

AB6
VCC_RTC

VCCCORE0
VCCCORE1
VCCCORE2
VCCCORE3
VCCCORE4
VCCCORE5
VCCCORE6

E12
D12
C12
B12
A12
A11

VCCUSBBG/VCC_SUS8

USB_PP0
USB_PP1
USB_PP2
USB_PP3
USB_PP4
USB_PP5
USB_PN#0
USB_PN#1
USB_PN#2
USB_PN#3
USB_PN#4
USB_PN#5

VCCPCPU0
VCCPCPU1
VCCPCPU2

D19
A19
E17
B17
D15
A15
D18
A18
E16
B16
D14
A14

F9
F10

+3VS
+1.8VA_ICH

Power

USB
Interface

ICH3-M (2/2)

IDE
Interface

USB_RBIAS

R310
0_0805

VCCUSBPLL/VCC_SUS9

USB_D_PP3

+1.8VALW

+CPU_CORE

VCCPAUX0/VCCLAN3_3
VCCPAUX1/VCCLAN3_3

C361
.1UF

R279
0_0805

VCC5REFSUS1
VCC5REFSUS2

USB_D_PP0
USB_D_PP1

VCC5REF1
VCC5REF2

U29B

USB_D_PP3
USB_D_PN3

F7
F8
K10

USB_PP3
USB_PN3

VCC_AUX0/VCCLAN1_8
VCC_AUX1/VCCLAN1_8
VCC_AUX2/VCCLAN1_8

26
26

+3VS

+RTCVCC

0_0805

USB_D_PP1
USB_D_PN1

F15
F16

USB_PP1
USB_PN1

VCC_USB0/VCC_SUS6
VCC_USB1/VCC_SUS7

26
26

USB_D_PP0
USB_D_PN0

E13
F14
K12
P10
V6
V7

USB_PP0
USB_PN0

CHB2012U170

VCC_SUS0
VCC_SUS1
VCC_SUS2
VCC_SUS3
VCC_SUS4
VCC_SUS5

26
26

L37
1

*
1
R294

C330
1UF_10V_0603

+V1.8_ICHLAN

+1.8VS

1
C43
.1UF

+V5S_ICHREF

B23

+V5S_ICHREF

D27
1SS355

+1.8VALW

**

R59
1K

DEL:C73, C87, C371.

E7
T21
D6
T1
C2

+3VS

+5VS

31

R293
18.2_1%

ICH_SPKR

ICH_SPKR
+1.8VS

+3VALW

Disable Timeout Feature

1
R313

0_0805

+V3A_ICH

2 ICH_SPKR
@1K

Power

VSS

AC15
AB15
AC21
AC22

IDE_PDCS1#
IDE_PDCS3#
IDE_SDCS1#
IDE_SDCS3#

IDE_PDA0
IDE_PDA1
IDE_PDA2
IDE_SDA0
IDE_SDA1
IDE_SDA2

AA14
AC14
AA15
AC20
AA19
AB20

IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

W12
AB11
AA10
AC10
W11
Y9
AB9
AA9
AC9
Y10
W9
Y11
AB10
AC11
AA11
AC12

IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

IDE_PDA0 19
IDE_PDA1 19
IDE_PDA2 19
IDE_SDA0 29
IDE_SDA1 29
IDE_SDA2 29
IDE_PDD[0..15] 19

IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15

Y17
W17
AC17
AB16
W16
Y14
AA13
W15
W13
Y16
Y15
AC16
AB17
AA17
Y18
AC18

IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15

IDE_PDDACK#
IDE_SDDACK#
IDE_PDDREQ
IDE_SDDREQ
IDE_PDIOR#
IDE_SDIOR#
IDE_PDIOW#
IDE_SDIOW#
IDE_PIORDY
IDE_SIORDY

Y13
Y19
AB12
AB18
AC13
AC19
Y12
AA18
AB13
AB19

19
19
29
29

IDE_SDD[0..15] 29

IDE_PDDACK# 19
IDE_SDDACK# 29
IDE_PDDREQ 19
IDE_SDDREQ 29
IDE_PDIOR# 19
IDE_SDIOR# 29
IDE_PDIOW# 19
IDE_SDIOW# 29
IDE_PIORDY 19
IDE_SIORDY 29

VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101

+3VS

R288

Misc

IDE_PDCS1#
IDE_PDCS3#
IDE_SDCS1#
IDE_SDCS3#

+3VS

ICH3-M

E14
E15
E18
E19
E20
F22
G3
G20
H19
AA22
J5
K11
K13
K20
K21
K22
K23
L3
L10
L11
L12
L13
L14
L21
L23
M11
M12
M13
M20
M22
N5
N10
N11
N12
N13
N14
N21
N23
P11
P13
P20
P22
R3
R5
R21
R23
T4
T20
T22
V3
AC23
V20
W6
W7
W10
W14
W18
W22
Y8
AA3
AA8
AA12
AA16
AA20
AB8
AC1
AC8

R295
100K

Title

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331
TRANSFERRED

37

1
D32

ACIN

2
RB751V

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE
Size
Document Number
Custom

ICH_ACIN

401207

Date:
A

, 18, 2004

Sheet
E

58

of

83

FROM THE CUSTODY OF

Rev
2A

+3VS PULL-UP/BY-PASS

+3VS
+3VS

47PF

C131

C130
.1UF

C84
.1UF

1
C82
.1UF

47PF

C71

1
C70
.1UF

C76
.1UF

1
C75
.1UF

47PF

C63

1
C50
.1UF

C42
.1UF

47PF

C41

1
C40
.1UF

C34
.1UF

47PF

C31

1
C32
.1UF

C35
.1UF

C287
22UF_16V_1206

+
C269
22UF_16V_1206

16,20,22,27
16,20,21,22,27,28
16,20,21,22,27
16,22

SERR#
DEVSEL#
PERR#
PLOCK#

10
9
8
7
6

RP12

1
2
3
4
5

16,20,21,22,27,28 FRAME#
16,20,21,22,27,28 IRDY#
16,20,21,22,27,28 TRDY#
16,20,21,22,27,28 STOP#

+3VS

C60
.1UF

10P8R_8.2K

+3VS

+3VS

+3VS
RP19

16
16
16,21
16,27

RP22

1
2
3
4
5

PCI_REQA#
PCI_REQB#
REQ#0
REQ#1

10
9
8
7
6

1
2
3
4

17
FWH_WP#
17
FWH_TBL#
16,22,24,27,28,32 PM_CLKRUN#

REQ#2
16,22
REQ#3
16,20
REQ#4
16,27
INT_SERIRQ 16,22,24,32

8
7
6
5

+3VS

8P4R_10K

10P8R_8.2K

16,20 GNT#3

RP13

1
2
3
4
5

16,27 GNT#1
16,22 GNT#2
16,27,28 PIRQD#
16,19 INT_IRQ14

1
R41
1
R47
1
R42

16,21 GNT#0
+3VS

+3VS

+3VS

1
R32
1
R40

16,32 LPC_DRQ#0

10
9
8
7
6

INT_IRQ15 16,29
PIRQA#
14,16,21,22
PIRQB#
16,20,22
PIRQC# 16,27,28

16,24 LPC_DRQ#1

2
10K
2
10K

16,27 GNT#4

2
8.2K
2
8.2K
2
8.2K

10P8R_8.2K

+3VALW PULL-UP

R57

16,20,21,22,27,28 PAR

@100

+3V PULL-UP/BY-PASS
+3V

+3V

1
R466

C357
.1UF

C354
.1UF

C355
.1UF

16 SM_INTRUDER#

2
100K

47PF

PBTN#

PBTN#

16

+V5S_ICHREF BY-PASS

+V1.8S_ICHLAN BY-PASS

+1.8VS

+V5S_ICHREF

+V1.8_ICHLAN

C78
.1UF

C61
47PF

C80
.1UF

C81
.1UF

C39

.1UF

.1UF

C47

.1UF

+
C321
1UF_10V_0603

C33
.1UF

C77
.1UF

C36
47PF

C67
.1UF

C241
150UF_6.3V_D2

C54

2
@0

1
R468

ON/OFF

2
0

+1.8SV BY-PASS

32,34

ON/OFF

10K

PBTN_OUT#

C267
22UF_16V_1206

4.7K

1
R256

+3VALW

PBTN_OUT#

32
3

R45

SMB_CLK

C356

4.7K

*
16 SMB_ALERT#

4.7K

1
R263

13,16

4.7K

SMLINK1

16

1
R250
1
R246

SMLINK0

+RTCVCC
R46

13,16 SMB_DATA

16

+RTCVCC PULL-UP

+3VALW

C48
.1UF

RP135
16
16
16
16

+V3A_ICH BY-PASS

+CPU_CORE BY-PASS

8P4R_0

+1.8VA_ICH

+CPU_CORE

.01UF

C53

.01UF

+
C376
1UF_10V_0603

C83
.1UF

C88
.1UF

C389
22UF_16V_1206

C85

.1UF

C51

.1UF

C46

.1UF

C66

.1UF

C74

+V3A_ICH

+1.8VA_ICH BY-PASS

ICH_RI#
ECSMI#
ECSCI#
LID#

C396
.1UF

C397
.1UF

ICH_RI#
ECSMI#
ECSCI#
LID#

5
6
7
8

4
3
2
1

EC_SWI#
EC_SMI#
EC_SCI#
EC_LID_OUT#

32
EC_SWI#
32
EC_SMI#
32
EC_SCI#
32 EC_LID_OUT#

C398
.1UF

Title

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE
Size
Document Number
Custom 401207
Date:
A

, 18, 2004

Sheet
E

59

TRANSFERRED FROM THE CUSTODY OF

Rev
2A
of

83

IDE,CD-ROM Module CONN.

+5VS

.1UF

IDE_PDD[0..15]

ATA33 : populate R31, de-populate R33.

ATA66/100 : populate R33, de-populate R31.
R31

+5VCD

Place component's closely IDE CONN.

Q8
SI3456DV

@10K
JP7

2
100K

29

R152

2
@10K

IDE_PDA2 17
IDE_PDCS3# 17

16

CD_SIOW#
CD_SIORDY
CD_IRQ
CD_SBA1
CD_SBA0
CD_SCS1#
SHDD_LED#

24
24
24
24
24
24
24
24,33

CD _SIORDY
CD_IRQ

SHDD_LED#
EXTCSEL
RDATA#
WP#
TRACK0#
WDATA#
STEP#
MTR0#
DSKCHG#
DRV0#

RDATA#
WP#
TRACK0#
WDATA#
STEP#
MTR0#
DSKCHG#
DRV0#

SIDEPWR

G1

2 IDE_PDD7
@10K
2 CDD7
10K

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

INT_CD_R 30

CD_AGND
CD D8
CD D9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15
CD_DREQ

+3VS
+5VMOD

1
R76

2 IDE_PIORDY
4.7K

1
R406

2 CD_SIORDY
4.7K

1
R69

1
R141

EXTID0
EXTID1
EXTID2
HDSEL#

C114

+5VS

2
.1UF

PCIRST#

7,14,16,20,21,22,23,24,27,28,34 PCIRST#

WGATE#

FDD IR#
3MODE#

WGATE#

24

FDDIR#
3MODE#

24
24

PIDE_RST#

2
7SH08FU

+5VS
INDEX#

INDEX#
+5VMOD

24
C113

5
8
7
6
5

EXTID0
EXTID1
EXTID2

U10

PCIRST#1

4
17 ICH_IDE_SRST#

8P4R_100K

SIDE_RST# 29

2
7SH08FU

DRV0#

1000PF

C148

1
STEP#
MTR0#
RDATA#

+5VS

W=80mils

+5VMOD

5
4
3
2
1

6
7
8
9
10

C149
C147
C145
1UF_25V_0805 .1UF
10UF_16V_1206

Place component's closely CD-ROM CONN.

COMPAL ELECTRONICS, INC

10P8R_1K

1
R154

U9

17 ICH_IDE_PRST#

1
2
3
4

RP1
WDATA#
WGATE#
HDSEL#
FDD IR#

+5VS
CD_DREQ 29
CD_SIOR# 29
CD_DACK# 29
CD_SBA2 29
CD_SCS3# 29
EXTID0
33
EXTID1
33
EXTID2
33
HDSEL# 24

2
1K

RP3
DSKCHG#
INDEX#
WP#
TRACK0#

8P4R_1K

1
R235

SI3456DV: N CHANNEL
VGS: 4.5V, RDS: 65 mOHM
Id(MAX): 5.1A
VGS,+-20V

.1UF

RP2

1
2
3
4

C140
.01UF

2 CD_DREQ
5.6K

+3VALW

8
7
6
5

Q37A
SI1906DL

2 IDE_PDDREQ
@5.6K

HEADER 2X30
+5VS

47K

29
29
29
29
29
29
33

1K

+5VS

JP17
CD_AGND
CD_RSTDRV#
CD D7
CD D6
CD D5
CD D4
CD D3
CD D2
CD D1
CD D0

R398

EXTIDE_EN#
G2

Q37B
SI1906DL

1
R302

33 EXTIDEPWR#

2
470

1
R73

47K

PCSEL

Q36
DTC144EKA

100K

1
R61

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

1
1

1
R407

30
INT_CD_L
30
CD_AGND
29 CD_RSTDRV#

+12VALW

C137
R150
4.7UF_16V_1206
<1st Part Field>
1K

@10K

CDD[0..15]

CDD[0..15]

HDD 44P SUYIN 20225A-44G5-A

2 SHDD_LED#
100K

1
R155

+5VMOD

+
R33

S1

1
R89

+5VS

+5VS

D1

INT_IRQ14

IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

S2

IDE_PIORDY

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

IDE_PDDREQ

17 IDE_PDDREQ
17 IDE_PDIOW#
17 IDE_PDIOR#
17 IDE_PIORDY
17 IDE_PDDACK#
16,18 INT_IRQ14
17
IDE_PDA1
17
IDE_PDA0
17
IDE_PDCS1#
33
PHDD_LED#

IDE_PATADET 16

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

D2

PIDE_RST#
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0

+5VMOD

6
5
2
1

17 IDE_PDD[0..15]

HDD Manual ATA Type Selection:

C89

C93
C379
10UF_16V_1206
1UF_25V_0805

1000PF

C90

+5VS

2 EXTCSEL
470

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

Size
B

Document Number

Date:

, 18, 2004

TRANSFERRED FROM THE CUSTODY OF T

Rev
2A

401207
Sheet

60

of

83

+3VLAN To +2.5VLAN Transfer

+3V

1
L32

2
4.7UH

AVDD-2

1
L31

2
4.7UH

+3VLAN
Q15
VCTRL

AD29
AD28
AD27
AD26
AD25
AD24

+2.5VLAN

16,21,22,27,28 C/BE#3

1
1

C10
0.1UF

AD23
AD17

1
R243

2
100

1
2

AD0
AD1

8
7
6
5

VCC
NC
NC
GND
9346

AD2
AD3

C248

0.1UF

C/BE#0

16,21,22,27,28

C255
4.7UF_10V_1206
RTL8100-B(L)

R179
510_0603
2

PR2-

PR3-

PR3+

RJ45_RX+

PR2+

RJ45_TX-

PR1-

RJ45_TX+

PR1+

C11

2
510_0603

1
2

15

10

Green LED-

Green LED+

SHLD2

14

SHLD1

13

R166
75

C180
1000P_2KV_1206
LAN_GND

LANGND

16

SHLD3

AMP RJ45/RJ11 with LED

R165
75
Q16
DTA114YKA

SHLD4
PR4-

+3V

C181
0.1UF

C187

Termination plane should be copled to chassis ground

R174
75

C13
0.1UF

4.7UF_10V_0805

R175
75

R13
50

2
1

RJ45_TX+
RJ45_TX-

R12
50

C8
0.1UF

Amber LED-

AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8

1
2
1

1
2

LINK10_100#
RJ45_RX+
RJ45_RX-

16
15
14
13
12
11
10
9

Pulse H0013

***

LAN_TD+
LAN_TD-

0.1UF

1 2
2

50

11

PR4+

RJ45_RX-

U18

50

Amber LED+

R15

12

Layout Note
The H0013 pls close to JP5

R14

C272

1000PF

JP5

+3V

RX+
RXCT
NC
NC
CT
TX+
TX-

C262

AD7

Q14
DTA114YKA

RD+
RDCT
NC
NC
CT
TD+
TD-

0.1UF

2
0_1206

AD4
AD5
AD6

R167

1
2
3
4
5
6
7
8

C271

1000PF

+2.5V

1
R189

0.1UF

C264
0.1UF

LAN_RD+
LAN_RD-

0.1UF

+3VLAN

47K

@10PF

1
C260

C15

C246

C253

1000PF

CS
SK
DI
DO

1
2
3
4

U3
LAN_EECS
LAN_EECLK
LAN_EEDI
LAN_EEDO

AUX

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

10K

@22

C252

2
0_1206

+2.5VLAN

16,21,22,27,28 C/BE#2
16,18,21,22,27,28 FRAME#
16,18,21,22,27,28 IRDY#
16,18,21,22,27,28 TRDY#
16,18,21,22,27,28 DEVSEL#
16,18,21,22,27,28 STOP#
16,18,21,22,27 PERR#
16,18,22,27 SERR#
16,18,21,22,27,28 PAR
16,21,22,27,28 C/BE#1

R227

0.1UF

C275

1000PF

C273

0.1UF

+3V

+3VLAN

CLK_PCI_LAN

C254

1
2

18PF

R207
5.6K

ACTIVITY#
STOP#
PERR#
SERR#
PAR

AD18
AD17
AD16
C/BE#2
FRAME#
IRD Y#
TRDY#
DEVSEL#

AD[0..31]

AD21
AD20
AD19

AD22

16,21,22,27,28 AD[0..31]

U4

AUX
EECS
EESK
EEDI
EEDO
AD0
AD1
GND
AD2
AD3
VDD25
VDD
AD4
AD5
AD6
VDD25
VDD
AD7
CBE0B
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

C274
0.1UF

+3V

1
R228

+3VLAN

C236

AD31
AD30

INTAB
RSTB
CLK
GNTB
REQB
AD31
AD30
GND
AD29
VDD
AD28
AD27
AD26
AD25
AD24
VDD25
VDD
CBE3B
IDSEL
AD23

18PF

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

C237

13 CLK_PCI_LAN
16,18 GNT#3
16,18 REQ#3

+3VLAN
LAN_X2

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
14,22,23,27,28 CBRST#

2
0
2
@0
CLK_PCI_LAN

ACTIVITY#
LINK10_100#

+3V

LED0
LED1
NC
LED2
AVDD25
AVDD
ISOLATEB
GND
TXD+
TXDAVDD
AVDD25
RXIN+
RXINGND
RTSET
RTT2
RTT3
GND
X1
X2
AVDD
AVDD25
PMEB
GND
VCTRL
NC
NC
NC
VDD25

1
R23
1
R22

Y2
25 MHz

+2.5VLAN

AD22
GND
AD21
AD20
AD19
VDD
VDD25
AD18
AD17
AD16
CBE2B
FRAMEB
IRDYB
TRDYB
DEVSELB
GND
STOPB
PERRB
SERRB
PAR
CBE1B
VDD
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8

16,18,22 PIRQB#
7,14,16,19,21,22,23,24,27,28,34 PCIRST#

***
LAN_X1

R205
15K

0.1UF

C214
@ 10UF_10V_1206

@ 0.1UF

+2.5VLAN

LAN_X1
LAN_X2
VCTRL

D43
RB751V

5.6K_1%
R204

4.7UF_10V_1206

2
1K

C213

0.1UF

47K

1
R208

+2.5VLAN

C224

1
L23
C218

C234

10K

***

0.1UF

@ 2SB1197K

+3VS

LAN_TDLAN_TD+

0.1UF

2
4.7UH

LAN_PME#
LAN_RDLAN_RD+

C235

C233

32

1
L30

AVDD-3

AVDD-1

LAN_GND

COMPAL ELECTRONICS, INC

0.1UF
Title
PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
3

SCHEMATIC, M/B LA-1331

Document Number

Rev
2A

401207
, 18, 2004

Sheet
1

61

of

83

IEEE1394 Controller/PHY

+3VS

R437
1M_0402

.1UF

C599

C612
.1UF

.1UF

C533

.1UF

C525

.1UF

C515

.1UF

C514

.1UF

C611
.1UF

Enable I2C EEPROM

10PF_0402

R436
1K

C509

C506

+3VS

R438

AD[0..31]

16,20,22,27,28 AD[0..31]

.1UF

2
C507
10PF

C508

.1UF

C504

24.576MHz
+3VS

X4

2K
+3VS

R426
1K

+3VS
C503
.1UF

C590

C512
.1UF

C517

C520

.1UF

.1UF

.1UF

CLK_PCI_1394
R449

GNT#0
REQ#0

AD31
AD30
AD29
AD28
AD27

1 2

33

1
2

AD5
AD6
AD7
C/BE#0

16,20,22,27,28

AD13
AD14
AD15

R411
56.2_1%
C/BE#1
PAR
PERR#

16,20,22,27,28
16,18,20,22,27,28
16,18,20,22,27

XTPBIAS0
XTPA0+
XTPA0XTPB0+
XTPB0-

AD8
AD9
AD10
AD11
AD12

R410
56.2_1%

C489
3

1UF_25V_0805
1
L52
1
L53
1
L54
1
L55

R408
56.2_1%

1394 VT6306
56.2_1%

*
*
*
*

2
0

JP12
4
3
2
1

2
0
2
0
2
0

4
3
2
1

Molex SD-54030-0411

2
AD16
AD17
AD18
AD19
AD20

AD21

AD22
AD23

AD24
AD25
AD26

STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
C/BE#2

16,20,22,27,28 C/BE#3
AD16
4

1
R452

R418
5.11K

C487
220PF

22PF

AD2
AD3
AD4

R409

103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

C600

R439
510

1/20 EECK,EEDI RENAMED TO EECK_LAN,EEDI_LAN

CLK_PCI_1394

EECK_LAN
EEDI_LAN

AD0
AD1

16,18
16,18

8
7
6
5

VCC
WC#
SCL
SDA

24C02-27
EECK_LAN
EEDI_LAN

14,16,18,22 PIRQA#
7,14,16,19,20,22,23,24,27,28,34 PCIRST#
13 CLK_PCI_1394

1394_PME# 32

A0
A1
A2
GND

.1UF

LPS/CMC
PME#
VSSC2
VDDC2
VSS9
VDD6
SCL/EECK
SDA/EEDI
EEDO
EECS
AD0
AD1
VSS8
RAMVSS
RAMVDD
AD2
AD3
AD4
VDD5
AD5
AD6
AD7
VSS7
CBE0#
AD8
AD9
AD10
AD11
AD12
VSS6
VDD4
AD13
AD14
AD15
CBE1#
PAR
PERR#
VSS5

1
2
3
4

C610

VDDARX0
XREXT
NC
GNDARX1
GNDATX1
XTPB0M
XTPB0P
XTPA0M
XTPA0P
XTPBIAS0
VDDARX1
VDDATX1
XTPB1M
XTPB1P
XTPA1M
XTPA1P
XTPBIAS1
GNDARX2
GNDATX2
XTPB2M
XTPB2P
XTPA2M
XTPA2P
XTPBIAS2
VDDARX2
VDDATX2
INTA#
PCIRST#
PCICLK
VSS1
GNT#
REQ#
AD31
AD30
AD29
AD28
AD27
VDD1

+3VS
U44
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

XTPB0XTPB0+
XTPA0XTPA0+
XTPBIAS0

65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102

.1UF

C513
47PF

GNDARX0
XCPS
VDDATX0
XO
XI
GNDATX0
PHYRESET
LINKON/TSIJMP
LREQ/TSOJMP
CTL1/PC1JMP
CTL0/PC0JMP
D7/PC2JMP
D6/CMCJMP
D5
PGND2
PVDD2
D4
D3
D2
D1
D0
MODE0
MODE1
PGND1
SCLK
PVDD1

C603
2

VSS2
AD26
AD25
AD24
CBE3#
IDSEL
AD23
AD22
VSS3
AD21
VDD2
VDDC1
VSSC1
AD20
AD19
AD18
AD17
AD16
VSS4
CBE2#
FRAME#
IRDY#
VDD3
TRDY#
DEVSEL#
STOP#

.1UF

R442
6.34K 1%

U45

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39

C597

2
100

16,18,20,22,27,28
16,18,20,22,27,28
16,18,20,22,27,28
16,18,20,22,27,28
16,18,20,22,27,28
16,20,22,27,28

@X3

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331 TRANSFERRED

Size
Document Number
Custom
Date:
A

FROM THE CUSTODY OF THE COMPE

Rev
2A

401207

, 18, 2004

Sheet
E

62

of

83

+3VS

CardBus Controller
OZ6933T (uBGA)

+3VS

CBRST#

+3VS

B14
A4
V9
K19
J19
E8

16,18,24,32 INT_SERIRQ

C5
E6

IRQ5/SERIRQ
IRQ7/SIN#/B_VPP_PGM

GND
GND

GND
GND
GND
GND
GND
NC
NC

S2_D10
S2_D9
S2_D1
S2_D8
S2_D0
S2_A0
S2_A1
S2_A2
S2_A3
S2_A4
S2_A5
S2_A6
S2_A25
S2_A7
S2_A24
S2_A17

P2
W5
V15
K18
E11
B15
E5

C631
.1UF

C630
.1UF

C534
.1UF
1

+S1_VCC

L18
M19
M18
M15
M17
N17
P18
R19
N14
R17
T19
R14
U15
P14
W15
U11
P10
W11
U10
V10
P9
R9
U9
W9
U8
R8
W7
V7
U7
W6
P8
U6

IRQ12/PME#
IRQ14/CLKRUN#
IRQ15/RING_OUT
SPKR_OUT#
LED_OUT/SKT_ACTIVITY
SKTB_ACTV

H3
K5

CardBus-OZ6933T-1

N18

Slot B

R450
@33

C604
@10PF

GRST#

R10
J18
B10
CORE_VCC
CORE_VCC
CORE_VCC

F2
J5
M6
P5
PCI_VCC
PCI_VCC
PCI_VCC
PCI_VCC

IDSEL
PCI_CLK
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PERR#
SERR#
PCI_REQ#
PCI_GNT#
IRQ9/INTA#
IRQ4/INTB#
LOCK#
RST#

32 PCM_PME#
16,18,24,27,28,32 PM_CLKRUN#
28
PCM_RI#
31 PCM_SPK#
33 PCM1_LED
33
PCM2_LED

C626
.1UF

A_SOCKET_VCC
A_SOCKET_VCC

R7
R13

A_REG#/CCBE3#
A_A12/CCBE2#
A_A8/CCBE1#
A_CE1#/CCBE0#

N15
V14
V11
W8

A_A16/CCLK
A_A23/CFRAME#
A_A15/CIRDY#
A_A22/CTRDY#
A_A21/CDEVSEL#
A_A20/CSTOP#
A_A13/CPAR
A_A14/CPERR
A_WAIT#/CSERR#
A_INPACK#/CREQ#
A_WE#/CGNT#
A_RDY_IRQ#/CINT#
A_A19/CBLOCK#
A_WP/CCLKRUN#
A_RST/CRESET#
A_D2/RFU
A_D14/RFU
A_A18/RFU
A_VS1/CVS1
A_VS2/CVS2
A_CD1#/CCD1#
A_CD2#/CCD2#
A_BVD2/CAUDIO
A_BVD1/CSTSCHG

V13
U14
P13
W14
U13
W13
R11
V12
R18
P17
R12
P12
U12
L17
P15
L19
V8
P11
W10
W16
V6
L14
M14
N19

B_BVD1/CSTSCHG
B_BVD2/CAUDIO
B_CD2#/CCD2#
B_CD1#/CCD1#
B_VS2/CVS2
B_VS1/CVS1
B_A18/RFU
B_D14/RFU
B_D2/RFU
B_RESET/CRESET#
B_WP/CCLKRUN#
B_A19/CBLOCK#
B_RDY_IRQ#/CINT#
B_WE#/CGNT#
B_INPACK#/CREQ#
B_WAIT#/CSERR#
B_A14/CPERR#
B_A13/CPAR
B_A20/CSTOP#
B_A21/CDEVSEL#
B_A22/CTRDY#
B_A15/CIRDY#
B_A23/CFRAME#
B_A16/CCLK

F8
C8
C6
J15
A10
E18
C14
G17
F7
C10
A5
A14
F12
E13
C9
A9
A15
C15
C13
B13
A13
C12
B12
E12

B_CE1#/CCBE0#
B_A8/CCBE1#
B_A12/CCBE2#
B_REG#/CCBE3#

G14
A16
A12
F9

B_SKT_VCC
B_SKT_VCC
B_SKT_VCC

G19
F13
E7

C632

C633

C634

.1UF

.1UF

.1UF

S1_REG# 23

S1_A12
S1_A8

S1_A[0..25]
S1_CE1#

R457
1

S1_A23
S1_A15
S1_A22
S1_A21
S1_A20
S1_A13
S1_A14

2 33

S1_A19
S1_D2
S1_D14
S1_A18

S2_A18
S2_D14
S2_D2
S2_A19

S2_A14
S2_A13
S2_A20
S2_A21
S2_A22
S2_A15
S2_A23
1
R446
S2_A8
S2_A12

S1_A[0..25] 23

23
S1_D[0..15] 23

S1_A16

S2_A[0..25]
S1_WAIT# 23
S1_INPACK# 23
S1_WE# 23
S1_RDY# 23
S1_WP
S1_RST

23
23

S1_VS1
S1_VS2
S1_CD1#
S1_CD2#
S1_BVD2
S1_BVD1

23
23
23
23
23
23

S2_BVD1
S2_BVD2
S2_CD2#
S2_CD1#
S2_VS2
S2_VS1

23
23
23
23
23
23

S2_RST
S2_WP

23
23

S2_A[0..25] 23

S2_D[0..15]

S2_D[0..15] 23

S2_RDY# 23
S2_WE# 23
S2_INPACK# 23
S2_WAIT# 23

2
33

S2_A16

S2_CE1#

23

S2_REG# 23
+S2_VCC

C537

C535

C536

.1UF

.1UF

.1UF

SLATCH
SLDATA
RTCCLK

23
23
16,23,28

S2_A10
S2_D15
S2_D7
S2_D13
S2_D6
S2_D12
S2_D5
S2_D11
S2_D4
S2_D3

CLK_PCI_CB

H5
E3
L3
K6
L1
L2
L5
M2
L6
M1
G6
F5
B5
F6
V5
D1

S2_A9

100
2

C/BE3#
C/BE2#
C/BE1#
C/BE0#

Slot
A

S2_A11

13 CLK_PCI_CB
16,18,20,21,27,28 DEVSEL#
16,18,20,21,27,28 FRAME#
16,18,20,21,27,28 IRDY#
16,18,20,21,27,28 TRDY#
16,18,20,21,27,28 STOP#
16,18,20,21,27,28 PAR
16,18,20,21,27 PERR#
16,18,20,27 SERR#
16,18 REQ#2
16,18 GNT#2
14,16,18,21 PIRQA#
16,18,20 PIRQB#
16,18 PLOCK#
7,14,16,19,20,21,23,24,27,28,34 PCIRST#

R451
AD20 1
CLK_PCI_CB

G1
K3
M3
R1

O 2 MICRO
CARDBUS CONTROLLER
OZ6933 209PIN CSP

B_D10/CAD31
B_D9/CAD30
B_D1/CAD29
B_D8/CAD28
B_D0/CAD27
B_A0/CAD26
B_A1/CAD25
B_A2/CAD24
B_A3/CAD23
B_A4/CAD22
B_A5/CAD21
B_A6/CAD20
B_A25/CAD19
B_A7/CAD18
B_A24/CAD17
B_A17/CAD16
B_IOWR#/CAD15
B_A9/CAD14
B_IORD#/CAD13
B_A11/CAD12
B_OE#/CAD11
B_CE2#/CAD10
B_A10/CAD9
B_D15/CAD8
B_D7/CAD7
B_D13/CAD6
B_D6/CAD5
B_D12/CAD4
B_D5/CAD3
B_D11/CAD2
B_D4/CAD1
B_D3/CAD0

C/BE#3
C/BE#2
C/BE#1
C/BE#0

C622
.1UF

B6
A6
B7
C7
A7
B8
A8
E9
B9
F10
E10
F11
C11
B11
A11
E14
D19
F15
E17
F14
G15
E19
F18
F17
G18
H15
H14
H17
H18
H19
J14
J17

16,20,21,27,28
16,20,21,27,28
16,20,21,27,28
16,20,21,27,28

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

IRQ3/VCC3#
SCLK/A_VCC_5#
SDATA/B_VCC_3#
SLATCH/B_VCC_5#
IRQ9/A_VPP_VCC
IRQ10/B_VPP_VCC

E1
E2
F3
F1
G5
H6
G3
G2
H2
H1
J1
J2
J3
J6
K1
K2
M5
N2
N1
N3
N6
P1
P3
N5
P6
R2
R3
T1
W4
R6
U5
P7

W12
K14
K15
K17
P19
F19

S1_IOWR# 23
S1_IORD# 23
S1_OE#
23
S1_CE2# 23

AUX_VCC

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

PCI

S1_IOWR#
S1_IORD#
S1_OE#
S1_CE2#

L15

.1UF

A_D10/CAD31
A_D9/CAD30
A_D1/CAD29
A_D8/CAD28
A_D0/CAD27
A_A0/CAD26
A_A1/CAD25
A_A2/CAD24
A_A3/CAD23
A_A4/CAD22
A_A5/CAD21
A_A6/CAD20
A_A25/CAD19
A_A7/CAD18
A_A24/CAD17
A_A17/CAD16
A_IOWR/CAD15
A_A9/CAD14
A_IORD#/CAD13
A_A11/CAD12
A_OE#/CAD11
A_CE2#/CAD10
A_A10/CAD9
A_D15/CAD8
A_D7/CAD7
A_D13/CAD6
A_D6/CAD5
A_D12/CAD4
A_D5/CAD3
A_D11/CAD2
A_D4/CAD1
A_D3/CAD0

C617

U49

C620
.1UF

+3VS

16,20,21,27,28 AD[0..31]

C607
.1UF

14,20,23,27,28

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

+3V

C616
4.7UF_10V_0805

S2_CE2#
S2_OE#
S2_IORD#
S2_IOWR#

S2_CE2# 23
S2_OE#
23
S2_IORD# 23
S2_IOWR# 23

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, M/B LA-1331

Size
Document Number
Custom
Date:

COMPAL ELECTRONICS, INC

Rev
2A

401207

, 18, 2004

Sheet
E

63

of

83

PCMCIA POWER CTRL.

CARDBUS
SOCKET

+5V
+3V

+12V

+S1_VPP

+S1_VPP

W=40mils

JP19

+S1_VCC

1
1
1
1
1
1
1

7
24

12V
12V

2 C177
.1UF
2 C179
.1UF
2 C178
.1UF
2 C170
.1UF
2 C172
.1UF
2 C171
.1UF

1
2
30

5V
5V
5V

15
16
17

3.3V
3.3V
3.3V

33

3
5
4

22
SLDATA
22
SLATCH
16,22,28 RTCCLK

13
19
18

OCCB#
+3V

AVPP
AVCC
AVCC
AVCC

8
9
10
11

BVPP
BVCC
BVCC
BVCC

23
20
21
22

RESET
RESET#

6
14

NC
NC
NC
NC

26
27
28
29

CBRST#

DATA
LATCH
CLOCK
APWR_GOOD#
BPWR_GOOD#
OC#

GND

C174

VCC_5V

22
22

4.7UF_10V_0805

+S2_VPP

S1_CD2#
S1_WP

+S2_VPP

W=40mils

+S2_VCC

25
C176
2 1UF_25V_0805

U15

C175

22

S1_BVD1

4.7UF_10V_0805
22

S1_BVD2

22

S1_REG#

22

S1_INPACK#

12

2
TPS2206AI/TPS2216
R162
100K

22

S1_WAIT#

22

S1_RST

22

S1_VS2

1
R322

CBRST#

CBRST#

14,20,22,27,28

+S1_VCC

+3V POWER

R323

1
R318

2
@0

S1_RDY#
S1_WE#

22

S1_IOWR#

22

S1_IORD#

C521

.01UF

1UF_25V_0805

22
22
22

S1_VS1
S1_OE#
S1_CE2#

22

S1_CE1#

W=30mils

+S1_VPP

22
22

+3V

W=30mils
C523

C522

C524
.01UF

S1_WAIT#
S1_A4
S1_RST
S1_A5
S1_VS2
S1_A6
S1_A25

S1_A16

2
G_RST#

S1_A0
S1_BVD2
S1_A1
S1_REG#
S1_A2
S1_INPACK#
S1_A3

+S1_VPP

U33A
74LVC125

10K

32

+S2_VPP

S1_A[0..25]
S1_D[0..15]
S2_A[0..25]
S2_D[0..15]

S1_A[0..25]
S1_D[0..15]
S2_A[0..25]
S2_D[0..15]

1UF_25V_0805

22

+S1_VCC

S1_CD1#

S1_A21
S1_RDY#
S1_A20
S1_WE#
S1_A19
S1_A14
S1_A18
S1_A13
S1_A17
S1_A8
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_VS1
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_CE1#
S1_D14
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_CD1#
S1_D3

a68
a34
a67
a33
GND
a66
a32
a65
a31
a64
a30
a63
GND
a29
a62
a28
a61
a27
a60
a26
GND
a59
a25
a58
a24
a57
a23
a56
GND
a22
a55
a21
a54
a20
a53
GND
a19
a52
a18
a51
a17
a50
a16
a49
a15
a48
a14
a47
a13
GND
a46
a12
a45
a11
a44
GND
a10
a43
a9
a42
a8
GND
a41
a7
a40
a6
a39
a5
GND
a38
a4
a37
a3
a36
a2
a35
a1

b68
b34
b67
b33
GND
b66
b32
b65
b31
b64
b30
b63
GND
b29
b62
b28
b61
b27
b60
b26
GND
b59
b25
b58
b24
b57
b23
b56
GND
b22
b55
b21
b54
b20
b53
GND
b19
b52
b18
b51
b17
b50
b16
b49
b15
b48
b14
b47
b13
GND
b46
b12
b45
b11
b44
GND
b10
b43
b9
b42
b8
GND
b41
b7
b40
b6
b39
b5
GND
b38
b4
b37
b3
b36
b2
b35
b1

B77
B76
B75
B74
B73
B72
B71
B70
B69
B68
B67
B66
B65
B64
B63
B62
B61
B60
B59
B58
B57
B56
B55
B54
B53
B52
B51
B50
B49
B48
B47
B46
B45
B44
B43
B42
B41
B40
B39
B38
B37
B36
B35
B34
B33
B32
B31
B30
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1

S2_CD2#
S2_WP

S2_CD2# 22
S2_WP
22

S2_D10
S2_D2
S2_D9
S2_D1
S2_D8
S2_D0
S2_BVD1

S2_BVD1 22

S2_A0
S2_BVD2
S2_A1
S2_REG#
S2_A2
S2_INPACK#
S2_A3
S2_WAIT#
S2_A4
S2_RST
S2_A5
S2_VS2
S2_A6
S2_A25

S2_BVD2 22
S2_REG# 22
S2_INPACK# 22
S2_WAIT# 22
S2_RST

22

S2_VS2

22

S2_A7
S2_A24
S2_A12
S2_A23
S2_A15
S2_A22
S2_A16
+S2_VPP
+S2_VCC
S2_A21
S2_RDY#
S2_A20
S2_WE#
S2_A19
S2_A14
S2_A18
S2_A13

S2_RDY# 22
S2_WE#

S2_A17
S2_A8
S2_IOWR#
S2_A9
S2_IORD#

22

S2_IOWR# 22
S2_IORD# 22

S2_A11
S2_VS1
S2_OE#
S2_CE2#
S2_A10
S2_D15
S2_CE1#
S2_D14
S2_D7
S2_D13
S2_D6
S2_D12
S2_D5
S2_D11
S2_D4
S2_CD1#
S2_D3

S2_VS1
S2_OE#
S2_CE2#

22
22
22

S2_CE1#

22

S2_CD1# 22

.1UF

C526

56PF

C527

C625
C528

C529
10UF_16V_1206

1000PF

S1_CD1# 1
@1000PF

+S2_VCC

PCMC154PIN

C486
S1_CD2# 1
@1000PF

C624
S2_CD1# 1
2
@1000PF

.1UF

56PF

C531

C532

C587
10UF_16V_1206

C530

C485

22
22
22
22

14

1
2
7,14,16,19,20,21,22,24,27,28,34 PCIRST#

PCMRST# 33

.1UF

S1_D10
S1_D2
S1_D9
S1_D1
S1_D8
S1_D0
S1_BVD1

S1_A7
S1_A24
S1_A12
S1_A23
S1_A15
S1_A22

+3V

C94

S1_CD2#
S1_WP

A77
A76
A75
A74
A73
A72
A71
A70
A69
A68
A67
A66
A65
A64
A63
A62
A61
A60
A59
A58
A57
A56
A55
A54
A53
A52
A51
A50
A49
A48
A47
A46
A45
A44
A43
A42
A41
A40
A39
A38
A37
A36
A35
A34
A33
A32
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1

1000PF

S2_CD2# 1
@1000PF

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

TRANSFERRED
SCHEMATIC, M/B LA-1331

Size
B

Document Number

Date:

, 18, 2004

FROM THE CUSTODY OF T

Rev
2A

401207
Sheet

64

of

83

.1UF
C276
1
2

U28

+3V
7,14,16,19,20,21,22,23,27,28,34 PCIRST#
LPCRST1

2
R251
10K

20
21
22
23

LAD0
LAD1
LAD2
LAD3

24
25

LFRAME#
LDRQ#

LPC_RST#

26
27

PCIRST#
LPCPD#

2
10K

CLK_LPC_SIO

50
17
30
28
29

GPIO12/IO_SMI#
IO_PME#
SIRQ
CLKRUN#
PCICLK

CLK_SIO14

19

CLK14

48
54
55
56
57
58
59
6
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

GPIO10
GPIO15
GPIO16
GPIO17
GPIO20
GPIO21
GPIO22
GPIO24
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47

51
52
64

GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO23/FDC_PP

18

VTR

53
65
93

VCC
VCC
VCC

7
31
60
76

VSS
VSS
VSS
VSS

16,32 LPC_FRAME#
16,18 LPC_DRQ#1
14,16,34 SUS_STAT#
+3VS
16,18,22,32 INT_SERIRQ
16,18,22,27,28,32 PM_CLKRUN#
13 CLK_LPC_SIO

13

CLK_SIO14

14
14
14
14

PID0
PID1
PID2
PID3

+3VS

1
R177
1
R178

1
R192

1
R3

1
R233

2
10K

2
10K

2
10K
2
10K

+3VS

CLK_LPC_SIO

2
2 1

C257
.1UF

C230

4.7UF_10V_0805 .1UF
10V

2 1

C232

C258

C209

@33

10

R211

R234

A1

A2

C277

1
R248

LPCRST

Y2

GND

D23
RB751V

2
10K

+3VS

LPC_RST#

LPC_RST# 32

.1UF

U24
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

15PF

Y1

LPC_AD[0..3]

16,32 LPC_AD[0..3]

CLK_SIO14

VCC

NC7WZ14

SUPER I/O SMsC FDC47N227

@22PF

C208
.1UF

PD0/INDEX#
PD1/TRK0
PD2/WRTPRT#
PD3/RDATA#
PD4/DSKCHG#
PD5
PD6/MTR0#
PD7

68
69
70
71
72
73
74
75

LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7

BUSY/MTR1#
PE/WDATA#
SLCT/WGATE#
ERROR#/HDSEL#
ACK#/DS1#
INIT#/DIR#
AUTOFD#/DRVDEN0#
STROBE#/DS0#
SLCTIN#/STEP#

79
78
77
81
80
66
82
83
67

LPTBUSY
LPTPE
LPTSLCT
LPTERR#
LPTACK#

DTR2#
CTS2#
RTS2#
DSR2#
TXD2
RXD2
DCD2#
RI2#

100
99
98
97
96
95
94
92

DTR1#
CTS1#
RTS1#
DSR1#
TXD1
RXD1
DCD1#
RI1#

89
88
87
86
85
84
91
90

IRMODE/IRRX3
IRRX2
IRTX2

63
61
62

RDATA#
WDATA#
WGATE#
HDSEL#
DIR#
STEP#
DS0#
INDEX#
DSKCHG#
WRTPRT#
TRK0#
MTR0#
DRVDEN0

16
10
11
12
8
9
5
13
4
15
14
3
1

DRVDEN1
GPIO11/SYSOPT

LPD[0..7]

LPTBUSY
LPTPE
LPTSLCT
LPTERR#
LPTACK#
INIT#
LPTAFD#
LPTSTB#
SLCTIN#

25
25
25
25
25
25
25
25
25

LPD[0..7] 25

RP9
DCD#1
RI#1
CTS#1
DSR#1

CTS#2

1
2
3
4

+3VS

8
7
6
5

RP10
CTS#2
DSR#2
DCD#2
RI#2

+3VS

1
2
3
4

8
7
6
5
2

DSR#2

DCD#2
RI#2

8P4R_4.7K

1
R206

2
1K

8P4R_4.7K
+5V
JP24

2
49

DTR#1
CTS#1
RTS#1
DSR#1
TXD1
RXD1
DCD#1
RI#1

1
R197

28
28
28
28
28
28
28
28

2
1K

IRMODE 25
IRRX
25
IRTXOUT 25
RDATA#
WDATA#
WGATE#
HDSEL#
FDD IR#
STEP#
DRV0#
INDEX#
DSKCHG#
WP#
TRACK0#
MTR0#

2
R232
1
R191

RDATA#
WDATA#
WGATE#
HDSEL#
FDDIR#
STEP#
DRV0#
INDEX#
DSKCHG#
WP#
TRACK0#
MTR0#
3MODE#

19
19
19
19
19
19
19,33
19
19
19
19
19
19

1
10K
2
1K

+5VS

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7
8
9
10
@96212-1011S

Base I/O Address

* 0 = 02Eh
1 = 04Eh

SMsC LPC47N227

COMPAL ELECTRONICS, INC

Title
PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

SCHEMATIC, M/B LA-1331

Document Number

Rev
2A

401207
, 18, 2004

Sheet
E

65

of

83

FIR Module
2

+3VS

C190

1
R2

2
3.3_1206

1
R1

2
@3.3_1206

+IR_ANODE

4.7UF_1206

+3VS

2
R164

R163
47_1206

1
@ 10K
2

1UF_0805

24

IRRX

IRRX

1
2

+IR_ANODE

IRED Anode

Txd

IRTXOUT

SD/Mode

IRMODE

Mode

IRED Cathode
Rxd
Vcc

IRTXOUT 24
IRMODE

24

GND

.1UF
FIR TFDU6101E

+IR_GND

SD/MODE: SHUTDOWN MODE, HIGH ACTIVE

MODE: HIGH/LOW SPEED SELECT

+5V_PRN

PARALLEL PORT

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

10
9
8
7
6

+5V_PRN
CP2
RP4
10P8R_2.7K

D3
+5VS

1
RB420D

1
2
3
4
5

100PF

4
6

C4

+5V_PRN
24

AFD#/3M#
LPTERR#
LPTINIT#
LPTSLCTIN#

LPTSTB#

24

INIT#

24

SLCTIN#

R171
33
2

+5V_PRN

LPTINIT#

24

LPTAFD#

24

LPTERR#

LPTSLCTIN#

F D4

RP7
LPD0
LPD1
LPD2
LPD3

RP5
10P8R_2.7K

LPD7
LPD6
LPD5
LPD4

+5V_PRN
F D3
F D2
F D1
F D0

F D0
LPTERR#
F D1
LPTINIT#
F D2
LPTSLCTIN#
F D3

1
2
3
4

8
7
6
5

1
2
3
4

8P4R_68
RP6
8
7
6
5

F D0
F D1
F D2
F D3

F D5
F D6
F D7

F D7
F D6
F D5
F D4

24

LPTACK#

24

LPTBUSY

24

LPTPE

24

LPTSLCT

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

R170
2.2K

C186
220PF

R169

AFD#/3M#
LPTERR#
LPTINIT#
LPTSLCTIN#

1
2
3
4

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

4
3
2
1

8P4C_220PF
CP1
5
6
7
8

F D0
F D1
F D2
F D3

1
2
3
4

8P4C_220PF
CP4
8
7
6
5

F D4
F D5
F D6
F D7

1
2
3
4

8P4C_220PF
CP3
8
7
6
5

33
R168

R172
33

F D4
F D5
F D6
F D7

LPTSTB#

AFD#/3M#

10
9
8
7
6

C1

1
2
3
4
5

+IR_VCC

U1
C188

33

1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13

8
7
6
5

8P4C_220PF
JP4
LPTCN-25

8P4R_68

24

LPD[0..7]

LPD[0..7]

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

Size

TRANSFERRED FROM THE CUSTODY OF T

Document Number

Rev
2A

401207
Date:

, 18, 2004

Sheet

66

of

83

USB PORT

+USB_VCCA

F4

+USB_VCCC

F2

150UF_D2_6.3V

150UF_D2_6.3V

POLYSWITCH_0.75A

C413

.1UF

R176

R180

1000PF

560K

C204

JP9

L5
FBM-11-160808-121
1
2
1
2
L4
FBM-11-160808-121
C103

1
2
3
4

C96

17
17

USB3_DUSB3_D+

USB_PN3
USB_PP3

L22
FBM-11-160808-121
1
2
1
2
L21
FBM-11-160808-121

C211

C212

47PF

.1UF

C203

.1UF

1
1

L16
CHB4516G750_1806
4516

C391

47PF

+USB_VCCB

F3

150UF_D2_6.3V

+5V

R186

POLYSWITCH_0.75A

C205

C217

.1UF

470K

USB_BGND

USB_OC#1

1
C206

R187

JP1

1000PF

560K

1
2
3
4
5
6
7
8

USB_PN1
USB_PP1

USB1_DUSB1_D+

1
1

2
2
L18
FBM-11-160808-121

C207

L17
CHB4516G750_1806

17
17

C193
47PF

L19
FBM-11-160808-121

17

L38
CHB4516G750_1806
4516

47PF

SUYIN USB Connector 2569A-04G3T-B

47PF

560K

USB_PN0
USB_PP0

USB_CGND

1
R321

1000PF

C408

2
17
17

USB_OC#3

17

USB0_DUSB0_D+

C199

.1UF

470K

USB_OC#0

17

C195

USB_AGND

470K

C400

R324

POLYSWITCH_0.75A

+5V

+5V

SUYIN 2553A-0BG5T-A
C194
47PF

.1UF

4516

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

TRANSFERRED
SCHEMATIC, M/B LA-1331

Size
B

Document Number

Date:

, 18, 2004

FROM THE CUSTODY OF T

Rev
2A

401207
Sheet

67

of

83

Q38
@SI2301DS

+3V
+5VS_MINIPCI

1
R153
1
R151

PCIRST#
2
0
2
@0

PCIRST#

7,14,16,19,20,21,22,23,24,28,34

CBRST#

14,20,22,23,28

C136
@1000PF

C138
@.1UF

MINI_RST#

C456
@1UF_25V_0805

C491
@1UF_25V_0805

R366

1
1

+3.3VAUX

+3VALW

C168
C142
@10UF_16V_1206

@.1UF

R420

EN_WOL#

+5VALW

@100K

+3V
C126

1
LAN RESERVED

7SH08FU

L12

***

@.1UF

C165

REQ#4

16,18 REQ#4

C146

CLK_MINIPCI

13 CLK_MINIPCI

.1UF

REQ#1

16,18 REQ#1

AD31
AD29

16,20,21,22,28 AD31
16,20,21,22,28 AD29
AD27
AD25

16,20,21,22,28 AD27
16,20,21,22,28 AD25

CLK_MINIPCI

1 2

R156
@10

C139
@33PF

PIRQD#

16,18,28 PIRQD#

W=40mils

1
CHB1608B121
0603

D42
RB751V

C/BE#3
AD23

16,20,21,22,28 C/BE#3
16,20,21,22,28 AD23

AD21
AD19

16,20,21,22,28 AD21
16,20,21,22,28 AD19

AD17
C/BE#2
IRDY#

16,20,21,22,28 AD17
16,20,21,22,28 C/BE#2
16,18,20,21,22,28 IRDY#

PM_CLKRUN#
SERR#

16,18,22,24,28,32 PM_CLKRUN#
16,18,20,22 SERR#

PERR#
C/BE#1
AD14

16,18,20,21,22 PERR#
16,20,21,22,28 C/BE#1
16,20,21,22,28 AD14

AD12
AD10

16,20,21,22,28 AD12
16,20,21,22,28 AD10

AD8
AD7

16,20,21,22,28 AD8
16,20,21,22,28 AD7

AD5

16,20,21,22,28 AD5

AD3

16,20,21,22,28 AD3
+5VS_MINIPCI
16,20,21,22,28 AD1

+5VS

1
L10

2
0_0603
0603

+5VS_MINIPCI

W=30mils
AD1

W=30mils

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123

1
KEY
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123

2
KEY
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

C141
10UF_16V_1206

@.1UF

LAN RESERVED

W=30mils
PIRQC#

+5VS_MINIPCI
PIRQC# 16,18,28
GNT#4
16,18
+3.3VAUX

W=40mils
MINI_RST#

+3VS_MINIPCI
L11
W=40mils

GNT#1

16,18

WLANPME# 32

.1UF

AD30

MINI_IDSEL
1
R35
AD22
AD20
PAR
AD18
AD16

AD28
AD26
AD24
AD18
2
100

FRAME#
TRDY#
STOP#
DEVSEL#
AD15
AD13
AD11
AD9
C/BE#0
AD6
AD4
AD2
AD0

W=20mils

1
C144

AD30

16,20,21,22,28

AD28
AD26
AD24

16,20,21,22,28
16,20,21,22,28
16,20,21,22,28

AD22
AD20
PAR
AD18
AD16

16,20,21,22,28
16,20,21,22,28
16,18,20,21,22,28
16,20,21,22,28
16,20,21,22,28

FRAME#
TRDY#
STOP#

16,18,20,21,22,28
16,18,20,21,22,28
16,18,20,21,22,28

KILL_SW

C164

RING

+3V

C153 CHB1608B121
0603
.1UF

DEVSEL# 16,18,20,21,22,28
AD15
AD13
AD11

16,20,21,22,28
16,20,21,22,28
16,20,21,22,28

AD9
C/BE#0

16,20,21,22,28
16,20,21,22,28

AD6
AD4
AD2
AD0

16,20,21,22,28
16,20,21,22,28
16,20,21,22,28
16,20,21,22,28

+3.3VAUX

TIP

+3VS_MINIPCI

+3V

***

JP18

33,34

.1UF

WL_OFF#

C143

Mini-PCI SLOT

33

+3VS_MINIPCI

U13

11,32

.1UF

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

TRANSFERRED
SCHEMATIC, M/B LA-1331

Size
B

Document Number

Date:

, 18, 2004

FROM THE CUSTODY OF T

Rev
2A

401207
Sheet

68

of

83

@.1UF

INPUT OUTPUT

+SMC_VCC

5
3

VCC
GND

SM_LED

34

.1UF

NC

SM_LED
R299

6
17
28
39
49
60
70
81
92
103
113
124

+SMC_VCC
+3V

+SMC_VCC

VIN
VOUT
VIN/CE VOUT

+3V

R352 @10K
FCMODE

+3V

1
R382

CLK_PCI_SD/SM 1
R343
@22

2
@0

2
C433
@10PF

@0
R328
1

+3V

IDSEL0

R349
1

16,20,21,22,27 C/BE#0
16,20,21,22,27 C/BE#1
16,20,21,22,27 C/BE#2
16,20,21,22,27 C/BE#3
16,18,20,21,22,27 PAR
16,18,20,21,22,27 FRAME#
16,18,20,21,22,27 IRDY#
16,18,20,21,22,27 TRDY#
16,18,20,21,22,27 STOP#
AD22
AD22

@100K
2 IDSEL1

R335 1
R350 1

16,18,22,24,27,32 PM_CLKRUN#
16,18,20,21,22,27 DEVSEL#
13 CLK_PCI_SD/SM
R104 1
@0 2
PCTRST#1
2
16,18,27 PIRQC#
16,18,27 PIRQD#
R105 @0
32 SM/SD_PME#

14,20,22,23,27 CBRST#
7,14,16,19,20,21,22,23,24,27,34 PCIRST#

CLK_PCI_SD/SM

1
1
1
1
1

2
2
2
2
2

@100K
@100K
@100K
@100K
@100K

SDCD0
SDCD1
SDCD2
SDCD3
SDCMD

R371 @0

13
120

IDSEL0
IDSEL1

55
27
125
123
121
122
128

CLKRUN#
DEVSEL#
PCICLK
PCIRST#
INTA#
INTB#
PME#

101
102
83
85
89
98
104
105
69

SDCD0
SDCD1
SDCD2
SDCD3
SDCMD
SDCLK
SDCD#
SDWP
SDPWR

CLK32
PWRST#
SUSPEND#
FCMODE
ROM_CS
ROM_SK
ROM_D

59
56
57
58
68
67
66

GND

C494
@ 0.1UF

C481

R311

SMD0
SMD1
SMD2
SMD3
SMD4
SMD5
SMD6
SMD7
SM_CLE
SM_ALE
SM_CE#
SMWE#
SM_RE#
SM_WP#
SM_R/B#
SMCD#
SM_LVD
SMWPD#
SMEJSW#
R395 1
R373 1
R403 1
SMVC3EN

SMCD# 1

@1K
@10UF_16V_1206

R423 @ 0
2 SMEJSW#

C496 @1000PF
1
2

+3V

2 @100K
2 @100K
2 @100K

C452

@1000PF

@RT9701-CB

R422
1

@100K
2

JP14
12
11
13
10
14
9
15
8
16
7
17
6
18
5
19
4
20
3
21
2
22
1
23
24

SMCD#
SMD4
SMD5
SMD3
SMD6
SMD2
SMD7
SMD1
SM_LVD
SMD0

+3V
+3V
+3V

SM_WP#
SM_R/B#
SMWE#
SM_RE#
SM_ALE
SM_CE#
SM_CLE
+SMC_VCC

PWRST#
SUSP#
FCMODE

RTCCLK

16,22,23

SUSP#

29,32,36,40,41

+3V

1
R136

2 SMWPD#
@10K

2
@100K

+3V

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7

110
111
112
114
115
116
117
119

NC
NC

126
127

R368
R369
R363
R364
R358
R359
R353
R354

1
1
1
1
1
1
1
1

@100K
@100K
@100K
@100K
@100K
@100K
@100K
@100K

2
2
2
2
2
2
2
2

SMD0
SMD1
SMD2
SMD3

+3V
+3V

When the serial

ROM interface is
not applied need
pull up.

+3V

1
2
3
4

8
7
6
5

@8P4R_100K*
RP80
SMD4
SMD5
SMD6
SMD7

1
2
3
4

8
7
6
5

@8P4R_100K*
RP77
SM_CLE
SM_ALE
SM_WP#
SM_LVD

TEST0
TEST1
TEST2
TEST3

61
62
63
64

1
R383

@0

1
2
3
4

8
7
6
5

@8P4R_100K*

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

+3V

+3V

8
7
6
5

TXD1
RTS#1
RI#1
COM_RI#

@8P4R_100K*
+3V

SM_R/B#

R319
@10K
TXD1
RTS#1
RI#1

24
24
24

22

PCM_RI#

R320
@10K

D34
2

1
R365

RING#

@RB751V
COM_RI#

SD/COM

@ TC6371AF

+5V

SDCD1
SDCD3
SDCLK
SDWP
SDLED

1
2
3
4

2
@10K

RXD1
DSR#1
CTS#1
DTR#1
DCD#1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

+SMC_VCC
RP78
SM_CE#
SMWE#
SM_RE#

24
24
24
24
24

RXD1
DSR#1
CTS#1
DTR#1
DCD#1
SUSP#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

1
12
23
33
44
54
65
76
87
97
108
118

JP15
SDCD0
SDCD2
SDCMD
SDCD#
SDPWR

VCC
PCD#
I/O4
VSS
I/O5
I/O3
I/O6
I/O2
I/O7
I/O1
LVD
I/O0
GND
WP#
RDY
WE#
RD#
ALE
CE#
CLE
VCC
VSS
GND
WPRO#

@SmartMedia Slot
1
R296

GND

SD Transfer Conn.

SMD0
SMD1
SMD2
SMD3
SMD4
SMD5
SMD6
SMD7
SMCLE
SMALE
SMCE#
SMWE#
SMRE#
SMWP#
SMRB#
SMCD#
SMLVD
SMWPD#
SMEJSW#
SMLED#
SMLOCK#
SMEJCT#
SMVC3EN
SMVC5EN

86
90
93
95
99
96
94
91
75
78
77
80
79
84
82
100
88
73
74
107
109
106
72
71

RP79

SD CARD I/F

+3V

R384
R412
R385
R396
R370

IDSEL0
IDSEL1

2 @100
2 @100

PCI I/F

R372 @10K

SmartMedia I/F

System I/F

@ 0.1UF
1

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
PAR
FRAME#
IRDY#
TRDY#
STOP#

GPIO I/F

C447
2

53
52
51
50
48
47
46
45
42
41
40
38
37
36
35
34
22
21
20
19
18
16
15
14
10
9
8
7
5
4
3
2
43
32
31
11
30
24
25
26
29

Test Pins

PWRST#

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE#0
C/BE#1
C/BE#2
C/BE#3

1
5

3
4

SMVC3EN

Power

U43

AD[0..31]

16,20,21,22,27 AD[0..31]

+5VS

Q26
@DTC114YKA

47K

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

U37

1
@110

@1K
@NC7S14

2
R314

10K

C478

D37
@HSMB-C110 BLUE

.1UF 1000PF

SM_LED

+3V

C479

C437

.1UF 1000PF

C462

.1UF

C458

C450

.1UF 1000PF

C442

C424

1
2

.1UF 1000PF
2

1
2

C425

1
C423

1
U31

C370

+3V

+3V

R292 @1M
2

32

Q27
@2N7002

2
G

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

TRANSFERRED
SCHEMATIC, M/B LA-1331

Size
Document Number
Custom

Rev
2A

401207

Date:

, 18, 2004

FROM THE CUSTODY OF THE COM

Sheet

69

of

83

**

1
R329

33,34 STOPBTN#

2
0

D36

+5VOZ

33 CD_STOPBTN#

OZ_STOPBTN#

2
@RB751V

X3
OSC1

OSC2

HCS0
HCS1

CCS0
CCS1

64
62

CD_SCS1#
CD_SCS3#

HDIOR#
HDIOW#
HIOCS16#
HIORDY

CDIOR#
CDIOW#
CIOCS16#
CIORDY

100
5
73
94

CD_SIOR#
CD_SIOW#
CIOCS16#
CD_ SIORDY

HINTRQ
HDMARQ
HDMACK#

CHINTRQ
CDMARQ
CHDMACK#

75
13
89

CD_IRQ
CD_DREQ
CD_DACK#

24
59

HRESET#
HDASPN

CRESET#
CDASPN

23
60

48
53
55
50
46

HSYNC
HBIT_CLK
HDATA_OUT
HDATA_IN
HACRSTN

SSYNC
SBIT_CLK
SDATA_OUT
SDATA_IN
SACRSTN

47
52
54
49
45

IDE_SDIOR#
IDE_SDIOW#

IDE_SDIOR#
IDE_SDIOW#

17

IDE_SIORDY

99
6
72
93

16,18 INT_IRQ15
17 IDE_SDDREQ
17 IDE_SDDACK#

74
IDE_SDDREQ 12
IDE_SDDACK# 88

DM_ON
PLAYBTN#
FRDBTN#
REVBTN#
OZ_STOPBTN#

PLAYBTN#
FRDBTN#
REVBTN#

10UF_16V_1206
10K

33

DM_ON
INTN

CD_INTA#

58

63
61

IDE_SDCS1#
IDE_SDCS3#

17
17

C407
10PF

44

CD_SBA0
CD_SBA1
CD_SBA2

IDE_SDCS1#
IDE_SDCS3#

SIDE_RST#

VDD

69
71
67

17
17

34
34
34

28
36
35
34
37
29
25
30

PAV_EN
PLAY/PAUSE
FFORWARD
REWIND
STOP/EJECT

PWR_CTL

PCSYSTEM_OFF
INTN
RESET#

D1

5,32

EC_SMD2

S1
1
Q31A
SI1906DL

26

SDATA

27

SCLK

G2

+5VALW
1

+5VCD

+5VALW

31
32

OSCI
OSCO

R119
200K

8P4R_10K
RP24
GPIO_0
GPIO_1
INTN

CD_SIORDY 19

1
2
3
4

8
7
6
5

8P4R_10K

CD_IRQ 19
CD_DREQ 19
CD_DACK# 19

RP23
PLAYBTN#
REVBTN#
FRDBTN#
STOPBTN#

CD_RSTDRV# 19

2
@10K
2
10K

56
57

R344
@1K
1
2
MODE1

+5VCD

1
R400

ISCDROM

R399

2
@0

MEDIA_DETECT 33
R249
100K

1
2
3
4

1
R332

2
@10K

1
R331

2
10K

CDD3
CDD1
CDD2
CDD0
CDD4
CDD6
CDD5
CDD7

1
2
3
4
5
6
7
8

CDD8
CDD9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15

8
7
6
5
4
3
2
1

8
7
6
5

STUFF
R399, R249
R400

RP25

CHIP
OZ165
0Z168

+5VCD

9
10
11
12
13
14
15
16
@16P8R_4.7K

Select SM BUS ADDRESS

STUFF

SMBus ID

R331
R332

B4h
34h

16
15
14
13
12
11
10
9
@16P8R_4.7K

Select OZ165 / OZ168

+5VCD

100K

C417
1UF_25V_0805

CIOCS16#

1
R393

2
47K

+5VMOD

+5VCD

U34
1
2
3
4

+5VALW
R109
1

R336
200K

R339
C414
10UF_16V_1206

OSC1
OSC2

Q31B
SI1906DL

4 S2

16
33
65
85
92

D2 3

EC_SMC2

5,32

1
R334
1
R340

GPIO_1
GPIO_0

38

8
7
6
5

@8P4R_10K

80

41
42
43

1
2
3
4

RP81

39
40

CSN
INCN
UDN

RP76
ISCDROM
CD_IRQ
CDASPN
MODE1

CD_SIOR# 19
CD_SIOW# 19

CD_RSTDRV#
CDASPN

ISCDROM

PAVMODE

+5VCD

C420
.1UF

CD_SCS1# 19
CD_SCS3# 19

GND
GND
GND
GND
GND

G1

RB751V

C473
.1UF

+5VCD

GPIO[1]/VOL_UP
GPIO[0]/VOL_DN
MODE0
MODE1

D39

51

C419
.1UF

CD_SBA0 19
CD_SBA1 19
CD_SBA2 19

240K
2

S
S
S
G

D
D
D
D

8
7
6
5

C403

C109
.1UF

10UF_16V_1206
+5VCD
+5VCD

SI4425DY
C412
1

CD_PLAY

22K

DM_ON#

CD_PLAY 33

DM_ON#

30

Q19
DTC124EK

DM_ON 5
G2

DM_ON

30

D2

Q21
DTC124EK

DM_ON

22K

Q5B
SI1906DL

SUSP#
2
G1

Q5A
SI1906DL
1

22K
22K

R333
100K

R126
100K

SUSP#

10K

D1

28,32,36,40,41 SUSP#

R111

1UF_25V_0805

2
1

S1

+5VCD

CDA0
CDA1
CDA2

68
70
66

1M

C402
R330
1

HDA0
HDA1
HDA2

IDE_SDA0
IDE_SDA1
IDE_SDA2

IDE_SDA0
IDE_SDA1
IDE_SDA2

19

C404
10PF

CDD0
CDD1
CDD2
CDD3
CDD4
CDD5
CDD6
CDD7
CDD8
CDD9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15

17
17
17

8MHZ
R337

C440
.1UF

77
79
82
84
87
91
96
98
1
3
7
10
14
17
19
21

HDD0
HDD1
HDD2
HDD3
HDD4
HDD5
HDD6
HDD7
HDD8
HDD9
HDD10
HDD11
HDD12
HDD13
HDD14
HDD15

IDE_SDD[0..15] 17

U39
OZ165/OZ168

CDD0
CDD1
CDD2
CDD3
CDD4
CDD5
CDD6
CDD7
CDD8
CDD9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15

76
78
81
83
86
90
95
97
2
4
8
11
15
18
20
22

CDD[0..15] 19

IDE_SDD[0..15]

VDD

IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15

VDD

9
CDD[0..15]

CHB1608U301
1
2
L44
1
2
L45
CHB1608U301

+5VOZ

S2

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

TRANSFERRED FROM THE CUSTODY OF THE COMPETEN

Size
Document Number
Custom

Rev
2A

401207

Date:

, 18, 2004

Sheet

70

of

83

AC97 Codec
C498

DELAY

SENSE

ERROR

CNOISE

GND

ON/OFF#

Q34
2N7002

C410

1 1

LEFT

Q35
2N7002
input to AMPLIFY

1UF_25V_0805

.1UF

+VDDA

4.7UF_10V_0805
C502

C427

R_INT_CD_R

19 INT_CD_R

SI9182
.1UF

DM_ON

29 DM_ON

R431
22K

+5VAMP_PU
R432
10K
2
2

R_INT_CD_L

1 1

+3VS

3
Q42
2N7002

1UF_25V_0805

Q50
2N7002

R435
@10K

RIGHT

Q43
2N7002

C434

R_INT_CD_L

19 INT_CD_L

+VDDA

1 1

CDROM_L

Q45
2N7002

VOUT

VIN

1
2

C416
4.7UF_10V_0805

U35

+5VS

+5VS

C501
10UF_10V_1206

input to CS 4297A

+AVDD_AC97

R433
10K

CHB2012U170
+VDDC

DM_ON#

MIC1

22

MIC2

13

PHONE

12

PC_BEEP

XTL_IN

1
2
R345 @ 10K

IAC_SDATAI0 16

Y3
24.576MHz

R346
@ 1M

XTL_OUT

AFLT1

29

AFLT2

30

VREFOUT

28

REFFLT

27

FLT3D

32

BPCFG
FLTI
FLTO
NC
NC

31
33
34
43
44

NC
AGND
AGND

40
26
42

RESET#
SYNC

1
C445

2
1000PF NPO
1
2
C449
1000PF
NPO

C439
NPO
22PF

1
R379

C435
NPO
22PF

+AUD_VREF

SDATA_OUT
ID0#
ID1#

47

EAPD#

48

S/PDIF_OUT

GND
GND

C441 @ 1000PF
AGND

C428
1UF_0805

C106
1UF_0805

C444
.01UF

C448
.1UF

C455
1UF_25V_0805

C438

+AUD_VREF

1UF_25V_0805
L46
1
2
CHB2012U170
L41
1
2 AGND
CHB2012U170

ALC101/201

DGND

DGND

C461
4.7UF_10V_0805

AGND

R401

**

.1UF

CD_GNA

1
R402
6.8K

AGND

C460

CD_AGND

R430
0

Compal Electronics, Inc.

6.8K

Title

19

14.318MHz External
24.576MHz Crystal
or External Colck

R348
2 22

CD_GNA

21

SDATA_IN

IAC_BITCLK 14,16

22
2

19

R341
1

CD_R

CD_L

20

BIT_CLK

14

18

4
7

R338
@0

LIN_IN_R

45
46

MODE

VCC

24

No-Stuff

VCC

41

14,16 IAC_SDATAO

Stuff

38

39

HP_OUT_R

10

R740

25

HP_OUT_L

LIN_IN_L

14,16 IAC_SYNC

EAPD

AVCC

VIDEO_R

23

11

31

17

31

MD_MIC

1
100

VIDEO_L

CDROM_R

Q46
2N7002

31

RIGHT

2
R356

IAC_RST#

37

16

LEFT

RIGHT

MONO_IN

MONO_OUT

AUX_R

LEFT

31

2
R387
2
R376

MD_SPK

14,16

MIC

MIC

14

1
20K
1
20K

LINE_OUT_R

LINER

31

2
R390
2
R391

36

15

CDROM_R

LINEL

CDROM_L

1
2
C470
1UF_25V_0805
1
2
C465
1UF_25V_0805
CD_L_R 1
2
C464
1UF_25V_0805
CD_R_R 1
2
C467
1UF_25V_0805
CD_GNA 1
2
C471
1UF_25V_0805
1
2
C463
1UF_25V_0805
1
+AUD_VREF
2.4K
1
1
2
10K
C466
1UF_25V_0805

35

LINE_IN_R

LINE_OUT_L

AUX_L

31

.1UF

1
6.8K
1
6.8K
1
6.8K
1
6.8K

14

LINE_IN_L

2
R404
2
R394
2
R389
2
R392

C457

C432
1 1000PF
C436
2 1000PF
C431
2 4.7UF_10V_0805
C430
2 4.7UF_10V_0805
C411
2 1UF_25V_0805
C418
1 1000PF

31

1
6.8K
1
6.8K

AVCC

2
R405
2
R367

C429
10UF_1206
29 DM_ON#

U38

1 1

.1UF

10UF_1206

C443

3
Q47
2N7002

R434
@10K

+3VS

C459

1
2

1
2

.1UF

R_INT_CD_R

+VDDC

+AVDD_AC97
C426

+5VAMP_PU

L39

+VDDA

PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:

SCHEMATIC, M/B LA-1331

Document Number

Rev
2A

401207
, 18, 2004

Sheet

71

of

83

+5VCD

AMP & Audio Jack

+5VCD

Q48
INTSPK_R2 1
U42

.47UF_0603

C483

1
1

INTSPK_L2 1

DTC314TK

2 1

R428

10K

2
Q41

.47UF_0603

C497
4.7UF_10V_0805

10K

C488

.47UF_0603

33

33

JP20

TPA0132

.047UF_0805

@.1UF
JP16
INTSPK_R1
INTSPK_R2
INTSPK_L1
INTSPK_L2

30

LINE_IN_R

30

LINE_IN_L

FBM-11-160808-700T
1
2
L47
1
2
L48
FBM-11-160808-700T

1
2
3
4

LINE_IN JACK

3
6
2
1
C606

C511 .47UF_0603

DTC314TK

C499

2
2

DAN217

C601
PHONEJACK

330PF

17

C495

.47UF_0603

+5VCD

R427
C492

DTC314TK

C510
C476 .47UF_0603
1
2

1
100K

INTSPK_L1 1

1
12
13
24

R419 2.2K

R421
C490
4.7K
10UF_16V_1206

33

Q40

2
R425

RIGHT

U3-5
U3-23
U3-6
U3-20

NBA_PLUG
C505 1
2
.1UF
INTSPK_L2
INTSPK_R2

30

VOL_OP
INTSPK_L1
INTSPK_R1
1
2
C484 .47UF_0603
2

2
3
4
21
5
23
6
20

22
15
14
11
9
16
10
8
1

LEFT

PVDD SHUTDOWN#
PVDD
SE/BTL#
VDD
PC-BEEP
BYPASS
PC-ENABLE LOUTVOLUME
ROUTLOUT+
LIN
ROUT+
RIN
LLINEIN
RLINEIN
GND
LHPIN
GND
RHPIN
GND
GND
CLK

30

7
18
19

100K

R429

1
R416
1

+5VCD

R415
10K

10K

33

2.2K

1 2

R424

INTSPK_R1 1

R413

1
1

30

3
1

2
EAPD

3
2SB1188

DTC314TK

Q29
2N7002

4.7UF_10V_0805

Q49

EC_AMPPD# 33

10K

1
1

C480

2
@0

.1UF

1
R469

R414
1.65K
2

C468

2 Q39

**

SHUTDOWN#

W=40Mil

C482
@1000PF

VOL_AMP 32

D41

+5VCD

VOL_OP

U41

LM7111

R386
100K

330PF

ACES 85205-0400

JP23

1
R458
NBA_PLUG

+VDDA
C415
2

R380
10K

C477
10UF_16V_1206
+AVDD_AC97

+AVDD_AC97

1
2

Q44
2SC2411K

**

+3V

C516
1UF_10V_0603

R454

2.2K

2.2K

4
1

C451
2

R378

1UF_10V_0603
+3V POWER

560

30

JP21

R388
10K

1
2
L49
FBM-11-160808-700T

D33
RB751V

EXT.
MICPHONE
JACK

3
6
2
1
PHONEJACK

C629
220PF

MIC

MIC

ICH_SPKR

R465

U32B
74LVC14

14

R445
100K_1%

1
R440
18K_1%

R397
2.4K

Q32
2SC2411K

1UF_10V_0603 560

MONO_IN 30

1UF_10V_0603

R441
18K_1%
1

MONO_IN

R377

C454
2

C453
2

PCM_SPK#

17

330PF

+3V POWER

22

C635

560

.22UF_0603

C401

R303

1UF_10V_0603

+3V POWER

C392
2

SPEAKER OUT JACK

3
6
2
1

2
8.2K

330PF

1
R317

PHONEJACK

R375
10K

U32A
74LVC14

14

C493
150UF_6.3V_D2

L50
1
2 INTSPK_R1-3
FBM-11-160808-700T
1
2 INTSPK_L1-3
L51
FBM-11-160808-700T
C636

2
47
2
47

.1UF
U33B
74LVC125

INTSPK_L1 1

R316
100K

1
R463
1
R464

BEEP#

INTSPK_R1 1

32

+3V

2
1K

+3V

+ +

C500
150UF_6.3V_D2

COMPAL ELECTRONICS, INC

Title
PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

SCHEMATIC, M/B LA-1331

Document Number

Rev
2A

401207
, 18, 2004

Sheet
E

72

of

83

1
RB751V

D19

21

1394_PME#

22

PCM_PME#

+3VALW

27

WLANPME#

LAN_PME#

G_RST#
EC_SWI#

VGA_SUSP#

40

BATT_TEMPA

38

BATT_OVP

BATT_TEMPA
BATT_TEMPB

ALI/MH#
BATT_CHGI
ADP_I

D12
1

16 ICH_WAKE_UP#

23
18

40

18,34
ON/OFF
16 PM_SLP_S5#

RB717F

ECAGND

EC_SMI#

VBATTB
RB717F
D21

20

18

13,16 PM_SLP_S1#

R240 10K

D20

**

PACIN
RING#

RB751V
2

OEM
OEM
PCI_PME#
14
31
38
34

BATT_TEMPA
2
.01UF
BATT_TEMPB
2
.01UF

1
C386
1
C387

+3VALW
RP16
1
2
3
4

DAC_BRIG
VOL_AMP
IREF
EN_DFAN
EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS

16,24 LPC_AD[0..3]

8P4R_10K

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
16,24 LPC_FRAME#
16,18 LPC_DRQ#0
16,18,22,24 INT_SERIRQ
34

1
R267

1
R226
1
R225

81
82
83
84

AD0
AD1
AD2
AD3

87
88
89
90
2
44

IOPE0AD4
IOPE1/AD5
IOPE2/AD6
IOPE3/AD7
IOPE4/SWIN
IOPE5/EXWINT40

93
94

DP/AD8
DN/AD9

99
100
101
102

DA0
DA1
DA2
DA3

105
106
107
108
109

TINT#
TCK
TDO
TDI
TMS

15
14
13
10

LAD0
LAD1
LAD2
LAD3

18

EC_SMC2
2
4.7K
EC_SMD2
2
4.7K

@0

9
8
7

51RST# 19
22
23
24
25

EC_RST#

34
LPCPD#
16,18,22,24,27,28 PM_CLKRUN#

+5VALW

IOPJ2/BST0
IOPJ3/BST1
IOPJ4/BST2
IOPJ5/PFS#
IOPJ6/PLI
IOPJ7/BRKL_RSTO#

95

34
45
123
136
157
166

161
VBAT

IOPL0/A16
IOPL1/A17
IOPL2/A18
IOPL3/A19
IOPL4/WR1#

113
112
104
103
48

KBA16
KBA17
KBA18
KBA19

IOPI0/D0
IOPI1/D1
IOPI2/D2
IOPI3/D3
IOPI4/D4
IOPI5/D5
IOPI6/D6
IOPI7/D7

138
139
140
141
144
145
146
147

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

IOPJ0/RD#
IOPJ1/WR0#

150
151

FR D#

SELIO#

152

SELIO#

SEL0#
SEL1#

173
174

FSEL#

IOPM0/D8
IOPM1/D9
IOPM2/D10
IOPM3/D11
IOPM4/D12
IOPM5/D13
IOPM6/D14
IOPM7/D15

148
149
155
156
3
4
27
28

SYSON
SUSP#
MMO_ON

PSCLK1/IOPF0
PSDAT1/IOPF1
PSCLK2/IOPF2
PSDAT2/IOPF3
PSCLK3/IOPF4
PSDAT3/IOPF5
PSCLK4/IOPF6
PSDAT4/IOPF7

110
111
114
115
116
117
118
119

KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA
TP_CLK
TP_DATA

KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

71
72
73
74
77
78
79
80

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15

49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

32KX1/32KCLKOUT

158

C RY1

32KX2

160

C RY2

LPC_AD[0..3]

G_RST#
FR D#
SELIO#
FSEL#

8
7
6
5

62
63
69
70
75
76

KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15

EC_SCI#

G20
RCL#

31
5
6
18

13 CLK_LPC_EC

LREST#
SMI#
PWUREQ#
IOPE6/LPCPD#/EXWIN45
IOPE7/CLKRUN#/EXWINT46
IOPD3/ECSCI#
GA20/IOPB5
KBRST#/IOPB6
LCLK

CLK

1
C350

2
1
@22PFR281

2
@33

1
R236

MMO_ON
FRD#
FWR#

33
33

SELIO#

33

FSEL#

33

SYSON
SUSP#

36,41
28,29,36,40,41

2
10K

+3VS

VR_ON

D22

RB751V

2
R255

1
10K

ATFOUT# 1

D24

42

ATF_INT# 16

RB751V

+3VALW

EC_RSMRST# 35
CK408_PWRGD# 13,35
ENVEE
14
ENBKL
14

ENVEE
ENBKL

KBA0
KBA1

1
R120
1
R121

2
@1K
2
1K

R122
1
R123

@1K
2
1K

R124
1
R125

@1K
2
1K

KBA2
TP_CLK
TP_DATA
LID_SW#
CDON#

14
14
34
34

KBA3
KBA4

KBA5

I/O Address
Index

BADDR1(KBA3) BADDR0(KBA2)

Data

2E

2F

4E

4F

(HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1

Reserved

R241
C RY1

2
20M

X1

47

PC87591VPC
L36

ECAGND

38

+3V

LFRAME#
LDRQ#
SERIRQ

FSTCHG

SM/SD_PME#

NUM_LED#
CAPS_LED#
PADS_LED#

IOPD0/RI1#/EXWINT20
IOPD1/RI2#/EXWINT21
IOPD2/EXWINT24
IOPD4
IOPD5
IOPD6
IOPD7

PC7

143
142
135
134
130
129
121
120

11
12
20
21
85
86
91
92
97
98

28

RB751V
2

34
34
34

26
29
30
SCR_LED# 41
42
54
55

PCI_PME#
ATFOUT#

MP3#
PC7

34,37,38,39 PACIN
28
RING#
13,16 PM_SLP_S3#

RCL#

IOPC0
IOPC1/SCL2
IOPC2/SDA2
IOPC3/TA1
IOPC4/TB1/EXWINT22
IOPC5/TA2
IOPC6/TB2/EXWINT23
IOPC7/CLKOUT

IOPK0/A8
IOPK1/A9
IOPK2/A10
IOPK3/A11
IOPK4/A12
IOPK5/A13/BE0
IOPK6/A14/BE1
IOPK7/A15/CBRD

KBA[0..18]
ADB[0..7]
KSI[0..7]
KSO[0..15]

KBA[0..18]
ADB[0..7]
KSI[0..7]
KSO[0..15]

C RY2

G20

168
169
170
171
172
175
176
1

EC_SMC2
EC_SMD2

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7

ENV0 (KBA0)
IRE
R242
* OBD
120K_0603
DEV
PROG

IOPB0/URXD
IOPB1/UTXD
IOPB2/USCLK
IOPB3/SCL1
IOPB4/SDA1
IOPB7/RING#/PFAIL#

124
125
126
127
128
131
132
133

32.768KHZ
C280
10PF

153
154
162
163
164
165

IOPH0/A0/ENV0
IOPH1/A1/ENV1
IOPH2/A2/BADDR0
IOPH3/A3/BADDR1
IOPH4/A4/TRIS
IOPH5/A5/SHBM
IOPH6/A6
IOPH7/A7

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10

34
34

D26

R257
10K

RC#

EC_URXD
EC_UTXD
EC_USCLK
EC_SMC1
EC_SMD1

EC_URXD
EC_UTXD
EN_WOL#
EC_SMC1
EC_SMD1
LPC_RST#

18
PBTN_OUT#
5,29
EC_SMC2
5,29
EC_SMD2
34 FAN_SPEED

RB751V
D25
16

PCM_SUSP#

IOPA0/PWM0
IOPA1/PWM1
IOPA2/PWM2
IOPA3/PWM3
IOPA4/PWM4
IOPA5/PWM5
IOPA6/PWM6
IOPA7/PWM7

33
33
14
14

11
11
11,27
33,40
33,40
24

+3VS

GATEA20

32
33
36
37
38
39
40
43

For PWM EN_DFAN

KSO16
KSO17

16

U30

INVT_PWM

INVT_PWM
BEEP#

38
ACOFF
16 PM_BATLOW#
34
EC_ON
18 EC_LID_OUT#

.1UF
ECAGND

R266
10K

.1UF

AGND

L35
1
2
CHB1608U800
C372

+EC_AVCC +RTCVCC

AVCC

14
31

+3VALW

C38

16

**
2

C282

1000PF 1000PF

C72

96

1
2

1
2

.1UF

.1UF

+EC_AVCC

C279

C91

+3VALW
51VDD

GND1
GND2
GND3
GND4
GND5
GND6
GND7

+RTCVCC

.1UF

**

17
35
46
122
137
159
167

C318

.1UF

C281

.1UF

C278

+3VS

2
@0
2
0

VDD

+3VALW

1
R64
1
R60

+3VALW

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6

C259
12PF

0
0
1
1

ENV1 (KBA1)

TRIS (KBA4)
0
0
0
0

0
1
0
1

SHBM(KBA5)=1: Enable shared memory with host BIOS

TRIS(KBA4)=1: While in IRE and OBD, float all the
signals for clip-on ISE use

COMPAL ELECTRONICS, INC

1
2
CHB1608U800
Title

PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
3

SCHEMATIC, M/B LA-1331

Document Number

Rev
2A

401207
, 18, 2004

Sheet
1

73

of

83

+3VALW
C239

+5VALW

+3VALW

19 SHDD_LED#
19 PHDD_LED#
19,24
DRV0#
23
OCCB#
+3VALW

SELIO#

SELIO#

20

8P4R_100K

2
.1UF

KBA2

SELIO#

U20A
74LVC32

74LVC244

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

3
4
7
8
13
14
17
18

D0
D1
D2
D3
D4
D5
D6
D7

AA
LARST#

11
1

CLK
CLR

CC

R244
+5VALW

EXTIDEPWR# 19
MDC_DN# 14

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

CD_PLAY 29
HDD_LED# 34
2ND_CHGI_CD_FDD_LED# 34

74HCT273

C263

U22
2
5
6
9
12
15
16
19

VCC

C220

+3VALW

1G
2G

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

32

KBA1

1
19

18
16
14
12
9
7
5
3

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

10

14

U20B
74LVC32

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

8
7
6
5

10

PCM_LED

2
4
6
8
11
13
15
17

VCC

BUTTON1#
INTERNET#
CD_INTA#

1
2
3
4

GND

34
34
29

RP11
DD
AA
BB
CC

GND

20

.1UF
U26

.1UF
C225

14

20K

R229

1UF_25V_0805

100K

D11

1
0_0402

+3VALW

KBA3

12

SELIO#

13

1G
2G

VCC

1
19

11

2
.1UF

20

18
16
14
12
9
7
5
3

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

10

14

U20D
74LVC32

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

C219

DAN202U

.1UF
U27

20
HOT#

29 MEDIA_DETECT
34
VOL_UP#
34
VOL_DW#
27,34 KILL_SW

2
4
6
8
11
13
15
17

+5VALW

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

+3VALW

KBA4

U20C
74LVC32

9
8

SELIO#

GND

EXTID0
EXTID1
EXTID2

PCM_LED

C240

19
19
19

10

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

3
4
7
8
13
14
17
18

D0
D1
D2
D3
D4
D5
D6
D7

BB
LARST#

11
1

CLK
CLR

74LVC244

U21
2
5
6
9
12
15
16
19

VCC

+3VALW

22 PCM2_LED

PWR_LED# 34
2nd_BATT_LOW_LED# 34
BATT_LOW_LED# 34
BATT_CHGI_LED# 34
WL_OFF# 27
CD_STOPBTN# 29
PCMRST# 23
EC_AMPPD# 31

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND

1
@0_0402

22 PCM1_LED

10

2
R276

THRM#

HOT#

14

2
R277

PROCHOT#

**
74HCT273

DD

BOARD ID

7SH32FU

C121
1
2

R18

U25
4

**

+3VALW

1
R149
1
R147
FLASH_VCC

2
@0
2
0

1 R16
1
1
R19
1
R20
2
R17
2
R21

2 100K
2 @100K
B ID
2
@100K
2
100K
1
100K
1
@100K

KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4

32
32

KBA[0..18]
ADB[0..7]

A11
A9
A8
A13
A14
A17
WE#
VCC
A18
A16
A15
A12
A7
A6
A5
A4

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3

@SST39VF040_TSOP
KBA[0..18]
ADB[0..7]

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

2
4

U40
7SH32FU

Q33
3

2N7002

R190

R198

.1UF

4.7K

4.7K

8
7
6
5

R188
100K

U16
EC_FLASH# 17
FWR#

32

32,40
32,40

EC_SMC1
EC_SMD1

VCC
WC
SCL
SDA

2
G
1

+12VS

FWE#

2
100K

R417
R381
100K

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

A0
A1
A2
GND

1
2
3
4

NM24C16

R181
100K

74LVC244

1
C128

+3VALW

2
.1UF

U14

U11

U12

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

18
16
14
12
9
7
5
3

+5VALW

.1UF
KBA11
KBA9
KBA8
KBA13
KBA14
KBA17
FWE#

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

2
.1UF

1G
2G

1
C474

1
19

2
.1UF
U19

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

C215

5
2

SELIO#

.1UF

KBA5

2
4
6
8
11
13
15
17

+5VALW

C249

MP3_STOPBTN#
MP3_PLAYBTN#
MP3_FRDBTN#
MP3_REVBTN#

34 MP3_STOPBTN#
34 MP3_PLAYBTN#
34 MP3_FRDBTN#
34 MP3_REVBTN#
29,34 STOPBTN#

+5VALW +5VALW

+3VALW

+3VALW +3VALW

C229

0
1
0
0

20

0
0
1
0

VCC

0
0
0
1

+5VALW
+3VALW

2A4

GND

0.1
0.2
0.3
1.0

2A3

10

REV 2A2

FR D#
KBA10
FSEL#
ADB7
ADB6
ADB5
ADB4
ADB3
ADB2
ADB1
ADB0
KBA0
KBA1
KBA2
KBA3

FRD#

32

FSEL#

32

KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1
KBA0
ADB0
ADB1
ADB2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS

VCC
WE*
A17
A14
A13
A8
A9
A11
OE*
A10
CE*
DQ7
DQ6
DQ5
DQ4
DQ3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

FWE#
KBA17
KBA14
KBA13
KBA8
KBA9
KBA11
FR D#
KBA10
FSEL#
ADB7
ADB6
ADB5
ADB4
ADB3

KBA11
KBA9
KBA8
KBA13
KBA14
KBA17
FWE#

FLASH_VCC

FLASH_VCC

KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

A11
A9
A8
A13
A14
A17
WE#
VCC
A18
A16
A15
A12
A7
A6
A5
A4

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

FR D#
KBA10
FSEL#
ADB7
ADB6
ADB5
ADB4
ADB3
ADB2
ADB1
ADB0
KBA0
KBA1
KBA2
KBA3

COMPAL ELECTRONICS, INC

@29F040_TSOP
Title
29F040/SST39VF040_PLCC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

Size
B

Document Number

Date:

, 18, 2004

TRANSFERRED FROM THE CUSTODY OF T

Rev
2A

401207
Sheet

74

of

83

+3VS

1
2
3
4

+3VALW

MP3_STOPBTN#
MP3_PLAYBTN#
MP3_FRDBTN#
MP3_REVBTN#

8
7
6
5

+3VALW

RP8

8P4R_10K

R74
R245

33 MP3_FRDBTN#

470K

EC_RST#

2
PC7

33 MP3_STOPBTN#

Q20
@2N7002

33 MP3_PLAYBTN#

32

33 MP3_REVBTN#

EC_RST# 32

@470K

7,14,16,19,20,21,22,23,24,27,28 PCIRST#

U23
@7SH08FU

1
4

LPCPD#

LPCPD#

MP3_REVBTN#

2
D28

1
RB751V

REVBTN#

MP3_STOPBTN#

2
D30

1
RB751V

STOPBTN#

MP3_PLAYBTN#

2
D31

1
RB751V

PLAYBTN#

27,33 KILL_SW
32 PADS_LED#
33
INTERNET#
33
VOL_DW#
32,37,38,39 PACIN
33 BATT_LOW_LED#
33
HDD_LED#
32
CDON#
29
FRDBTN#
29,33 STOPBTN#

32

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

**

For PC87591 REV 0.A Only

FRDBTN#

JP6

LPCPD#
R219

1
RB751V

18,32
ON/OFF
32
EC_ON
33 2nd_BATT_LOW_LED#

14,16,24 SUS_STAT#

2
D29

+3VALW

2
@.1UF
5

1
C243

MP3_FRDBTN#

FRDBTN#
STOPBTN#

+5VALW

1
2

C638
1000PF

+3V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

51ON#
37
LID_SW# 32
MP3#
32
SM_LED 28
CAPS_LED# 32
NUM_LED# 32
BUTTON1# 33
VOL_UP# 33
PWR_LED# 33
BATT_CHGI_LED# 33
2ND_CHGI_CD_FDD_LED# 33

SMLED

REVBTN#
PLAYBTN#

REVBTN# 29
PLAYBTN# 29
C

+3VALW
+3VS

SUYIN-80065A-040G2T
C639
1000PF

FAN CONN.
+5V

+12V

R355

EN_DFAN

EN_DFAN

U36

1
4
2

3
VEE LMV321_SOT23-5

1
2

JP10
D38
1N4148

1
2
3
53398-0310-FAN

+3V

1
R347
13K_1%

+5VFAN
.1UF

Q30
2SA1036K

32

1N4148

@10UF_16V_1206

1SS355

VCC

2
.1UF

C409

D35

E
C446

1
C422

.1UF

D40

Q28
FMMT619

2
B

+5V
C421

3.6K

1
R342
7.32K_1%

R132

10K
32

FAN_SPEED

COMPAL ELECTRONICS, INC

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE

SCHEMATIC, M/B LA-1331

Size
B

Document Number

Date:

, 18, 2004

TRANSFERRED FROM THE CUSTODY OF

Rev
2A

401207
Sheet
1

75

of

83

RTC Batt. Connector

W=30mils

@.1UF

GND

EC_RSMRST# 32
1

U32D

74LVC14
C388

1
R92

2
@0

PM_RSMRST# 16

74LVC14

R52
10K

GND

CHGRTC

+3V
C105
.1UF

Place near ICH3-M

2
20K

11

10

14

+3V
U32F
74LVC14

13

12

+3V

PM_PWROK 16

C107
1UF_0805_X7R

1
R297

U32E
74LVC14

VGATE

+3V

42

U33C
74LVC125

10

R98
10K

14

W=30mils

U32C

1
R48

+3V

1
@1M

2
R300

+3V

D44
HSM1265

*
1

**

+RTCVCC

R301
@150K

14

RTCBATT

14

.1UF

Power ON Circuit
+3V

+RTC_BATT
C111
1
1
2

BATT1

+3V
H8

ST2

ST3

ST4

H2

R95
10K

U33D
74LVC125

13

ST1

Screw Boss 070

Stand-Off 115

Stand-Off 053

Stand-Off 053

H27

11

Stand-Off 053

Stand-Off 090

H10

1
R96

ICH_VGATE 16

+3V
+3VS

H9

H12

12

R93

CK408_PWRGD# 13,32
Q4

2
1

H26

L Screw Hold

M Screw Hold

N Screw Hold

O Screw Hold

O Screw Hold

O Screw Hold

O Screw Hold

O Screw Hold

O Screw Hold

FD1
FIDUCAL

FD2
FIDUCAL

FD3
FIDUCAL

FD5
FIDUCAL

FD4
FIDUCAL

CF10
CF6
CF7
CF8
CF2
CF4
CF17
CF19
CF18
CF12
SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80

H19

H21

H17

H7

H13

H14

H24

CF5
CF1
CF3
CF9
SMD40M80 SMD40M80 SMD40M80 SMD40M80

M Fixed Position Hold

I Fixed Position Hold F Fixed Position Hold

H11

CF11
CF16
CF14
CF13
CF15
SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80

I Screw Hold

3904

100PF

G Screw Hold

C95

F Screw Hold

H22

H5

D Screw Hold

2
100K

C Screw Hold

H20

1
R97

A Screw Hold

J CPU Thermal Plane Screw Hold

H29

H4

H1

H23

H28

J CPU Thermal Plane Screw Hold

H3

J CPU Thermal Plane Screw Hold

J CPU Thermal Plane Screw Hold

10K

FD6
FIDUCAL

H6

H16

H15

H25

COMPAL ELECTRONICS, INC

Title

SCHEMATIC, M/B LA-1331

E HDD Frame Hold

E HDD Frame Hold

E HDD Frame Hold

PROPRIETARY NOTE

E HDD Frame Hold

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
Document Number
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
Custom401207
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
, 18, 2004
C

Rev
2A
Sheet
E

76

of

83

+1.8VALW To +1.8VS Transfer

+1.8VALW

+1.8VS
U2

SUSP# 5
G2

28,29,32,40,41 SUSP#

1
2

10UF_16V_1206

1
R195

R461
470

10UF_16V_1206

+5VALW To +5VS Transfer

3
4
8
1

Q13
2N7002

4.7UF_10V_0805

.1UF

4.7UF_25V_1206

C613
4.7UF_25V_1206

+5VS

C614

C615

R453
470

4.7UF_25V_1206

SI4702DY

R459
1K

2N7002

330K

+12VALW To +12VS Transfer

SYSON# 2
G
SUSP

SUSP
3

C519
.01UF

2N7002
2
G

Q54
2N7002

2
G

Q55
2N7002
3

1 2

1
Q2

R443

+5VS_GATE

.01UF

C588
4.7UF_10V_0805

SYSON#

Q51
2
G

D
C621

ON_GATE
1

SYSON#

SI4702DY

C602

+5V
C605

SUSP

S2
S2
VHV
S1
VON/OFF

1UF_25V_0805

VIN
VIN
VIN

7
6
5

C608

C618
4.7UF_10V_0805

2
G

+5V & +5VS Discharge

3
4
8
1

S2
S2
VHV
S1
VON/OFF

SUSP
Q57
2N7002

+5VS

U46

4.7UF_10V_0805

VIN
VIN
VIN

7
6
5

C589

+5VALW

U47

+5V

+5VALW

SYSON# 2
G

R194
1M

C18
.1UF

+12V

R173
1K

.01UF

2
100K

+3VS

C189

1 2

+5VS_GATE

+5VALW To +5V Transfer

1
2

+12VALW

R447
100K

R448
1M

10UF_16V_1206

C210

SI4702DY

C242
4.7UF_10V_0805

1
2

10UF_16V_1206

C2

C216

C596

+3V
C200

ON_GATE
1

SYSON#

3
4
8
1

SI4702DY

S2
S2
VHV
S1
VON/OFF

1UF_25V_0805

VIN
VIN
VIN

7
6
5

C619
SUSP

4.7UF_10V_0805

+3V & +3VS Discharge

1UF_10V_0603

C609

S2
S2
VHV
S1
VON/OFF

Q18B
SI1906DL

+3VS

U17

3
4
8
1

VIN
VIN
VIN

7
6
5

+3VALW

S2

+3V

SUSP

Q18A
SI1906DL

S1

41

G1

U48

C598
4.7UF_10V_0805

SYSON#

+3VALW To +3VS Transfer

+3VALW

2
6

2
1

SYSON

Q17
2N7002

+3VALW To +3V Transfer

4.7K

SYSON#

D2

32,41

2
G

R199

10K

1K

SUSP

R193

R11

+5VS_GATE

+3VALW

C16
C9
C17
1UF_10V_0603 4.7UF_10V_0805 4.7UF_10V_0805
2

SI4800
C14
4.7UF_10V_0805

1
2
3
4

S
S
S
G

D1

+3VALW

D
D
D
D

8
7
6
5

+12V & +12VS Discharge

+12VALW To +12V Transfer

C166
1UF_25V_0805

R460

SYSON# 2
G

Q58
2N7002

1K
1 2

1 2
3

C623
1UF_25V_0805

1K

1
2

SUSP# 2
Q52 G
2N7002

+12VS

R462

+12VS

1
2

Q10
2N7002

1
R456
51K
1 2

1
1 2
3

1
2

+12V

1UF_25V_0805

Q53
NDS352P

2
G
C167

1
2
3

1UF_25V_0805

+12V

SYSON

C628

R160
47K

R455
100K

.1UF_25V_0805

Q9
NDS352P

C627

.1UF_25V_0805

C169

R161
100K

C173

+12VALW

+12VALW

+12VALW

+12VALW

SUSP 2
G

Q56
2N7002

COMPAL ELECTRONICS, INC

1000PF

Title

SCHEMATIC, M/B LA-1331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
Document Number
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
Custom
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
, 18, 2004
A

Rev
2A

401207
Sheet
E

77

of

83

VS

VIN

VIN

PR1
1M_1%

PU1A

PR5
22K

PC6
0.1UF_50V

PR6
20K_1%

PC5
1000PF_50V

PC4
100PF_50V

PZD1
RLZ4.3B

PC3
1000PF_50V

ACIN

17

PACIN

32,34,38,39

PR7
10K

Vin Detector

High 18.764 17.901 17.063

Low 17.745 16.903 16.038

RTCVREF

1
PR8
10K

PC2
100PF_50V

PC1
1000PF_50V

PACIN

PD1
EC10QS04

2
2DC-S026B201 2.5D 5P

LM393M

3
3

PR4
1K

10K

PR2

PR3
84.5K_1%

PCN1

VS

PL1
CHC4532U800_1812

PF1
@7A 32V UL/CSA FAST
1

2
1

Build 0 ohm for ACL10

3.3V

VIN

VSB

PD2
RB751V
PD3
RLS4148

BATT+

PR9
1K_1206

PD4
RB751V

1
PR10

**

33_1206

VS

VIN

PQ1
TP0610T
3
1

PR162
200_0805

PR11
1K_1206

PC7
0.22UF_1206_25V

PC8
0.1UF_0805_25V

PR12
100K

B+

PR13
1K_1206

CHGRTCP

PD5
RLS4148
2
1

3.3V
PZD3
RLZ6.2C

PC12
1UF_0805_25V

PZD4
RLZ16B

PR23
47K

(6A,240mils ,Via NO.= 12)

+1.5VS

(2A,80mils ,Via NO.= 4)

+1.25VSP

PAD-OPEN 3x3m

+1.25VS

PAD-OPEN 3x3m

PJP4

(3A,120mils ,Via NO.= 6)

Precharge detector
15.34
15.90
16.48
13.13
13.71
14.20

PQ3
DTC115EUA

+1.8VALW

(3A,120mils ,Via NO.= 6)

+12VALW

(120mA,20mils ,Via NO.= 1)

100K

+1.8VALWP

PACIN

+5VALWP

100K

PAD-OPEN 3x3m
PJP5

+2.5V

2
G
3

+1.5VSP

PQ2
2N7002

PJP3

3.3V

PJP2

RTCVREF

+2.5VP

PC9
1000PF

PR19
499K_1%
PR21
215K_1%

PC13
10UF_1206_10V

PR22
200

PR20
10K

CHGRTC

PC10
1000PF

RB715F

200_0805

S-81233SG (SOT-89)

PR17
499K_1%

ACON

38

PU1B
LM393M

PD6

1
3

PR18

PU2

PC11
0.1UF_16V

RTCVREF

PR16
1M_1%

6.0V

39,40 MAINPWON

PR15
10K
VS

2
PR14
22K

51ON#

34

PAD-OPEN 3x3m
PJP6
4

+12VALWP

PJP7

+1.2VPP

PAD-OPEN 2x2m
PJP8
+5VALWP

+5VALW

(5A,200mils ,Via NO.= 10)

+1.2VP

(300mA,40mils ,Via NO.= 2)

COMPAL ELECTRONICS, INC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY

OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
Size
Document Number
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
B
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
Date: , 18, 2004

PAD-OPEN 3x3m
PJP9
+3VALWP

1
PAD-OPEN 2x2m

+3VALW

SCHEMATIC, M/B LA-1331

(5A,200mils ,Via NO.= 10)

PAD-OPEN 3x3m
A

Rev

401207

2A
Sheet

78

of

83

8
7
6
5

PL3
FBM-L11-453215-900LMAT_1812
1
2

PQ6
SI4835DY

4.7UF_1210_25V

ACOFF#

1
PU3
MB3878

-INC2

+INC2

24

OUTC2 GND

23

PC16
220PF_50V

+INE2

CS

22

-INE2 VCC(o)

21

FB2

OUT

20

VREF

VH

19

FB1

VCC

18

2
PQ9
2N7002

VIN

3
2
1

PR28 47K

4
PQ7
SI4835DY

100K

ACOFF

32

PC21
0.1UF_16V

PC22
2200PF_50V

2
PR36
10K

PR38
162K_1%
1
2
PR40 10K
2
1

PC25
0.1UF_16V

+INE1

RT
-INE3

17

16

10

OUTC1

FB3

15

11

OUTD

CTL

14

12

-INC1

+INC1

13

2
PR37
68K

2
PR41
47K

CC=0.5~2.52A
CV=16.84V(8 CELLS LI-ION)

32

PL4
22UH_SPC-1205P-220A
1
2
1

PD8
1SS355

PC24
1500PF_50V

PR42
100K_1%

IREF=1.31*Icharge
IREF=0.73~3.3V

BATT+

PR39
0.02_2512_1%

PD9
RB051L-40

PR43
47K

IREF

-INE1

FSTCHG

5
6
7
8
LXCHRG

PC23
0.1UF_0805_25V
1
2

PC19
PR35
4700PF_50V 10K

PC17
0.1UF_0805_25V
PC20
0.1UF_50V
1
2

PC27
4.7UF_1210_25V
2
1

PQ8
DTC115EK

PC26
4.7UF_1210_25V
2
1

PR34
10K_1%

PC18
0.1UF_16V

100K

PR33
21K_1%

ACON

32

2
G
3

1
PR31
10K

32,34,37,39 PACIN

PR32
10K

PR27 10K

PR30
150K

PR29
0

1
PD7
1SS355
ACOFF# 1

37

8
7
6
5
4

4.7UF_1210_25V

PC15

PR26
200K

PR25
10K

PC14

1
2
3

1
2
3

B++

B+
PR24
0.02_2512_1%

1
2
3
1

Iadp=0~3.5A

P3
PQ5
SI4835DY

8
7
6
5

VIN

P2
PQ4
SI4835DY

1
PR44
47.5K_1%

1
PR45
143K_1%

4.2V

VMB

VS

PR46
340K_1%

8 CELL : 18V--> BATT_OVP= 2.0V

+SDREF

+2.5V
1

OVP voltage : LI-MH

PC28
0.1UF_50V

PR47
499K_1%

PR49
0

2.2K

PC32
0.01UF

PR52
105K_0.5%

PC31
@0.1UF_16V

PC30
10UF_1206

1
1

PR51

PC29
0.1UF_16V

PR50
100K_0.5%

PR48
100K_0.5%
PU4B
LM358

32 BATT_OVP

PU4A
LM358

(BAT_OVP=0.1111 *VMB)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY

OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
A

COMPAL ELECTRONICS, INC

Title

SCHEMATIC, M/B LA-1331

Size

Document Number

B
Date:

Rev

401207
, 18, 2004

2A
Sheet

79

of

83

PC33
2.2UF_1206_25V
1
2

1
2

2
3

5
6
7
8

PC40
4.7UF_1210_25V

5
6
7
8

2
1

1
2

VL

PD13
EP10QY03

SPOK

10K_1%

PR73

PR75

+
PC53
100PF

PR71
10K

3
2
1
PR67
0

PR72
47K

1
PR68
10.5K_1%

2
PR66
@0

680PF

1
2

2
1

VL

PR70
10K_1%

+5VALWP
PC50

VS

+5VALWP
PC49
4.7UF_1206_10V
PC52
150UF_D_6.3V_KO

RUN/ON3

TIME/ON5

28

2.5VREF

PR62
0.012_2512_1%

PC51
150UF_D_6.3V_KO

MAX1632

PR61
2M

CSH3
CSL3
FB3
SKIP#
SHDN#

CSH5

3
2
1

1
2
3
10
23

PC45
47PF

PLX5

LX3
DL3

PQ13
SI4810DY

PDL5

PU5

VL

V+

DH3

26
24

4
5
18
16
17
19
20
14
13
12
15
9
6
11

GND

PC48
100PF

PR63
10K
PR65
@300K

27

PDH51

2
PR58
0

12OUT
VDD
BST5
DH5
LX5
DL5
PGND
CSH5
CSL5
FB5
SEQ
REF
SYNC
RST#

PT1
SDT-1205P-100

21

22
2

BST3

3.57K_1%

PR64

PD12
EP10QY03

FLYBACK

PDH5

1
2
3
1

32,34,37,38 PACIN

25

PC39
4.7UF_1210_25V

PC41
4.7UF_1206_10V

1
2

PR57
0

2
2
1

CSH3

PC47

150UF_D_6.3V_KO
2
1

PC46
150UF_D_6.3V_KO
2
1

PR59
1M

PQ11
SI4800DY

+12VALWP

PC43
4.7UF_1210_25V

PDL3

B+++

2
PC42
0.1UF_0805_25V

8
7
6
5
1
1
2

VL

PR56
10_1206

1
2
3

PLX3

PQ12
SI4810DY
47PF
PC44

PD11

PDH31 1

PDH3

PL6
SLF12565T-100M

PD10
EC11FS2

8
7
6
5
4

+3VALWP

PR53
22_1206
SNB 2

PC38
0.1UF_0805_25V
1
2

DAP202U

VS
PR54
0

PC37
4.7UF_1210_25V

PQ10
SI4800DY

PR55
0

PR60
0.012_2512_1%

BST51

BST31

B+++

FBM-L11-322513-151LMAT
PL5
2
1

PC36
4.7UF_1210_25V

B+

PC35
0.1UF_0805_25V

PC34
470PF_0805_100V

0.047UF_16V

40

SPOK

+5V Ipeak = 6.66A ~ 10A

MAINPWON 37,40

+3.3V Ipeak = 6.66A ~ 10A

47K_1%

PC56

PC57
0.047UF_16V

COMPAL ELECTRONICS, INC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY

OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
Size
Document Number
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
B
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
Date: , 18, 2004

SCHEMATIC, M/B LA-1331

Rev

401207

2A
Sheet

80

of

83

PF2
7A 24V UL/CSA FAST

PR76
1K

2
1

PR78
47K
PR77
1K

+3VALWP

VL

**
PH1
10K_1%

PC60
0.1UF_50V

ALI/MH#

TM_REF1

PD15
@BAS40-04

**

1
1SS355

VL
PR86
100K_1%

**

PU6A
LM393M

PC61
1000PF_50V

**
3

PC62
0.22UF_0805_16V

PR81
3K_1%

PD33

+3VALWP

PR85
1K

**
1

PR83
16.9K_1%

32

PR163
47K_1%

**

PR82
47K_1%

PD14
@BAS40-04

PR84
25.5K_1%
2

VL

VS

3
1

PC59
0.01UF_50V

PR80
100

SUYIN 25063A-07G1-E 7P P2.5

PH1 under CPU botten side :

CPU thermal protection at 87 degree C
Recovery at 48 degree C

BATT+

1
PR79
100

PL7
BLM41P600S_1806
2
1

ALI/NIMH#
AB/I
TSA

**
VMB

PJP10

1
2
3
4
5
6
7

PC58
1000PF_50V

37,39

BATT_TEMPA 32

PQ45
DTC115EK

EC_SMC1 32,33

100K

PH2 near main Battery CONN :

BAT. thermal protection at 73 degree C
Recovery at 50 degree C

100K

**

PD17
@BAS40-04

PD16
@BAS40-04

PR87
100K_1%

EC_SMD1 32,33
EC_SMC1

EC_SMD1

MAINPWON

**

+5VALWP
VL
VL

**

VIN

**
2

PD18

PH2
10K_1%

+12VALWP

PR89
47K_1%

PD19
1SS355
SBAT_VCC

PR91
6.2K

1
PR96

SBAT_CON_2P

39

SPOK

SPOK

2
1

PQ16
DTC115EK

28,29,32,36,41 SUSP#

SUSP# 2

**

B+

100K

PD34

PU6B
LM393M

1
1SS355

VL
PR94

100K_1%

PR95
100K_1%

EC10QS04
100K

PD21

100K

**
PR88
3.24K_1%

PQ15
DTC115EK

PC64 1000PF_50V

PQ14
IRLML5103

EC10QS04

1
2

**

PR92
100K

4.7K

PC65
0.22UF_0805_16V

TM_REF2

PR93

PD20

**

PR90
10K_1%

1SS355

PJP11

PR164
47K_1%

VSB

100K

COMPAL ELECTRONICS, INC

100K

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY

OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
Size
Document Number
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
B
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
Date: , 18, 2004

SCHEMATIC, M/B LA-1331

Rev

401207

2A
Sheet

81

of

83

+2.5VP
D
PQ17
@SI3445DV
+2.5VP
PL8

1
PC66
0.1UF_0805_25V

1
VCC2

16

PVDD1

PVDD2

15

VL1

VL2

14

PGND1

PGND2

13

AGND1

AGND2

12

PQ21
DTC115EUA

SD

VIN/2

VCCQ

10

+2.5VP

1
2

AGSEN

AGND

1
2

PC79
0.1UF_0805_25V

PR109
1K

PC78
1000PF

PC80
2

SUSP#

100K

100K

SYSON

11

100K

100K

VFB

VL

2
PR108
100K

PQ22
DTC115EUA

100K

Layout : "Compensation network close to FB pin"

PQ23
DTC115EUA

2
2

PU8B
LM393M
7

100K

PR106
100K

PR107

+2.5VP

PR105
200K

100K

PD25
@EP10QY03

1
4

PC77
1000PF

PC75
4.7UF_1206_16V

2.5VREF

1000PF
1

8
3

LX1.25

CM8500

PQ20
2SA1036K

PU7

PR104
@11.8K_1%

+1.25VSP

PL9
5UH_SPC_06704

PC73
4.7UF_1206_16V

2
3

PU8A
LM393M
1

PC68
0.1UF_0805_25V

PC76
220UF_D_4V_KO

1
2

PC72
@0.1UF_16V

VCC1

1.25VIN

VS
PC74
0.1UF_50V

1
2
2

PC67
@470P

PD23
RB051L-40

1
1

PR101
100

PC69
220UF_D_4V_KO

SPC-5R0M
PR100
@2M

PQ18
SI3445DV

PC71
2200PF

2
PR103
1K

1
1

PR102
10K

PQ19
HMBT2222A

PD22
RB751V

PC70
10UF_1206_10V
2
1

PR99
10

**

LX2.5

6
5
2
1

2.5VIN

PR98
0_1206

PR97
0_1206

+2.5V +-5%

6
5
2
1

+5VALWP

5.1K

PR113
0

PQ27
DTC115EK

8
3

2
PR122

2.5VREF

200K

39

PR119
100K

PR120

PU9B
LM358

2.5VREF

PQ28
DTC115EK

SUSP#

100K
+

PR121

3
PQ29
2SA1036K

2.5VREF

PC89
68PF

100K
PU13A
LM393M
1

PR114
200K_1%
1

+5VALWP

2
2

PC84
220PF

2
PR112
5.1K

PC83
0.1UF_16V

2
8
3

PC81
150UF_D_6.3V_KO

PC116
0.1UF_50V

PR118
300K_0.5%

PR117
100

PU9A
LM358

PC87
0.01UF

1
2

VS

PR116
1K

+1.5VSP
VS

PC88
2200PF_50V

PD27
RB051L-40

PR115
10K

PQ26
HMBT2222A

2
1
2

PD26
RB751V

PC86
4.7UF_1206_16V

PC85
150UF_D_6.3V_KO

6
5
2
1

1.8VIN

+1.8VALWP

PL10
5UH-SPC-06704
LX1.8 1
2

PQ25
SI3445DV

+1.5V+-5%

+1.8V+-5%

PR111
0_1206

6
5
2
1
G

PC82
4.7UF_1206_16V

+1.8VALWP

PQ24
SI3442DV
+3VALWP

100K

2
PR123

28,29,32,36,40

1
0

1
@0

SYSON

32,36

100K
4

PR124
511K_1%

PC90
1000PF

SYSON#

SYSON# 36

100K

PU13B
LM393M
7

100K

PQ30
@DTC115EK

COMPAL ELECTRONICS, INC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY

OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
Size
Document Number
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
B
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.
Date: , 18, 2004

SCHEMATIC, M/B LA-1331

Rev

401207

2A
Sheet

82

of

83

B+

PC93

PC94
5
6
7
8

PC92

4.7UF_1210_25V

+5VALWP

PR125

PQ32
IR7811A

IR7811A
PD28
1SS355

2
17

PR139
180K_1%

PC99
47PF_0603

PC100
PC101
2VREF
1UF_0805

1UF_0805

PR143
100K_1%

+2VREF

VGATE
TIME

VCC

FB

SDN/SKIP

POS

13

VDD

NEG

CC

ZMODE

1
2

PD29
EC31QS04

0.01UF

PR135
2.8K_1%
1
PR137

PC97
4.7UF_0805_10V

2
100

PC98
+5VALWP
PR140
49.9K_1%

1000PF_0603

19

20

OVP

SUS

11

REF

S1

12

ILIM

S0

15

GND

TON

PR142
68K_1%

18

10

D
+5VALWP

CPUB+

5
6
7
8

PQ37
2N7002
2
G

13,16
2
G

PC121
1000P

PQ40
IR7811A

IR7811A
3
2
1

3
2
1

PL13
SSC-1305-0R5 0.5UH
CS+ 2

VTT2LX

14

CM--

CM-

LX

13

CS--

CS-

DH

12

CS++

CS+

VDD

11

DL

10

2.7_0805

PC104 0.1UF_0805
PD31
C PUVDD
2
1

2.2
PR152

PC119

PQ43
2N7002
2
G

PM_DPRSLPVR

S
+CPU_CORE

PR161

PR149
2mR
1

PQ41
SI4362DY

PQ42
SI4362DY

PD30
EC31QS04

15

BST

5
6
7
8

V+

CM+

5
6
7
8

TRIG

0.01UF

CPUB+

PQ44
2N7002
2
G
PC122
1000P

2
CM++

PR151
1K_1%

16

PR150
20K_1%

PC103
0.1UF_0805

LIMIT

+CPU_CORE

PU11MAX1887
ILIM

PC102
470P

GND

PGND

1SS355

PC105

3
2
1

COMP

3
2
1

PC106

PC107

PC108

PC109
1UF_0805

4.7UF_1210_25V

4.7UF_1210_25V

4.7UF_1210_25V

4.7UF_1210_25V

0 PR154

PR157
200 2

CS++

PR156
0

PU12

VR_ON

DELAY

SENSE

ERROR

CNOISE

GND

32 VR_ON
PR160
0

PR158
200 2

VIN

ON/OFF#

GMUXSEL

CPUSTP#

DPRSLPVR

PM D-S

BM

BM D-S

Deeper

VCORE'
1.30V

Offset
0%
4.62%

1.20V
1.0V
D

PR159
@10K_1%

PC115

.1UF

VCORE
1.30V
1.239V

2.0%

1.176V

4.62%

1.144V

0%

SI9182AD

CS--

PM

VOUT

CPU_ON

2200PF PC114

PC113
4700P

CS+ 1

4.7UF_1206_16V

PC112
4.7UF_1206_16V

CM--

PC111

PC110
4700P

+CPU_CORE 1

PR155
200 2

CM++

CM+ 1

+CPU_CORE 1

+1.2VPP

+3VALWP

PR153
200 2

PM_GMUXSEL 16
PC120
1000P

PM_STPCPU#

PQ39

PR148
48.7K_1%

PQ36
2N7002
2
G

PR144
100K

PQ38
2N7002S

PR141
100K

PQ35
2N7002
2
G

PM_DPRSLPVR 16

PR146
33K_1%

PD32
EC31QS04

POS

PC118
1000P

PR145
53.6K_1%

PC96
0.1UF_0805

CPUFB

PQ34
SI4362DY

PC117

14

PQ33
SI4362DY

0K_0603
1
120K

D0

CPUB+

2.7_0805

V+

25

PR147
PC95
0.1UF_0805

16

DL

150K_1%

D1

2.2
PR130

PR138

PR134
2
PR136
CPU_ON

24

+CPU_CORE
+CPU_CORE

VGATE

26

35
+3VALWP

BST

CPU_VID0

D2

3
2
1

5,6

28

23

5
6
7
8

CPU_VID1

DH

5
6
7
8

5,6

D3

CM+

3
2
1

CPU_VID2

LX

22

5,6

D4

1
100K
1
100K
1
100K
1
100K

CPU_VID3

PR128
2mR

PL12
SSC-1305-0R5 0.5UH

VTT1LX

PM_DPRSLPVR

CPU_VID4

5,6

27

20
PU10 MAX1718A
21

3
2
1

PR126

3
2
1

PQ31

2
2

C PUVDD

CPU-CORE

4.7UF_1210_25V

5,6

4.7UF_1210_25V

5
6
7
8

4.7UF_1210_25V

PC91

2
PR127
2
PR129
2
PR131
2
PR132
2
PR133

CPUB+
PL11
KC-FBM-L11-322513-201LMAT

5
6
7
8

COMPAL ELECTRONICS, INC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY

OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
Size
Document Number
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
B
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
Date: , 18, 2004

SCHEMATIC, M/B LA-1331

1.0V
E

Rev

401207

2A
Sheet

83
H

of

83