ELE2120 Digital Circuits and Systems

Tutorial Note 11 Tutorial Note 11

Prepared by Qi Lin

Outline
Key points in the sequential circuit design Key points in the sequential circuit design
1. Convert Task to state diagram 1. Convert Task to state diagram 2. Moore FSM and Mealy FSM 2. Moore FSM and Mealy FSM 3. Equivalent states 3. Equivalent states 4. State assignment 4. State assignment

Example 1
Problem
Draw a state transition diagram for a decimal counter which counts from 0~9 and carry 1 when meeting 10(decimal)

Analysis
There is no input : when power on, it will count automatically. Output : when meeting 10(decimal), the output is 1. Binary code assignment : Q3Q2Q1Q0 (0~F, but actual state is from 0~9)

Example2 Example 2
Problem
Avendingmachinesellinga20centitem g g Inputcouldbe5,10cents Input Output State centsalreadyinthemachine y

Statediagram State diagram

States A 0B 5centsC 10centsD 15cents Inputx:0 5cents1 10cents
0/0 /

A 1/0 /

0/1 1/1

B 1/0 1/0 / 1/1

C 0/0

Moore FSM and Mealy FSM

Moore FSM

Mealy FSM

Example
Derive a minimal state table for a single-input and single-output Moore-type FSM that produces an output of 1 if in the input sequence it detects either 110 or 101 patterns. Overlapping sequences should be detected. (Q3 in Quiz 2)

Moore FSM
Task description:
clock : t0 t1 t2 input w: 0 1 1 output z: 0 0 0 t3 t4 t5 0 0 1 1 0 0 t6 t7 t8 0 1 1 0 1 0 t9 t10 0 0 1 0

State Assignment(Moore FSM):

state state state state state State A: B: C: D: E: F: Got no 1 Got1 Got11 Got110 Got10 Got101

Moore FSM

Moore FSM
Present state A B C D E F Next State w=0 A E D A A E w=1 B C C F F C Output Z 0 0 0 1 0 1

State table

Mealy FSM
State Assignment(Mealy FSM):
state state state state A: B: C: D: Got no 1 Got1 Got11 Got10

Mealy FSM
Reset

1/0

1/0 0/0

1/0

B
1/1 0/0

0/0 0/1 State Diagram

Mealy FSM
Present state A B C D Next State w=0 A D D A w=1 B C C B Output Z w=0 0 0 1 0 w=1 0 0 0 1

State table

EquivalentStates quivalent States

Statesareequivalent if: Foreveryinput,theygotothesamenext i h h state withthesameoutput Statesaredifferent if: Foranyinput,theyhavedifferentoutputs For any input, they have different outputs Adecisionmustbedeferred if: Foreveryinput,theyhavethesameoutput, F i h h h butgotodifferentstates

Example:EquivalentStates Example: Equivalent States

0/0 A C

0/0 B 1/0

1/0 D

Example:Non EquivalentStates Example: Non Equivalent States

0/1 A C

0/0 B 1/0

1/0 D

Example:DeferredDecision Example: Deferred Decision

0/1,1/0 0/1, 1/0 A C

0/1,1/0

AisequivalenttoBifandonlyif C i Ai i l t t B if d l if CisequivalentD i l tD

ResultsofaDeferredDecision
A 0,1/0 B 0/1,1/0 0/1 1/0 D E 0/1,1/0 C 0,1/0

Ais equivalenttoB i l 0/1,1/0 0/1 1/0 A 0,1/1 0 1/1 B 0/1,1/0 D E C 0,1/0

Aisnot equivalenttoB

StateAssignment State Assignment

Duringthedesignprocess,statesareoften y y denotedsymbolically Somestateassignments(choosingabinary representationofthestate)resultinsimpler representation of the state) result in simpler circuitsthanotherstateassignments Somesimpleguidelinesavoidtheworststate assignments

RulesforStateAssignment Rules for State Assignment

1) S 1)Stateswhichhavethesamenextstatefora hi h h h f giveninputshouldbeadjacent
(adjacentmeansdifferingbyasinglebitinthestate assignment=adjacentinaKmap)

2) S 2)Stateswhicharethenextstateofagivenstate hi h h f i shouldbeadjacent Tominimizetheoutputequation: p q Stateswhichhavethesameoutputforagiven inputshouldbeadjacent

ApplyingtheRulesforState Assignment
Applyrule1first,thenapplyrule2 M lti l Multiplerequirementsshouldbeplacedas i t h ld b l d groupsof4ormoreontheKmap Stateadjacencieswhichoccurmorethan onceshouldbegiveprecedence

Example3 Example 3
Description i i
DesignaMealysequentialstatemachine(SSM)whose inputisatwobitnumber,I1I0 t b i t i ti t bit b I tobeinterpretedasa t d decimalnumber=2*I1+I0. The output is 1ifthepreviousinputisgreaterthan Theoutputis 1 if the previous input is greater than orequaltothecurrentinput

a) Make a state assignment to minimize the a)Makeastateassignmenttominimizethe controlinputs b) Make a state assignment to minimize the b)Makeastateassignmenttominimizethe outputcircuit.

Tasktostatediagram Mealysolution Task to state diagram Mealy solution

currentinput/output current input/output 0/1

Last number input

1/0 0 3/0 0/1 3 3/0 2/0 1 1/1

2/0 2

StateTable State Table

Input

0 A/1 A/1 A/1 A/1

1 B/0 B/1 B/1 B/1

2 C/0 C/0 C/1 C/1

3 D/0 D/0 D/0 D/1

A(0)
Currentstate

B(1) C(2) D(3)

Nextstate/output

StateAssignment(Controls)
Input
A(0) 0 A/1 A/1 A/1 A/1 1 B/0 B/1 B/1 B/1 2 C/0 C/0 C/1 C/1 3 D/0 D/0 D/0 D/1

Currents state

( ) B(1) C(2) D(3)

Nextstate/output

1)Statesthathavethesamenextstateshouldbeadjacent ) h h h h ld b d (ABCD)useless 2)Statesthatarethenextstateofagivenstateshouldbeadjacent (ABCD)useless (ABCD) l

StateAssignment(Output)
Input Curr rentstate
A(0) B(1) C(2) D(3) 0 A/1 A/1 A/1 A/1 1 B/0 B/1 B/1 B/1 2 C/0 C/0 C/1 C/1 3 D/0 D/0

Nextstate/output
D/0 D/1

a)Statesthathavethesameoutputshouldbeadjacent (ABCD),(BCD),(CD),(AB),(ABC) (ABCD), (BCD), (CD), (AB), (ABC) Therefore,CshouldbenexttoDandAnexttoB LetA=00,B=01,C=10,D=11 , , ,

xyq1q0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Q1Q0Z 00 1 00 1 00 1 00 1 01 0 01 1 01 1 01 1 10 0 10 0 10 1 10 1 11 0 11 0 11 0 11 1

Goodstate assignmentto assignment to minimizeoutput p

LetA=00,B=01,C=10,D=11 L t A 00 B 01 C 10 D 11 Z=q1q0+yq1+xq0+xy

xyq1q0 0000 0001 0010 0011 0100 0 0 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Q1Q0Z 00 1 00 1 00 1 00 1 11 0 11 1 11 1 11 1 01 0 01 1 01 1 01 0 10 0 10 0 10 1 10 0

Badstate assignmentwith respecttooutput respect to output

A=0last=00 B=1last=11 C=2last=01 D=3last=10

Z=q1q0+yq1q0+xq0+xy

Requiresa3inputANDinsteadofa2inputAND.