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Testable Fault Detecting Vedic Multiplier Core
Testable Fault Detecting Vedic Multiplier Core
Testable Fault Detecting Vedic Multiplier Core
Saranya B 1BG08EC087 Priti Saigal 1BG08EC074 Sahana R 1BG08EC086 Batch B10-2012 Project Seminar Project Guides Dr Veena S Chakravarthi (Internal) Mr.Chandramohan Umapathy (External) Professor ECE, BNMIT Cofounder of Pool Systems Department of Electronics Communication Engineering 1 BNM Institute of Technology 08-05-12 www.bnmit.org Sharan J M 1BG08EC093
Introduction
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Data Pre-processor
RTL CODE
TEST BENCH
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(ab) = a + 2ab + b
16
16
16
16
MAS
8 8 8 8 8 8 8
MAS
MAS
RTL CODE
Duplex adder_8
32
33
32
Duplex adder_8
Duplex adder_16
64
FUNCTIONAL VERIFICATION
Output number
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RTL CODE
FUNCTIONAL VERIFICATION
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Multiplier
RTL CODE
FUNCTIONAL VERIFICATION
6
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RTL CODE
FUNCTIONAL VERIFICATION
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B
32 8
A7A6 A5A4 A3A2 A1A0 A1A0 B1B0 P1 A7A6 A5A4 B7B6 B5B4 P14 + P15 A3A2 A1A0 B3B2 B1B0 P2 + P3 A7A6 RTL CODE B7B6 P16 FUNCTIONAL VERIFICATION
P16 P14+P15
B7B6 B5B4 B3B2 B1B0 A7A6 A5A4 A3A2 A1A0 B7B6 B5B4 B3B2 B1B0 P7 + P8 + P9 + P10 A7A6 A5A4 A3A2
PRODUCT
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OUTPUT
Cuber
RTL CODE
FUNCTIONAL VERIFICATION
9
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Fault Detector
RTL CODE
FUNCTIONAL VERIFICATION
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10
Performance Parameter Cell Area Timing Power Performance Parameter Cell Area Timing Power
Performance Parameter
Cell Area Timing Power
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16.88% 19.07%
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Chipscope
Chipscope is a set of tools made by Xilinx that allows you to easily probe the internal signals of your design inside an FPGA. It has two main parts: Embeddable IP cores that capture and store values of signals within the FPGA. Software tool that allows one to read the captured data and visualize it on a host computer. The Xilinx Chipscope tools package has several modules that are added to Verilog design. They are: ICON (Integrated controller) VIO (Virtual Input/Output) ILA (Integrated Logic Analyser)
Chipscope
Incorporating ChipScope Modules into Your Design 1. Generate the ChipScope modules, using the ChipScope Core Generator. 2. Incorporate and instantiate the ChipScope modules into the top-level module in your design. 3. Connect the ChipScope modules to your design. 4. Synthesize, implement, and run the design on the FPGA.
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ICON-1 ICON-2 ICON-3 1. Double-click on ICON. (a) Component Name: Assign your ICON a name (this is arbitrary). (b) Select the correct Number of Control Ports. 2. Your ICON will have been created in the directory you specified to store your project. VIO-1 VIO-2 VIO-3
1. Double-click on VIO. (a) Component Name: Assign your VIO a name (this is arbitrary). (b) Enter the bit width for any 2 of the 4 signals: asynchronous inputs, synchronous inputs, asynchronous outputs and synchronous outputs. 2. Your VIO will have been created in the directory you specified to store your project. UCF You will also need a UCF file in the same directory to specify that the designs timing should be meet a clock constraint, and that the system clock is located at a specific pin on the board.
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Instantiate ICON and VIO in top module. TOP MODULE After generating the top module, implement the process by clicking on analyze design using chipscope. After the entire process is successful, the main window of Chipscope Pro opens. Make sure that FPGA board is connected to PC. Click on Initialize JTAG Chain icon located at the top right corner of the window. Now select the FPGA device from the JTAG chain, right click and then select Configure to specify the configuration bit stream file. CHIPSCOPE PRO
The required input and output signals are obtained in VIO Console. Result for Quarter Squarer multiplier is displayed.
SNAPSHOT
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UART Data Transmission UART data transmit and receive UART Tx byte register UART Rx byte register Clock frequency = 66MHz Baud rate of UART core = 19200 bits/sec Frame format
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References
High speed squarer by Chandra Mohan Umapathy. http://www.magicalmethods.com/FREE/applications_in_sw/Camera_high_speed_paper.pdf Vedic Mathematics based 32 Bit High Speed Squarer Circuit using McCMOS Technique for Low Power VLSI Applications by Arindam Chakraborty ,Hamim Zafar, Jubin Hazra . High speed vedic multiplier for digital signal processor by Ramesh pushpangadam, Vineet Sukumaran, Rino Innocent, Dinesh Sasikumar, Vaisak Sundar. Analysis, Verification and FPGA Implementation of Vedic Multiplier with BIST Capability by Vinay Kumar . www.vedicmaths.org www.vedicganita.org
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Greetings from Cadence! Congratulations! Your submission below has been shortlisted for the next stage of the Cadence Design Contest 2012. Title of abstract: Testable fault detecting Vedic Multiplier Core Category: Bachelor's Institute: BNM Institute of Technology Please submit your project report by *Friday, July 20, 2012*. Late submissions will not be accepted. Format of Paper Your final submission must be in the following format (IEEE Standard). On Front Cover: Project Name Project Submitters Details (name, email address, semester) Guides Details (name, email address) if applicable
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Literature survey..
Vedic Mathematics was Rediscovered in the early twentieth century by Swami Sri Bharati Krishna Tirthaji Maharaja. The sutras were contained in the Atharva Veda a branch of mathematics and engineering. It comprises of 16 sutras like Urdhva Tiryagbyham, Nikhilam Navatascaramama Dasatah and sub sutras derived from the main sutras like duplex sutra. Reduces cumbersome looking calculations to very simple ones resulting in a more efficient method in terms of speed and implementation
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Application scenario..
CONVOLUTION
C I A F
ALU
MICROPROCESSOR
DSP OPERATIONS
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Functional specification..
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Functional verification multiplier using Nikhilam BNMIT DEPT OF ECE-2012 and Anurupye..
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ICON-1
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ICON-2
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ICON-3
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VIO-1
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VIO-2
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VIO-3
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UCF
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Top Module
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