INDEX

S.No 1. 2. NAME Page No 1 2 2 2 3 6 8 10 10 12 12 12 13 14 14 15 16 17 17 18 18 22 22 22 23 24 25 25 25 27 27 27 28 28 29 29 30 31

INTRODUCTION VERTICAL INTERCONNECTIONS IN 3-D ELECTRONICS 2.1. Periphery Interconnection between Stacked ICs 2.1.1. Stacked Tape Carrier 2.1.2) Solder Edge Conductors 2.1.3) Thin Film Conductors on Face-of-a-Cube 2.1.4) An Interconnection Substrate Soldered to the Cube Face 2.1.5) Folded Flex Circuits 2.1.6) Wire Bonded Stacked Chips 2.2. Area Interconnection between Stacked ICs 2.2.1) Flip-Chip Bonded Stacked Chips Without Spacers 2.2.2) Flip-Chip Bonded Stacked Chips With Spacers 2.2.3) Micro bridge Springs and Thermo migration Vias 2.3. Periphery Interconnection between Stacked MCMs 2.3.1) Solder Edge Conductors 2.3.2) Thin Film Conductors on Face-of-a-Cube 2.3.3) Blind Castellation Interconnection 2.3.4) Wire Bonded Stacked MCMs 2.3.5) Elastomeric Connectors 2.4. Area Interconnection between Stacked MCMs 2.4.1) Arrays of Contacts Between MCMs With Through Hole Vias 3. ADVANTAGES OF 3-D PACKAGING TECHNOLOGY 3.1. Size and Weight 3.2. Silicon Efficiency 3.3. Delay 3.4. Noise 3.5. Power Consumption 3.6. Speed 3.7. Interconnect Usability and Accessibility 3.8. Bandwidth 4. LIMITATIONS OF 3-D PACKAGING TECHNOLOGY 4.1. Thermal Management 4.2. Design Complexity 4.3. Cost 4.4. Time to Delivery 4.5. Design Software 5. APPLICATIONS 6. CONCLUSION REFERENCES