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  • I Yr M.Tech Ii Sem 2 Technical Seminar Component-1: Title of The Seminar

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    This document summarizes a student's technical seminar presentation on 3D packaging technologies for VLSI systems. The presentation reviewed state-of-the-art 3D stacking techniques for meeting demands of low power, small size, and portable systems. Vertical interconnect methods were discussed in detail. Key issues like silicon efficiency, complexity, thermal management and connection density that influence the choice of 3D stacking technology for different applications were briefly covered. The seminar was supervised by Mr. Shaik Basha and presented by the student K Nagarjun.

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    This document summarizes a student's technical seminar presentation on 3D packaging technologies for VLSI systems. The presentation reviewed state-of-the-art 3D stacking techniques for meeting demands of low power, small size, and portable systems. Vertical interconnect methods were discussed in detail. Key issues like silicon efficiency, complexity, thermal management and connection density that influence the choice of 3D stacking technology for different applications were briefly covered. The seminar was supervised by Mr. Shaik Basha and presented by the student K Nagarjun.

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    9 views2 pages

    I Yr M.Tech Ii Sem 2 Technical Seminar Component-1: Title of The Seminar

    Uploaded by

    nagarjuna_sree
    This document summarizes a student's technical seminar presentation on 3D packaging technologies for VLSI systems. The presentation reviewed state-of-the-art 3D stacking techniques for meeting demands of low power, small size, and portable systems. Vertical interconnect methods were discussed in detail. Key issues like silicon efficiency, complexity, thermal management and connection density that influence the choice of 3D stacking technology for different applications were briefly covered. The seminar was supervised by Mr. Shaik Basha and presented by the student K Nagarjun.

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    IST YR M.

    TECH II SEM 2nd TECHNICAL SEMINAR COMPONENT-1


    Title of the Seminar
    A Review of 3-D Packaging Technology

    Area of the Seminar VLSI Abstract

    This paper reviews the state-of-the-art in three dimensional (3-D) packaging technologies for very large scale integration (VLSI). A number of bare dice and multichip module (MCM) stacking technologies are emerging to meet the ever increasing demands for low power consumption, low weight and compact portable systems. Vertical interconnect techniques are reviewed in details. Technical issues such as silicon efficiency, complexity, thermal management, interconnection density, speed, power etc. are critical in the choice of 3-D stacking technology, depending on the target application, are briefly discussed. Name of the Supervisor Name of the Student : : Mr. Shaik Basha, Associate Professor, ECE K Nagarjun 11C104211

    Signature of the Supervisor

    Signature of the Student

    References
    [1] D. Abbott et al., Towards the realization of an interactive mobile multimedia personal communicator (Im3PC), IEEE 14th Australian Microelectron. Conf. (Micro 97), Melbourne, Australia, Sept. 28Oct. 1, 1997, pp. 1822. [2] S. Sheng, A. Chandrakasan, and R. W. Brodersen, A portable multimedia terminal, IEEE Commun. Mag., vol. 30, pp. 6475, Dec. 1992. [3] R. E. Terrill, Aladdin: Packaging lessons learned, in Proc. 1995 Int. Conf. Multichip Modules, Denver, CO, Apr. 1995, pp. 711. [4] R. Crowley, Three-dimenstional electronics packaging, Tech. Rep., TechSearch International, Inc., Austin, TX, p. 18, Nov. 1993.

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