Solution of Verilog HDL by Samir Palnitkar

4/4/13
Chapter 7: Behavioral Modeling | Tarique Mahmud
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Chapter 7: Behavioral Modeling

by tarique on October 4th, 2011 1. Declare a register called oscillate. Initialize it to 0 and make it toggle every 30 time units. Do not use always statement ( Hint: Use the forever loop). ANSWER:
www.tariquemahmud.net/?p=536
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2. Design a clock with time period = 40 and a duty cycle of 25% by using the always and initial statements. The value of clock at time = 0 should be initialized to 0. ANSWER:
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3. Given below is an initial block with blocking procedural assignments. At what simulation time is each statement executed? What are the intermediate and final values of a, b, c, d?
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ANSWER:
4. Repeat exercise 3 if nonblocking procedural assignments were used. ANSWER:
5. What is the order of execution of statements in the following Verilog code? Is there any ambiguity in the order of execution? What are the final values of a,b,c,d?
ANSWER:
6. What is the final value of d in the following example? (Hint: See intra-assignment delays.)
ANSWER:
7. Design a negative edge-triggered D-flipflop(D_FF) with synchronous clear, active high (D_FF clears only at a negative edge of clock when clear is high). Use behavioral statements only. (Hint: Output q of D_FF must be declared as reg). Design a clock with a period of 10 units and test the D_FF. ANSWER:
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8. Design the D-flipflop in exercise 7 with asynchronous clear (D_FF clears whenever clear goes high. It does not wait for next negative edge). Test the D_FF. ANSWER:
9. Using the wait statement, design a level-sensitive latch that takes clock and d as inputs and q as output. q=d whenever clock=1.
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10. Design the 4-to-1 multiplexer in eg 7-19 by using if and else statements. The port interface must remain the same.
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11. Design the traffic signal controller discussed in this chapter by using if and else statements. ANSWER: 1 `define TRUE 1b1; 2 3 `define FALSE 1b0; 4 5 //Delays 6 7 `define Y2RDELAY 3 //Yellow to red delay 8 9 `define R2GDELAY 2 //Red to green delay 10 11 module sig_control 12
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13 (hwy,cntry,X,clock,clear); 14 15 //I/O ports 16 17 output [1:0] hwy, cntry; 18 19 //2-bit output for 3 states of signal 20 21 //GREEN, YELLOW, RED 22 23 reg [1:0] hwy,cntry; 24 25 //declared output signals are registers 26 27 input X; 28 29 //if TRUE, indicates that there is car on 30 31 //the country road, otherwise FALSE 32 33 input clock,clear; 34 35 parameter RED=2d0, 36 37 YELLOW=2d1, 38 39 GREEN=2d2; 40 41 //State definition HWY CONTRY 42 43 parameter S0=3d0, //GREEN RED 44 45 S1=3d1, //YELLOW RED 46 47 S2=3d2, //RED RED 48 49 S3=3d3, //RED GREEN 50 51 S4=3d4; //RED YELLOW 52 53 //Internal state variables 54 55 reg [2:0] state; 56 57 reg [2:0] next_state; 58 59 //state changes only at postive edge of clock 60 61 always @(posedge clock)
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62 63 if(clear) 64 65 state<=S0; //Controller starts in S0 state 66 67 else 68 69 state<=next_state; //State change 70 71 //Compute values of main signal and country signal 72 73 always @(state) 74 75 begin 76 77 //case(state) 78 79 //S0: ; //No change, use default 80 81 if(state==S1) 82 83 hwy=YELLOW; 84 85 else if(state==S2) 86 87 hwy=RED; 88 89 else if(state==S3) 90 91 begin 92 93 hwy=RED; 94 95 cntry=GREEN; 96 97 end 98 99 else if(state==S4) 100 101 begin 102 103 hwy=RED; 104 105 cntry=YELLOW; 106 107 end 108 109 else 110
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111 begin 112 113 hwy=GREEN; //Default Light Assignment for Highway light 114 115 cntry=RED; //Default light Assignment for Country light 116 117 end 118 119 end 120 121 //State machine using case statements 122 123 always @(state or X) 124 125 begin 126 127 if(state==S0) 128 129 if(X) 130 131 next_state=S1; 132 133 else 134 135 next_state=S0; 136 137 else if(state== S1) 138 139 begin //delay some positive edges of clock 140 141 repeat(`Y2RDELAY) @(posedge clock); 142 143 next_state=S2; 144 145 end 146 147 else if(state== S2) 148 149 begin //delay some positive edges of clock 150 151 repeat(`R2GDELAY) @(posedge clock); 152 153 next_state=S3; 154 155 end 156 157 else if(state== S3) 158 159 if(X)
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160 161 next_state=S3; 162 163 else 164 165 next_state=S4; 166 167 else 168 169 begin //delay some positive edges of clock 170 171 repeat(`Y2RDELAY) @(posedge clock); 172 173 next_state=S0; 174 175 end 176 177 //default:next_state=S0; 178 179 //endcase 180 181 end 182 183 endmodule 12. Using a case statement, design an 8-function ALU that takes 4-bit inputs a and b and a 3-bit input signal select, and gives a 5-bit output out. The ALU implements the following functions based on a 3-bit input signal select. Ignore any overflow or underflow bits. ....... ANSWER:
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13. Using a while loop, design a clock generator. Initial value of clock is 0. Time period for the clock is 10. ANSWER:
14. Using the for loop, initialize locations 0 to 1023 of a 4-bit register array cache_var to 0.
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ANSWER:
15. Using forever statement, design a clock with time period =10 and duty cycl = 40%. Initial value of clock is 0. ANSWER:
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16. Using the repeat loop, delay the statement a= a+1 by 20 positive edges of clock. ANSWER:
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17. Below is a block with nested sequential and parallel blocks. When does the block finish and what is the order of execution of events? At what simulation times does each statement finish execution?
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ANSWER:
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(p.s, I made a change at line 19).
18. Design an 8-bit counter by using forever loop, named block, and disabling of named block. The counter starts counting at count=5 and finishes at count=67. The count is incremented at positive edge of clock. The clock has a time period of 10. The counter counts through the loop only once and then is disabled.(Hint: Use the disable statement). ANSWER:
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0 count= 5 # 5 count= 6 # 15 count= 7 # 25 count= 8 # 35 count= 9 # 45 count= 10 # 55 count= 11 # 65 count= 12 # 75 count= 13 # 85 count= 14 # 95 count= 15 # 105 count= 16 # 115 count= 17 # 125 count= 18
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# 135 count= 19 # 145 count= 20 # 155 count= 21 # 165 count= 22 # 175 count= 23 # 185 count= 24 # 195 count= 25 # 205 count= 26 # 215 count= 27 # 225 count= 28 # 235 count= 29 # 245 count= 30 # 255 count= 31 # 265 count= 32 # 275 count= 33 # 285 count= 34 # 295 count= 35 # 305 count= 36 # 315 count= 37 # 325 count= 38 # 335 count= 39 # 345 count= 40 # 355 count= 41 # 365 count= 42 # 375 count= 43 # 385 count= 44 # 395 count= 45
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# 405 count= 46 # 415 count= 47 # 425 count= 48 # 435 count= 49 # 445 count= 50 # 455 count= 51 # 465 count= 52 # 475 count= 53 # 485 count= 54 # 495 count= 55 # 505 count= 56 # 515 count= 57 # 525 count= 58 # 535 count= 59 # 545 count= 60 # 555 count= 61 # 565 count= 62 # 575 count= 63 # 585 count= 64 # 595 count= 65 # 605 count= 66 # 615 count= 67 Reference: Smair Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis (2nd edition) Source: http://www.cnblogs.com/halflife/ From CSE413/ETE419 No comments yet Leave a Reply
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4/4/13

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

4. Repeat exercise 3 if nonblocking procedural assignments were used. ANSWER:

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

(p.s, I made a change at line 19).

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

Name: (required): Email: (required): Website:

Chapter 7: Behavioral Modeling | Tarique Mahmud

Chapter 7: Behavioral Modeling | Tarique Mahmud

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