BANASTHALI VIDYAPEETH PERIODICAL TEST CLASS: M.TECH II SEM.

VLSI DESIGN

SUBJECT: ANALOG AND MIXED SIGNAL IC DESIGN

NUMBER OF STUDENTS = 44 NAME OF THE EXAMINER: CHANDRA MOHAN SINGH NEGI ADDRESS: 3103, GHOSHA III, BANASTHALI VIDYAPEETH NOTE: ATTEMPT ALL QUESTIONS. WRITE SPECIFIC ANSWERS, UNNECESSARY LONG ANSWER CAN DEDUCT YOUR MARKS. MAX. MARKS: 10 Q.1. Attempt all parts. (a) Write major steps in the Analog IC design process. (1) (b) Describe the small signal model for the circuit shown in figure below. Also calculate output resistance. (1.5) TIME: 1:30 Hrs.

. (c) Calculate the input common mode range for N-channel input pair differential amplifier shown
below. (1.5)

P.T.O.

ISS

Q.2. Attempt any two parts. (1.5X 2)

(a) Calculate the output resistance and the minimum output voltage, while maintaining all devices in saturation, for the circuit shown in Fig. below. Assume that IOUT is actually 10A. You can use the value of various model parameters from the table 3.1.2 shown below. Dimensions are in micrometer.

(b) Derive expression for VREF and sensitivity for Gate source reference circuit (MOS equivalent of p-n junction referenced circuit). (c) Discuss large signal analysis of CMOS differential amplifier.

Q.3. Attempt any two parts. (1.5X 2) (a) Calculate Output resistance and Voltage gain of the differential amplifier shown in figure of Q.1(c) above. Assume that Bias current I SS is 100 A, W1/L1=W2/L2=5m/1m, W3/L3=W4/L4=1m/1m, and VDD=5V. You can use the value of various model parameters from the table 3.1-2 given above in Q.2 (a).
(b) Discuss Matching accuracy of MOS current mirrors, and derive the relation ship between output current and input current:

(c) Discuss small signal model of Wilson current mirror and calculate its output resistance. *************