EECS240 Spring 2012

Lecture 20: Comparators

Elad Alon Dept. of EECS

Comparator

Specs and issues:

Clock rate fs Offset Resolution Hysteresis Input cap Power dissipation CM rejection Kickback noise

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Flash Converter
VREF VIN

Fast: one clock cycle per conversion High complexity: 2B-1 comparators High input capacitance

R/2

R Encoder Digital Output

R/2

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Comparator Gain-Bandwidth
Example: 4Gb/s link Minimum V: 1mV Vdd = 1V Av > 1V / 1mV = 1000 in < 250ps!

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Operational Amplifier?

f 3dB

fu 2 1 Avo 3 Tbit 2 Avo 3Tbit 1000 1.33THz 3 250ps

fu

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Open-Loop Amplifier Cascade

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Cascaded Amplifier
Simplified bandwidth analysis:
Open-circuit time constants (Not most accurate, but leads to nearly the right answer for design optimization)

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Bandwidth/Gain Optimization

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Bandwidth/Gain Optimization

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Power Consumption

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Regenerative Latch

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CML Comparator (Latch)

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StrongArm Latch

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Hysteresis

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Overdrive Recovery

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Kickback

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Kickback contd

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Kickback contd

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