Traffic Light

module traffic(clk,rst,r1,r2,r3,g1,g2,g3,y1,y2,y3,pr,pg,seg_1);
input clk,rst;
output reg r1,r2,r3,g1,g2,g3,y1,y2,y3,pr,pg;
output reg[13:0]seg_1;
integer timer_count1=0,timer_count2=0;
reg clk_msec,clk_sec;
reg[4:0]count;
reg[1:0]state=2'b0;
always@(posedge clk)
begin
if(timer_count1==3999)
begin
timer_count1=0;
clk_msec=1'b1;
end
else
begin
timer_count1=timer_count1+1;
clk_msec=1'b0;
end
end
always@(posedge clk_msec)
begin
if(timer_count2==999)
begin
timer_count2=0;
clk_sec=1'b1;
end
else
begin
timer_count2=timer_count2+1;
clk_sec=1'b0;
end
end
always@(posedge clk_sec)
begin
if(~rst)
begin
r1=1'b1;g1=1'b0;y1=1'b0;
r2=1'b1;g2=1'b0;y2=1'b0;
r3=1'b1;g3=1'b0;y3=1'b0;
state=2'b00;
end
else
begin
case(state)
2'b00:begin
if(count==5'b11100)
begin
g1=1'b0;
r1=1'b0;
y1=1'b1;
r3=1'b1;
y3=1'b0;
g3=1'b0;
end
if(count==5'b11111)
begin

g1=1'b1;
y1=1'b0;
state=2'b01;
end
else
state=2'b00;
end
2'b01:begin
if(count==5'b11100)
begin
y1=1'b1;
g1=1'b0;
r2=1'b0;
y2=1'b1;
g2=1'b0;
end
if(count==5'b11111)
begin
r1=1'b1;
y1=1'b0;
y2=1'b0;
g2=1'b1;
state=2'b10;
end
else
state=2'b01;
end
2'b10:begin
if(count==5'b11100)
begin
y2=1'b1;
g2=1'b0;
r3=1'b0;
y3=1'b1;
g3=1'b0;
end
if(count==5'b11111)
begin
r2=1'b1;
y2=1'b0;
y3=1'b0;
g3=1'b1;
state=2'b11;
end
else
state=2'b10;
end
2'b11:begin
if(count==5'b11100)
begin
y1=1'b0;
y3=1'b1;
g3=1'b0;
end
if(count==5'b11111)
begin
y1=1'b0;
r3=1'b1;
y3=1'b0;
state=2'b00;

end
else
state=2'b11;
end
endcase
end
end
always@(count,state)
begin
if((state==2'b00)&&(count<=5'b11100))
begin
pr=1'b1;
pg=1'b0;
end
else
begin
pr=1'b0;
pg=1'b1;
end
end
always@(posedge clk_sec)
begin
if(rst==1'b0)
count=5'b00000;
else if(clk_sec)
begin
count[4:0]=count[4:0]+1;
end
end
always@(count)
begin
case(count[4:0])
5'b00000:seg_1=14'b11111101111110;
5'b00001:seg_1=14'b11111100110000;
5'b00010:seg_1=14'b11111101101101;
5'b00011:seg_1=14'b11111101111001;
5'b00100:seg_1=14'b11111100110011;
5'b00101:seg_1=14'b11111101011011;
5'b00110:seg_1=14'b11111101011111;
5'b00111:seg_1=14'b11111101110000;
5'b01000:seg_1=14'b11111101111111;
5'b01001:seg_1=14'b11111101111011;
5'b01010:seg_1=14'b01100001111110;
5'b01011:seg_1=14'b01100000110000;
5'b01100:seg_1=14'b01100001101101;
5'b01101:seg_1=14'b01100001111001;
5'b01110:seg_1=14'b01100000110011;
5'b01111:seg_1=14'b01100001011011;
5'b10000:seg_1=14'b01100001011111;
5'b10001:seg_1=14'b01100001110000;
5'b10010:seg_1=14'b01100001111111;
5'b10011:seg_1=14'b01100001111011;
5'b10100:seg_1=14'b11011011111110;
5'b10101:seg_1=14'b11011010110000;
5'b10110:seg_1=14'b11011011101101;
5'b10111:seg_1=14'b11011011111001;
5'b11000:seg_1=14'b11011010110011;
5'b11001:seg_1=14'b11011011011011;
5'b11010:seg_1=14'b11011011011111;
5'b11011:seg_1=14'b11011011110000;

5'b11100:seg_1=14'b11011011111111;
5'b11101:seg_1=14'b11011011111011;
5'b11110:seg_1=14'b11110011111110;
5'b11111:seg_1=14'b11110010110000;
default:seg_1=14'b00000000000000;
endcase
end
endmodule
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"clk"
"g1"
"g2"
"g3"
"pg"
"pr"
"r1"
"r2"
"r3"
"rst"
"seg_1<0>"
"seg_1<10>"
"seg_1<11>"
"seg_1<12>"
"seg_1<13>"
"seg_1<1>"
"seg_1<2>"
"seg_1<3>"
"seg_1<4>"
"seg_1<5>"
"seg_1<6>"
"seg_1<7>"
"seg_1<8>"
"seg_1<9>"
"y1"
"y2"
"y3"

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