Two Terminal Nanoscale Electronics

David T. Shaw Spring, 2013

Memristor

TiO2 Memristor

NMOS Structure

LD is caused by side diffusion

Substrate contact--to reverse bias the pn junction Connect to most negative supply voltage in most circuits.

Source: the terminal that provides charge carriers. (electrons in NMOS) Drain: the terminal that collects charge carriers.

Saturation of Drain Current

P-N junctions

CNT FET

Martel, R.; Schmidt, T.; Shea, H. R.; Hertel, T.; Avouris, Ph. (1998). "Single- and multiwall carbon nanotube field-effect transistors". Applied Physics Letters 73 (17): 2447.

CNT FET

Leakage Current limits

Off-state and gate leakage currents severely limit performance for EOTR MOS. Scaling limit for SiO2 gate 30 nm MOS with 0.8 nm gate oxide. Many non-classical MOS configurations expressly designed for minimizing leakage currents.

Potential Contours for Deep and Shallow MOS

Shallow junctions have smaller leakage current the gate!!

TriGate transistors (22nm Ivy Bridge 3D) fin chips to reduce leakage problem

Wrap-around gate CNT-FETs

Schottky barrier