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    VHDL Code For Right Shift Register

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    sklove123
    The document provides feedback on VHDL code for implementing a right shift register. It notes that the original code will shift the rightmost value into all left locations instead of performing a right shift. It recommends updating the code to first assign the rightmost value to a temporary variable, then shift each value right by one location in a loop, and finally assign the input to the rightmost location. It also suggests declaring the temporary vector as a register for holding the shifted values.

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    VHDL Code For Right Shift Register

    Uploaded by

    sklove123
    71 views2 pages
    The document provides feedback on VHDL code for implementing a right shift register. It notes that the original code will shift the rightmost value into all left locations instead of performing a right shift. It recommends updating the code to first assign the rightmost value to a temporary variable, then shift each value right by one location in a loop, and finally assign the input to the rightmost location. It also suggests declaring the temporary vector as a register for holding the shifted values.

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    Vhdl Codes (2)

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    The document provides feedback on VHDL code for implementing a right shift register. It notes that the original code will shift the rightmost value into all left locations instead of performing a right shift. It recommends updating the code to first assign the rightmost value to a temporary variable, then shift each value right by one location in a loop, and finally assign the input to the rightmost location. It also suggests declaring the temporary vector as a register for holding the shifted values.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    71 views2 pages

    VHDL Code For Right Shift Register

    Uploaded by

    sklove123
    The document provides feedback on VHDL code for implementing a right shift register. It notes that the original code will shift the rightmost value into all left locations instead of performing a right shift. It recommends updating the code to first assign the rightmost value to a temporary variable, then shift each value right by one location in a loop, and finally assign the input to the rightmost location. It also suggests declaring the temporary vector as a register for holding the shifted values.

    Copyright:

    Attribution Non-Commercial (BY-NC)
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    VHDL code for Right Shift register

    Your vector is std_logic_vector(7 downto 0) Left to Right, corrrect. In your loop process, you are looping first with index value as 0. So, tmp(0+1) = tmp (0); will result in tmp(1) getting written with tmp(0). This will take the second from right location and load it with the right most location. I do not believe this will accomplish your desired shift to the right, it will move the right most value into all the locations to the left. You will then be loading the right most location with the SI value. Just draw out step by step what you are trying to do and you will see that you might want to; SO = tmp(0); for i in 1 to 7 loop tmp (i-1) = tmp(i); end loop; tmp(7) = SI; and also, where is tmp declared as a register, not just as a signal? Tmp needs to hold the value, right. I hope this helps.

    library ieee; use ieee.std_logic_1164.all; entity shift is port(C, SI : in std_logic; SO : out std_logic); end shift; architecture archi of shift is signal tmp: std_logic_vector(7 downto 0); begin process (C) begin if (C'event and C='1') then for i in 0 to 6 loop tmp(i+1) = tmp(i); end loop; tmp(0) = SI; end if; end process; SO = tmp(7); end archi; Thanks a lot

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