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Verilog Exercise
Verilog Exercise
Verilog Exercise
A) Design 6 bits ripple carry counter using behavioral modeling. Make sure, it must work on negative clock edge B) Using the wait statement ,design a level-sensitive latch that takes clock and d as inputs and q as output=d whenever clock=1
Lab Task 2:
A) B) Design 16 by 4 encoder using behavioral if-else statement