FPGA Based System Design

1 ENGR. RASHID FARID CHISHTI LECTURER,DEE, FET, IIUI CHISHTI@IIU.EDU.PK WEEK 8

BEHAVIORAL MODELING MEALY MACHINE

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Friday, May 17, 2013

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A Mealy machine is a finite-state machine whose output values are determined both by its current state and the current inputs. (This is in contrast to a Moore machine, whose output values are determined solely by its current state.)

Mealy Machine

Friday, May 17, 2013

Structured Programming
// Structural description of sequential circuit module DFF (Q, D, CLK, RST); // D flip-flop with asynchronous reset. output Q; input D, CLK, RST; reg Q; always @(posedge CLK or negedge RST) if (~RST) Q = 1'b0; // Same as: if (RST == 0) else Q = D; endmodule module Mealy_Circuit (x , y, AB, CLK, RST); input x, CLK, RST; output y; output [1:0] AB; wire Da, Db,A,B; //Flip-flip input equations assign Da = (A&x) | (B&x) ; // assign Db = ~A & x ; // assign y = ~x & (A|B) ; // assign AB = {A , B} ; DFF Dffa (A, Da, CLK, RST); DFF Dffb (B, Db, CLK, RST); endmodule
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Friday, May 17, 2013

Examples

module test_Mealy_Circuit; reg x, CLK, RST; wire Y; wire [1:0] ABC ; Mealy_Circuit MC1 (x ,Y , ABC, CLK, RST); initial begin CLK = 0; repeat (30) #5 CLK = ~CLK; end initial begin RST = 1; x = 0; #10 RST = 0; #10 RST = 1; repeat (6) #30 x = ~x; end endmodule
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Friday, May 17, 2013

Input x 0 0 0 0 1 1 1 1

Present State Flip Flop Inputs A 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 DA 0 0 0 0 0 1 1 1 DB 0 0 0 0 1 1 0 0

Next State A+ 0 0 0 0 0 1 1 1 B+ 0 0 0 0 1 1 0 0

Output y 0 1 1 1 0 0 0 0

State Diagram 1/0 10 0/1

State Table
Input
D 0 1

Next Output
Q(t+1) 0 1

0/0
00 input 1/0 output 01

0/1

0/1

1/0

1/0

11
Friday, May 17, 2013

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Mealy Machine: Behavioral Modeling

module Mealy_Model ( x, y, CLK, RST ); input x,CLK,RST; output y; reg y; reg [1:0] Prstate, Nxtstate; parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11; always @ (posedge CLK or negedge RST) if (~RST) Prstate = S0; // Initialize to state S0 else Prstate = Nxtstate; // Clock operations always @ (Prstate or x) // Determine next state case (Prstate) S0: if (x) Nxtstate = S1; S1: if (x) Nxtstate = S3; else Nxtstate = S0; S2: if (~x)Nxtstate = S0; S3: if (x) Nxtstate = S2; else Nxtstate = S0; endcase always @ (Prstate or x) // Evaluate output case (Prstate) S0: y = 0; S1: if (x) y = 1'b0; else y = 1'b1; S2: if (x) y = 1'b0; else y = 1'b1; S3: if (x) y = 1'b0; else y = 1'b1; endcase endmodule
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Friday, May 17, 2013