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  • M.S.P.Velayutha Nadar Lakshmithaiammal Polytechnic College, Pavoorchatram

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    The document is an exam paper for a polytechnic college containing instructions and questions about computer architecture and assembly language. It is divided into three parts: Part A contains 10 multiple choice questions worth 1 mark each about topics like logic micro operations, pipelining, I/O interfaces, and memory concepts. Part B contains 5 short answer questions worth 3 marks each about CISC characteristics, programmed I/O, cache memory and conditional jumps. Part C contains 5 long answer questions worth 10 marks each allowing a choice between two topics for each, covering areas such as arithmetic circuits, pipelining, DMA, CPU-IOP communication, cache memory organization and page replacement, 8086 architecture, MOV instructions, D

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    The document is an exam paper for a polytechnic college containing instructions and questions about computer architecture and assembly language. It is divided into three parts: Part A contains 10 multiple choice questions worth 1 mark each about topics like logic micro operations, pipelining, I/O interfaces, and memory concepts. Part B contains 5 short answer questions worth 3 marks each about CISC characteristics, programmed I/O, cache memory and conditional jumps. Part C contains 5 long answer questions worth 10 marks each allowing a choice between two topics for each, covering areas such as arithmetic circuits, pipelining, DMA, CPU-IOP communication, cache memory organization and page replacement, 8086 architecture, MOV instructions, D

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    17 views1 page

    M.S.P.Velayutha Nadar Lakshmithaiammal Polytechnic College, Pavoorchatram

    Uploaded by

    tapas_bayen9388
    The document is an exam paper for a polytechnic college containing instructions and questions about computer architecture and assembly language. It is divided into three parts: Part A contains 10 multiple choice questions worth 1 mark each about topics like logic micro operations, pipelining, I/O interfaces, and memory concepts. Part B contains 5 short answer questions worth 3 marks each about CISC characteristics, programmed I/O, cache memory and conditional jumps. Part C contains 5 long answer questions worth 10 marks each allowing a choice between two topics for each, covering areas such as arithmetic circuits, pipelining, DMA, CPU-IOP communication, cache memory organization and page replacement, 8086 architecture, MOV instructions, D

    Copyright:

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    M.S.P.VELAYUTHA NADAR LAKSHMITHAIAMMAL POLYTECHNIC COLLEGE, PAVOORCHATRAM SECOND MODEL EXAMINATION MARCH 2010 5241 1. 2. 3. 4. Answer all questions.

    . Part A Each 1 Mark Part B Each 3 Marks Part C carry each 10 marks and answer All questions by selecting either one. Time: 3 Hrs. Max. Marks:75

    PART A 10 X 1 = 10 1. What are the applications of logic micro operations? 2. What is pipelining? 3. What is I/O interface? 4. What is asynchronous data transfer? 5. What is hit ratio? 6. What is address space & memory space? 7. Write the general format of JMP instruction. 8. What is meant by linker? 9. What is meant by subroutine? 10. Define stack. PART B 5 X 3 = 15 11. Write any three CISC Characteristics. 12. Write about programmed I/O. 13. Discuss the need for cache memory. 14. What is meant by conditional jump instruction? Explain with an example. 15. What is meant by AND instruction? Explain with an example. PART C 5 X 10 = 50 16. Explain 4 bit arithmetic circuit in briefly. (OR) Explain pipeline processing with example. 17. Explain about DMA data transfer. (OR) Explain how the communication between CPU & IOP Occurs 18. Explain (i) Operational principles of cache memory. (ii) Cache initialization. (OR) Explain page replacement in cache memory. 19. Explain in detail about 8086 architecture with neat block diagram. (OR) Write about MOV instructions with examples. 20. Explain about DOS interrupts with examples. (OR) Write an assembly language program to copy a string from one memory to another memory.

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