Reg. No.

Question Paper Code :

T3027

B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2009 Third Semester Computer Science and Engineering CS 2202 DIGITAL PRINCIPLES AND SYSTEMS DESIGN (Common to Information Technology) (Regulation 2008) Time : Three hours Marks Answer ALL Questions PART A (10 2 = 20 Marks) 1. Draw the logic diagram for the Boolean expression NAND gates. 2. 3. 4. 5. 6. 7. 8. 9. ((A + B) C)D using Maximum : 100

Perform subtraction using 1s complement (11010)2 (10000)2. Perform 9s and 10s compliment subtraction between 18 and 24. Draw the logic diagram for half adder. What is the difference between decoder and demultiplexer? What is programmable logic array? How does it differ from ROM? Write down the difference between sequential and combinational circuits. What is race around condition? What is meant by lockout condition?

10. What are the steps for design of asynchronous sequential circuit?

PART B (5 16 = 80 Marks) 11. (a) Simplify the following Quine method : F = Boolean expression using McCluskey

m (0, 9, 15, 24, 29, 30) + d (8, 11, 31) .

Or

(16)

(b) (i) and

Implement Boolean expression for EXOR gate using NAND NOR gates. (8) (4) (4)

(ii) (iii) 12. (a) (i)

Prove that ( AB + C + D )(C + D )(C + D + E ) = ABC + D . Using 2s complement perform (42)10 (68)10.

Explain the gray code to binary converter with the necessary diagram. (10) Design a half subtractor circuit.

(ii) (6)

Or (b) With neat diagram BCD complement method. (a) explain subtractor using 9s and 10s (16 )

13.

Explain with necessary diagram a BCD to 7 segment display dec ode r. (16 ) Or (b) (i) Write the comparison between PROM, PLA, PAL. (6) (ii) Design a BCD to excess-3 code converter and implement using (10) 2

PLA.

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14.

(a)

Design and implement a Mod-5 synchronous counter using JK flipflop. Draw the timing diagram also. (16) Or

(b)

(i) (ii)

Explain the working of master slave JK flip-flop. Draw the diagram for a 3 bit ripple counter.

(10) (6)

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15.

(a)

(i) (ii)

Design a comparator.

(6)

Design a non sequential ripple counter which will go through the states 3, 4, 5, 7, 8, 9, 10, 3, 4 .................. draw bush diagram also. (10) Or

(b)

(i) (ii)

Design a parity checker. Design a sequential circuit with JK flip-flop.

(6) (10)

0|1

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