lect_dma.

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Leicester University Department of Engineering Microprocessors

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DMA - Direct memory access or autonomous transfer

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What is direct memory access Cycle stealing and hidden cycle DMA. What is the DMA controller programmed with The sequence of events for a DMA Disk access terminology Disk access time Bus arbitration Bus arbitration schemes (daisy chain, parallel, self-selection, collision) DMA on the IBM-PC: What it is and how it works A Sample DMA transfer (IBM-PC)

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DMA - Direct memory access or autonomous transfer

What is direct memory access - Direct memory access is a sophisticated i/o technique in which a DMA controller replaces the CPU and takes care of the access of both, the i/o device and the memory, for fast data transfers. Using DMA you get the fastest data transfer rates possible. Special hardware writes to / reads from memory directly (without CPU intervention) and saves the timing associated with op-code fetch and decoding, increment and test addresses of source and destination. 30 The DMA controller may either stop the CPU and access the memory (cycle stealing DMA) or use the bus while the CPU is not using it (hidden cycle DMA). 35 The DMA controller has some control lines (to do a handshake with the CPU negotiating to be a bus master and to emulate the CPU behaviour while accessing the memory), an address register which is auto-incremented (or auto-decremented) at each memory access, and a counter used to check for final byte (or word) count. Say we want to input bytes: The DMA controller is programmed with (at least): - initial memory address - number of bytes to be input - address of the source

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The sequence of events is: - Bus request to CPU (can I use the bus, please?) - Bus grant from CPU (yes, you can, at the end of this bus cycle) - Bus grant acknowledge to CPU ( thank you. Here I go!) - DMA controller reads device - DMA controller writes to memory - DMA controller increments counter - DMA controller checks for End-of-Count - At the End-of-Count the DMA controller may generate an interrupt request to tell the CPU: 'I have done a DMA operation. New data is available'.

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15 DMA is commonly required to interface fast I/O devices such as video frame grabbers and hard disks: 1 s video frame grabber: 512 x 512 bytes in 50 means that the transfer rate must be 13.1 MBytes/s hard disk: 20 bit density = 50 kbits/inch 7200 rpm track radius (inner track) = 0.9" 50 kbits 7200 rotations 1min 2 0.9 inch min ute 60 s transfer time = inch = 33.93 Mbits/s

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Disk access terminology

seek time - time to move the arm to the desired track (9 ms - 20 ms) rotation latency - time for the desired sector to rotate under the head. Average = halfway turn (3600rpm - 5400rpm) transfer time - time to transfer a block of bits / bytes (2 - 4 MB/s) controller time - overhead of electronics (a few milliseconds) Example: What is the average time to read or write a 512-byte sector for a typical disk rotating @ 4000 rpm? The advertised seek time is 18 ms, the transfer rate is 2 MB/s, and the controller overhead is 2 ms. 18 ms + 0.5 rotations 60 s 0.5 kB x + + 2 ms = 27. 75 ms 4000 rpm 1 min 2 MB / s

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Answer: 40

Bus arbitration
Bus arbitration is the term used to describe the mechanism and the sequence of events that take place when another potential bus master requests the buses and is granted the use of the buses. In other words, deciding which potential bus master gets to use the bus next is called bus arbitration. For the MC68000 bus arbitration consists of the following: 1. Asserting a bus mastership request

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2. Receiving a grant indicating that the bus is available at the end of the current cycle 3. Acknowledging that mastership has been assumed 5 The 68000 has three bus arbitration control pins: BR - The bus request signal is assigned by the potential bus master to the 68000 and signals intent to use the buses. This signal indicates 10
BG - The bus grant signal is assigned by the 68000 in response to a BR , and means that the bus will be released at the end of the current bus cycle. When BG is asserted BR can be de-asserted. BG can be routed through a daisy chain or through a specific priority-encoded circuit. BGACK - At the end of the current bus cycle the potential bus master takes control of the system buses and asserts a bus grant acknowledge signal to inform the old bus master that it is now controlling the buses. This signal should not be asserted until the following conditions are met:

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1. A bus grant has been received 2. Address strobe is inactive, which indicates that the microprocessor is not using the bus 3. Data transfer acknowledge is inactive, which indicates that neither memory nor peripherals are using the bus 4. Bus grant acknowledge is inactive, which indicates that no other device is still claiming bus mastership.

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Some common bus arbitration schemes

1) Daisy chain, serial arbitration - grant in, grant out, 2) Centralised, parallel arbitration - multiple request lines, centralised arbiter (priority encoder), 3) Distributed arbitration by self-selection - code indicating identity on the bus: NuBus 16 devices, 4) Distributed arbitration by collision detection - Ethernet. NuBus has four arbitration lines. A candidate to bus master asserts its arbitration level on the 4-bit open collector arbitration bus. If a competing master sees a higher level on the bus than its own level, it ceases to compete for the bus. Each potential bus master simultaneously drives and samples the bus. When one bus master has gained bus mastership and then relinquished it, it would not attempt to reestablish bus mastership until all pending bus requests have been dealt with (fairness).

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I have borrowed this section from:

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http://www.whatis.com/dma.htm

DMA (Direct Memory Access) Direct Memory Access is a capability provided by some computer bus architectures that allows data to be sent directly from an attached device (such as a disk drive) to the memory on the computer's motherboard. The microprocessor is freed from involvement with the data transfer, thus speeding up overall computer operation.

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Usually a specified portion of memory is designated as an area to be used for direct memory access. In the ISA bus standard, up to 16 megabytes of memory can be addressed for DMA. The EISA and MCA standards allow access to the full range of memory addresses (assuming they're addressable with 32 bits). PCI accomplishes DMA by using bus mastering (with the microprocessor "delegating" I/O control to the PCI controller).

An alternative to DMA is the Programmed Input/Output (PIO) interface in which all data transmitted between devices goes through the processor. A newer protocol for the ATA/IDE interface is Ultra DMA/33, which provides a burst data transfer rate up to 33 MB (megabytes) per second. Hard drives that come with Ultra DMA/33 also support PIO modes 1, 3, and 4, and multiword DMA mode 2 (at 16.6 megabytes per second).
Sources: Winn L. Rosch. The Winn L. Rosch Hardware Bible (Third Edition), Sams Publishing, 1994 Last update: October 13, 1999

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I have borrowed the next section from:

http://www.freebsd.org/handbook/dma.html

DMA on the IBM-PC: What it is and how it works

Copyright 1995,1997 Frank Durda IV <uhclem@FreeBSD.org>, All Rights Reserved. 10 December 1996. Last Update 8 October 1997. 15 Direct Memory Access (DMA) is a method of allowing data to be moved from one location to another in a computer without intervention from the central processor (CPU). The way that the DMA function is implemented varies between computer architectures, so this discussion will limit itself to the implementation and workings of the DMA subsystem on the IBM Personal Computer (PC), the IBM PC/AT and all of its successors and clones. 20 The PC DMA subsystem is based on the Intel 8237 DMA controller. The 8237 contains four DMA channels that can be programmed independently and any one of the channels may be active at any moment. These channels are numbered 0, 1, 2 and 3. Starting with the PC/AT, IBM added a second 8237 chip, and numbered those channels 4, 5, 6 and 7. The original DMA controller (0, 1, 2 and 3) moves one byte in each transfer. The second DMA controller (4, 5, 6, and 7) moves 16-bits from two adjacent memory locations in each transfer, with the first byte always coming from an even-numbered address. The two controllers are identical components and the difference in transfer size is caused by the way the second controller is wired into the system. The 8237 has two electrical signals for each channel, named DRQ and -DACK. There are additional signals with the names HRQ (Hold Request), HLDA (Hold Acknowledge), -EOP (End of Process), and the bus control signals -MEMR (Memory Read), -MEMW (Memory Write), -IOR (I/O Read), and -IOW (I/O Write). The 8237 DMA is known as a ``fly-by'' DMA controller. This means that the data being moved from one location to another does not pass through the DMA chip and is not stored in the DMA chip. Subsequently, the DMA can only transfer data between an I/O port and a memory address, but not between two I/O ports or two memory locations. Note: The 8237 does allow two channels to be connected together to allow memory-tomemory DMA operations in a non-``fly-by'' mode, but nobody in the PC industry uses this scarce resource this way since it is faster to move data between memory locations using the CPU. In the PC architecture, each DMA channel is normally activated only when the hardware that uses a given DMA channel requests a transfer by asserting the DRQ line for that channel.

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A Sample DMA transfer (IBM-PC)

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 DMA requests buses by asserting HRQ CPU releases bus and asserts HLDA DMA ``is in charge'' activates its -MEMR, -MEMW, -IOR, -IOW output signals 5

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(-IOR, -MEMW in this case), and the memory address DMA asserts the DACK2 to peripheral Peripheral places the byte to be transferred on the bus Data lines DMA waits one clock, and then de-asserts -MEMW and -IOR signals so that the memory will latch and store the byte Peripheral drops the DRQ2 signal, so that the DMA knows it is no longer needed DMA de-asserts -DACK2 signal and peripheral releases data bus DMA controller tri-states the -MEMR, -MEMW, -IOR, -IOW and address signals DMA will de-assert the HRQ signal. CPU sees this, and de-asserts the HOLDA signal. CPU activates its -MEMR, -MEMW, -IOR, -IOW and address lines, and it resumes executing instructions and accessing main memory and the peripherals.

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Here is an example of the steps that occur to cause and perform a DMA transfer. In this example, the floppy disk controller (FDC) has just read a byte from a diskette and wants the DMA to place it in memory at location 0x00123456. The process begins by the FDC asserting the DRQ2 signal (the DRQ line for DMA channel 2) to alert the DMA controller. The DMA controller will note that the DRQ2 signal is asserted. The DMA controller will then make sure that DMA channel 2 has been programmed and is unmasked (enabled). The DMA controller also makes sure that none of the other DMA channels are active or want to be active and have a higher priority. Once these checks are complete, the DMA asks the CPU to release the bus so that the DMA may use the bus. The DMA requests the bus by asserting the HRQ signal which goes to the CPU. The CPU detects the HRQ signal, and will complete executing the current instruction. Once the processor has reached a state where it can release the bus, it will. Now all of the signals normally generated by the CPU (-MEMR, -MEMW, -IOR, -IOW and a few others) are placed in a tri-stated condition (neither high or low) and then the CPU asserts the HLDA signal which tells the DMA controller that it is now in charge of the bus. Depending on the processor, the CPU may be able to execute a few additional instructions now that it no longer has the bus, but the CPU will eventually have to wait when it reaches an instruction that must read something from memory that is not in the internal processor cache or pipeline.

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Now that the DMA ``is in charge'', the DMA activates its -MEMR, -MEMW, -IOR, -IOW output signals, and the address outputs from the DMA are set to 0x3456, which will be used to direct the byte that is about to transferred to a specific memory location. The DMA will then let the device that requested the DMA transfer know that the transfer is commencing. This is done by asserting the -DACK signal, or in the case of the floppy disk controller, -DACK2 is asserted.

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The floppy disk controller is now responsible for placing the byte to be transferred on the bus Data lines. Unless the floppy controller needs more time to get the data byte on the bus (and if the peripheral does need more time it alerts the DMA via the READY signal), the DMA will wait one DMA clock, and then de-assert the -MEMW and -IOR signals so that the memory will latch and store the byte that was on the bus, and the FDC will know that the byte has been transferred. Since the DMA cycle only transfers a single byte at a time, the FDC now drops the DRQ2 signal, so the DMA knows that it is no longer needed. The DMA will de-assert the -DACK2 signal, so that the FDC knows it must stop placing data on the bus.

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The DMA will now check to see if any of the other DMA channels have any work to do. If none of the channels have their DRQ lines asserted, the DMA controller has completed its work and will now tristate the -MEMR, -MEMW, -IOR, -IOW and address signals. 5 Finally, the DMA will de-assert the HRQ signal. The CPU sees this, and de-asserts the HOLDA signal. Now the CPU activates its -MEMR, -MEMW, -IOR, -IOW and address lines, and it resumes executing instructions and accessing main memory and the peripherals. For a typical floppy disk sector, the above process is repeated 512 times, once for each byte. Each time a byte is transferred, the address register in the DMA is incremented and the counter in the DMA that shows how many bytes are to be transferred is decremented. 10 When the counter reaches zero, the DMA asserts the EOP signal, which indicates that the counter has reached zero and no more data will be transferred until the DMA controller is reprogrammed by the CPU. This event is also called the Terminal Count (TC). There is only one EOP signal, and since only DMA channel can be active at any instant, the DMA channel that is currently active must be the DMA channel that just completed its task. If a peripheral wants to generate an interrupt when the transfer of a buffer is complete, it can test for its -DACKn signal and the EOP signal both being asserted at the same time. When that happens, it means the DMA will not transfer any more information for that peripheral without intervention by the CPU. The peripheral can then assert one of the interrupt signals to get the processors' attention. In the PC architecture, the DMA chip itself is not capable of generating an interrupt. The peripheral and its associated hardware is responsible for generating any interrupt that occurs. Subsequently, it is possible to have a peripheral that uses DMA but does not use interrupts. It is important to understand that although the CPU always releases the bus to the DMA when the DMA makes the request, this action is invisible to both applications and the operating systems, except for slight changes in the amount of time the processor takes to execute instructions when the DMA is active. Subsequently, the processor must poll the peripheral, poll the registers in the DMA chip, or receive an interrupt from the peripheral to know for certain when a DMA transfer has completed.
lect_dma.doc

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