Boolean Algebra

&
Logic Gates
 Common Postulates (Boolean Algebra)
• Closure
N={1,2,3,4,5,…..}
It is closed w.r.t +
i.e. a+b=c
as a,b,cΣN
• Associative Law
(x*y)*z = x*(y*z)
for all x,y,z,ΣS
• Commutative Law
x*y = y*x for all x,yΣS
x+y = y+x
x+y = y+x x.Y = y.x
 Common Postulates (Boolean Algebra)
• Identity Element
e*x = x*e = x xΣS
x+0 = 0+x = x e+x = x+e = x
x.1 = 1.x = x 0+x = x+0 = x
1*x = x*1 = x
• Inverse
x+x’ = 1 x*y = e →a*1/a = 1
x+y = e
x.x’ = 0
a+(-a) = 0
• Distributed Law
x*(y.z) = (x*y) . (x*z)
x.(y+z) = (x.y) + (x.z)
x+(y.z) = (x+y) . (x+z)
 Boolean Algebra and Logic Gates
x y x.y x y x+y x x’
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 1
x.(y+z) = (x.y)+(x.z)
x y z Y+z x.(y+z) x.y x.z (x.y)+x.z
0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 1
1 1 1 1 1 1 1 1
 Postulates and Theorems of Boolean Algebra
Postulate 2 (a) x+0 = x (b) x.1 = x

Postulate 5 (a) x+x’ = 1 (b) x.x’ = 0

Theorem 1 (a) x+x = x (b) x.x = x

Theorem 2 (a) x+1 = 1 (b) x.0 = 0

Theorem3, involution (x’)’ = x

Postulate3, commutative (a) x+y = y+x (b) xy = yx

Theorem4, associative (a) x+(y+z)=(x+y)+z (b) x(yz) = (xy)z

Postulate4, distributive (a) x(y+z)=xy+xz (b) x+yz = (x+y)(x+z)

Theorem5, DeMorgan (a) (x+y)’ = x’y’ (b) (xy)’ = x’+y’

Theorem6, absorption (a) x+xy = x (b) x(x+y)=x

 Theorems
1a. x+x = x
x+x = (x+x).1
= (x+x)(x+x’)
= x+xx’
=x+0
=x
1b. x.x = x (Remember Duality of 1a)
x.x = xx+0
= xx+xx’
= x(x+x’)
= x.1
=x
 Theorems
2a. x+1 = 1
x+1 =1.(x+1)
= (x+x’)(x+1)
= (x+x’)
= x+x’
=1
2b. X.0 = 0 (Remember Duality of
of
2a)
3. (x’)’ = x
Complement of x = x’
Complement of x’ = (x’)’ = x
6a x+xy = x
x+xy = x.1+xy
= x(1+y)
= x.1
=x
6b. x(x+y) = x (Remember Duality of 6a)

Can also be proved using truth table method

 x y xy x+xy
0 0 0 0
0 1 0 0
1 0 0 1
1 1 1 1

x=x+xy

x y x+y (x+y)’ x’ y’ x’y’

0 0 0 1 1 1 1
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 0

(x+y)’ = x’y’ → DeMorgan’s Theorem

(xy)’ = x’ +y’ → DeMorgan’s Theorem
Operator Precedence
2.( )
3.NOT
4.AND
5.OR
 x y x y

xy’ xy x’y

x’y’

VENN DIAGRAM FOR TWO VARIABLES VENN DIAGRAM ILLUSTRATION X=XY+X

x x y
y

z z

x+(y+z) xy+xz

VENN DIAGRAM ILLUSTRATION OF THE DISTRIBUTIVE LAW

TRUTH TABLE FOR F1=xyz’, F2=x+y’z, F3=x’y’z+x’yz+xy’ and
F4=xy’+x’z

x y z F1 F2 F3 F4
0 0 0 0 0 0 0
0 0 1 0 1 1 1
0 1 0 0 0 0 0
0 1 1 0 0 1 1
1 0 0 0 1 1 1
1 0 1 0 1 1 1
1 1 0 1 1 0 0
1 1 1 0 1 0 0
 z
x F2
x
y F1

z
(b) F2 = x+y’z
(a) F1 = xyz’
x

F3
z

(c) F3 = x’y’z+x’yz+xy’
x

F4

(c) F4 = xy’+x’z
z

Implementation of Boolean Function with GATES

 Algebraic Manipulations for Minimization of Boolean Functions
(Literal minimization)
1. x+x’y = (x+x’)(x+y)
= 1.(x+y)=x+y
3. x(x’+y) = xx’+xy
= 0+xy=xy
5. x’y’z+x’yz+xy’
= x’z(y’+y)+xy’
= x’z+xy’
8. xy+x’z+yz (Consensus Theorem)
=xy+x’z+yz(x+x’)
=xy+x’z+xyz+x’yz
=xy(1+z)+x’z(1+y)
=xy+x’z
13. (x+y)(x’+z)(y+z)=(x+y)(x’+z)
by duality from function 4
 Complement of a Function

(A+B+C)’ = (A+X)’
= A’X’
= A’.(B+C)’
= A’.(B’C’)
= A’B’C’
∴(A+B+C+D+…..Z)’ = A’B’C’D’…..Z’
(ABCD….Z)’ = A’+B’+C’+D’+….+Z’
Example using De Morgan’s Theorem (Method-1)
F1 = x’yz’+x’y’z
F1’ = (x’yz’+x’y’z)’
= (x+y’+z)(x+y+z’)
F2 = x(y’z’+yz)
F2’= [x(y’z’+yz)]’
= x’+(y+z)(y’+z’)
Example using dual and complement of
each literal (Method-2)

F1 = x’yz’ + x’y’z
Dual of F1 = (x’+y+z’)(x’+y’+z)
Complement ⇒ F1’ = (x+y’+z)(x+y+z’)

F2 = x(y’z’+yz)
Dual of F2=x+(y’+z’)(y+z]
Complement =F2’= x’+ (y+z)(y’+z’)
Minterm or a Standard Product
n variables forming an AND term provide 2n possible
combinations, called minterms or standard products
(denoted as m1, m2 etc.).
Variable primed if a bit is o
Variable unprimed if a bit is 1
Maxterm or a Standard Sum
n variables forming an OR term provide 2n possible
combinations, called maxterms or standard sums
(denoted as M1,M2 etc.).
Variable primed if a bit is 1
Variable unprimed if a bit is 0
MINTERMS AND MAXTERMS FOR THREE BINARY VARIABLES

MINTERMS MAXTERMS
x y z Term Designation Term Designation
0 0 0 x’y’z’ m0 x+y+z M0
0 0 1 x’y’z m1 x+y+z’ M1
0 1 0 x’yz’ m2 x+y’+z M2
0 1 1 x’yz m3 x+y’+z’ M3
1 0 0 xy’z’ m4 x’+y+z M4
1 0 1 xy’z m5 x’+y+z’ M5
1 1 0 xyz’ m6 x’+y’+z M6
1 1 1 xyz m7 x’+y’+z’ M7
 FUNCTION OF THREE VARIABLES
x y z Function f1 Function f2
0 0 0 0 0
0 0 1 1 0
0 1 0 0 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

f1 = x’y’z+xy’z’+xyz =m1 + m4 + m7
f2 = x’yz+xy’z+xyz’+xyz = m3 + m5 + m6 + m7
 MINTERMS AND MAXTERMS FOR THREE BINARY VARIABLES

f1 = x’y’z+xy’z’+xyz
f1’ = x’y’z’+x’yz’+x’yz+xy’z+xyz’
f1 =(x+y+z)(x+y’+z)(x+y’+z’)(x’+y+z’) (x’+y’+z)
= M0.M2.M3.M5.M6
= M0M2M3M5M6
f2 = x’yz+xy’z+xyz’+xyz
f2’ = x’y’z’+x’y’z+x’yz’+xy’z’
f2 = (x+y+z)(x+y+z’)(x+y’+z)(x’+y+z)
= M0 M1 M2 M4
Canonical Form
Boolean functions expressed as a sum of minterms or product of
maxterms are said to be in canonical form.
M3+m5+m6+m7 or M0 M1 M2 M4
 Sum of Minterms (Sum of Products)
Example: F = A+B’C
F = A(B+B’)+B’C(A+A’)
= AB+AB’+AB’C+A’B’C
= AB(C+C’)+AB’(C+C’)+AB’C+A’B’C
= ABC+ABC’+AB’C+AB’C’+AB’C+A’B’C
= A’B’C+AB’C’+AB’C+ABC’+ABC
= m1+m4+m5+m6+m7
F(A,B,C)=Σ(1,4,5,6,7)

ORing of term AND terms of variables A,B &C

They are minterms of the function
 Product of Maxterms (Product of sums)
Example: F = xy+x’z
F = xy+x’z
F = (xy+x’)(xy+z) distr.law (x+yz)=(x+y)(x+z)
= (x+x’)(y+x’)(x+z)(y+z)
= (x’+y)(x+z)(y+z)
= (x’+y+zz’)(x+z+yy’)(y+z+xx’)
= (x’+y+z)(x’+y+z’)(x+z+y)(x+z+y’)(y+z+x)(y+z+x’)
= (x+y+z)(x+y’+z)(x’+y+z)(x’+y+z’)
= M0 M2 M4 M5
F(x,y,z) = Π(0,2,4,5)

ANDing of terms Maxterms of the function (4 OR terms

of variables x,y&z)
 Conversion between Canonical Forms
F(A,B,C) = Σ(1,4,5,6,7)
⇒ sum of minterms
F’(A,B,C) = Σ(0,2,3)
= m0+m2+m3
F(A,B,C) = (m0+m2+m3)’
= m0’.m2’.m3’
= M0 M2 M3
= Π(0,2,3)
⇒ Product of maxterms

Similarly
F(x,y,z) = Π(0,2,4,5)
F(x,y,z) = Σ(1,3,6,7)
 Standard Forms
Sum of Products (OR operations)
F1 = y’+xy+x’yz’
(AND term/product term)

Product of Sums (AND operations)

F2=x(y’+z)(x’+y+z’+w)

(OR term/sum term)

Non-standard form
F3=(AB+CD)(A’B’+C’D’)

Standard form of F3
F3=ABC’D’ + A’B’CD
 TRUTH TABLE FOR THE 16 FUNCTIONS OF
TWO BINARY VARIABLES
x y F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15

0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Operator
symbols
+ ,
⊂ ,
⊃

F0 = 0 F1 = xy F2 = xy’ F3 = x
F4 = x’y F5 = y F6 = xy’ +x’y F7= x +y
F8 = (x+y)’ F9 = xy +x’y’ F10 = y’ F11 = x +y’
F12 = x’ F13 = x’ + y F14 = (xy)’ F15 = 1
 BOOLEAN EXPRESSIONS FOR THE 16 FUNCTIONS OF TWO VARIABLE

BOOLEAN OPERATOR NAME COMMENTS

FUNCTIONS SYMBOL

F0 =0 NULL BINARY CONSTANT 0

F1=xy x.y AND x and y

F2=xy’ x/y inhibition x but not y

F3=x transfer x
F4=x’y y/x inhibition y but not x
F5=y transfer y
F6=xy’+x’y x y exclusive-OR x or y but not both
F7=x+y x+y OR x or y
F8=(x+y)’ x y NOR not OR
F9=xy+x’y’ x y *equivalence x equals y
F10=y’ y’ complement not y
F11=x+y’ x⊂y implication if y then x
F12=x’ x’ complement not x
F13=x’+y x⊃y implication if x then y
F14=(xy)’ x y NAND not AND
F15=1 IDENTITY BINARY CONSTANT 1
• *Equivalence is also known as equality, coincidence, and
exclusive NOR
• 16 logic operations are obtained from two variables x &y
• Standard gates used in digital design are: complement,
transfer, AND, OR , NAND, NOR, XOR & XNOR (equivalence).
 H and L LEVEL IN IC LOGIC FAMILIES

IC Family Voltage High-level voltage Low-level

Type Supply (V) (V) voltage (V)

Range Typical Range Typical

TTL Vcc=5 2.4-5 3.5 0-0.4 0.2
ECL VEE=-5.2 -0.95- -0.7 -0.8 -1.9-- -1.6 -1.8
CMOS VDD=3--10 VDD VDD 0-0.5 0
Positive Logic: Logic-1 Logic-0
Negative Logic Logic-0 Logic-1
 TYPICAL CHARACTERISTICS OF IC
LOGIC FAMILIES
IC Logic Fan out Power Propagation Noise Margin (v)
Family Dissipation (mw) delay (ns)
Standard TTL 10 10 10 0.4
Shottky TTL 10 22 3 0.4
Low power
Shottky TTL 20 2 10 0.4
ECL 25 25 2 0.2
CMOS 50 0.1 25 3

TTL basic circuit : NAND gate

ECL basic circuit: NOR gate
CMOS basic circuit: Inverter to construct NAND/NOR
 DIGITAL LOGIC GATES
NAME GRAPHIC ALGEBRIC TRUTH
SYMBOL FUNCTION TABLE

AND F=XY X Y F
X 0 0 0
F
Y 0 1 0
1 0 0
1 1 1

OR F=X+Y X Y F
0 0 0
X
F 0 1 1
Y
1 0 1
1 1 1
 NAME GRAPHIC ALGEBRIC TRUTH
SYMBOL FUNCTION TABLE
Inverter X F
0 1
X F F=X’ 1 0

Buffer X F
0 0
X F
F=X 1 1

X Y F
X F 0 0 1
NAND Y F=(XY)’
0 1 1
1 0 1
1 1 0
NAME GRAPHIC ALGEBRIC TRUTH
SYMBOL FUNCTION TABLE
X Y F
X 0 0 1
NOR Y F F=(X+Y)’ 0 1 0
1 0 0
1 1 0

X Y F
Exclusive-OR X F F=XY’+X’Y 0 0 0
Y
(XOR) =X⊕Y 0 1 1
1 0 1
1 1 0

Exclusive-NOR X Y F
or X F 0 0 1
Y F=XY+X’Y’
Equivalence 0 1 0
=X Y
1 0 0
1 1 1
 (X+Y)’
x
[Z+(X+Y)’]’
Y (X Y) Z=(X+Y) Z’
=XZ’+YZ’
Z

X (X ( Y Z)=X’(Y+ Z)

=X’Y+X’Z
[X+(Y+Z)’]’
(Y+Z)’
Y
Z

Demonstrating the nonassociativity of the NOR operator

(X ↓ Y)↓ Z ≠ X ↓(Y↓ Z)
X X (XYZ)’
(X+Y+Z)’ Y
Y
Z Z

(a) There input NOR gate (b) There input NAND gate

A
B
C

F=[(ABC)’. (DE)’]’=ABC+DE

D
E
(c) Cascaded NAND gates

Multiple-input AND cascaded NOR and NAND gates

 TRUTH TABLE
X
Y X Y Z F
0 0 0 0 1
0 0 1 1 0
F=X ⊕ Y ⊕ Z 0 1 0 1 0
Z
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
(a) Using two input gates 1 1 0 0 1
1 1 1 1 0

X XOR
Y F=X ⊕ Y ⊕ Z
Z
XNOR
(b) Three input gates Odd
function

Even
(b) Three input exclusive OR gates function
 IC DIGITAL LOGIC FAMILIES
TTL⇒ Transistor- Transistor Logic
• Very popular logic family.
• It has a extensive list of digital functions.
• It has a large number of MSI and SSI devices, also has LSI devices.

ECL⇒ Emitter Coupled Logic

• Used in systems requiring high speed operations.
• It has a large number of MSI and SSI devices, also LSI devices.
MOS ⇒ Metal-Oxide Semiconductor
• Used in circuit requiring high component density
• It has a large number of MSI and SSI devices, also LSI devices
(mostly)
CMOS ⇒ Complementary MOS
• Used in systems requiring low power consumption.
• It has a large number of MSI and SSI devices, also has LSI devices.
I2L ⇒ Integrated - Injection Logic
• Used in circuit requiring high component density.
• Mostly used for LSI functions
 Some Typical IC Gates
VCC VCC
14 13 12 11 10 9 8 14 13 12 11 10 9 8

1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND

7404 Hex Inverters 7400 Quadruple 2-input

NAND gates

TTL gates
VCC 2 Some Typical IC Gates
16 15 14 13 12 11 10 9

10107 Triple
Exclusive – OR/
NOR gates

1 2 3 4 5 6 7 8 VEE 2 (-5.2V)
VCC 1

VCC 2
16 15 14 13 12 11 10 9

10102 Quadruple
2-Input NOR gate

VEE (-5.2V)
VCC 1 1 2 3 4 5 6 7 8
 (3-15 V)
VDD NC

14 13 12 11 10 9 8

C MOS
GATES

1 2 3 4 5 6 7
NC Vss (GND)

4002 dual 4 input NOR gates

 NC NC

16 15 14 13 12 11 10 9

CMOS
GATES
1 2 3 4 5 6 7 8 Vss
VDD (GND)
(3-15 V)

4050 Hex buffer

 SIGNAL LOGIC SIGNAL
LOGIC
VALUE VALUE VALUE
VALUE

1 H 0 H

0 L
L 1

Negative Logic
Positive Logic

Signal amplitude assignment and type of logic

X y z
L L H x
TTL
L H H 7400 z
H L H GATE
y
H H L

Truth table in terms of Gate block diagram

H and L

X y z
0 0 1
x
0 1 1 z
y
1 0 1
1 1 0

Truth table for positive logic Graphic symbol for

H=1, L=0 positive logic NAND gate
X y z
x
1 1 0 z
y
1 0 1
0 1 1 Graphic symbol for negative logic
0 0 1 NOR gate

Truth table for negative logic

L=1 H=0 Same gate can function
+ive logic NAND or -ive logic NOR
+ive logic NOR or -ive logic NAND

DEMONSTRATION OF POSITIVE AND

NEGATIVE LOGIC
 Characteristics of IC logic families
(parameters)
Fan-out
Specifies the number of standard loads (the amount of current needed by
an input of another gate in the same IC family) that the output of a gate can
drive without impairing its normal operation. it is expressed by a number.
Power dissipation
It is the supplied power required to operate the gate. It is expressed in mw.
Propagation delay
It is the average transition delay time for a signal to propagate from input to
output when the binary signals change in value. It is expressed in ns.
Noise margin
It is the maximum noise voltage added to the input signal of a digital circuit
that does not cause an undesirable change in the circuit output. It is
expressed in volts (v).