MemoryDesignConsiderationsWhen MigratingtoDDR3Interfacesfrom DDR2

ByRajMahajan,VirageLogic Abstract TheemergingDDR3memorystandardwillextendtheperformancerangeofDDR memoriesconsiderably,whilemaintainingsomeamountofbackwardscompatibilitywith theexistingDDR2memorystandard.Itisimportanttounderstandthesimilaritiesand differencesbetweentheDDR3standardandtheexistingDDR2standardinordertoget themaximumbenefitfromthenewstandardwhilereusingasmuchaspossiblefromany previousDDR2memoryinterfacedesign.Thispaperwillprovidethereaderwitha detailedunderstandingofthekeydesignconsiderationswhenmigratingtoaDDR3 systeminterfacefromaDDR2interface. ThispaperwillreviewthenewDDR3featuresandcompareandcontrastthemto previousfeaturesavailableintheDDR2specification.Oneofthebiggestchangesisthe inPhysicalLayer(PHY)portionofthememoryinterfaceandthesechangeswillbehigh lightedandillustratedwithanexampledesignofahighperformanceprocessorinterface. Theareaswherebackwardscompatibilityshouldbemaintainedwillalsobeillustrated withanexampledesign,showinghowsimplechangescanprovidesignificantbenefitsin reuseandsystemflexibility. 1.Introduction TheemergingDDR3memorystandardwillextendtheperformancerangeofDDR memoriesconsiderably,whilemaintainingsomeamountofbackwardscompatibilitywith theexistingDDR2memorystandard.Itisimportanttounderstandthesimilaritiesand differencesbetweentheDDR3standardandtheexistingDDR2standardinordertoget themaximumbenefitfromthenewstandardwhilereusingasmuchaspossiblefromany previousDDR2memoryinterfacedesign.Thispaperwillprovidethereaderwitha detailedunderstandingofthekeydesignconsiderationswhenmigratingtoaDDR3 systeminterfacefromaDDR2interface. 2.AComparisonofDDR2andDDR3MemoryStandards TheDDR2memorystandardisbeingupgradedwiththeadventoftheDDR3standard. Thevarietyofmemorydevicesavailabletodayprovidesthesystemarchitectwith multipleoptionswhenselectingamemory.Beforegoingintothedetailedcomparisonof DDR2andDDR3let'sreviewthekeyfeaturesofatypicalDDR2memorysubsystemand theassociatedmemorycontroller.Thiswillserveasabaselineforthedetailed comparison.

2.1DDR2Description AtypicalDDR2memorysubsystemusesaDIMMtohousemultipleDDR2memory devices.AtypicalDDR2DIMMarchitectureisillustratedinFigure1below.Thecontrol andaddresssignalscomeontotheDIMMandareroutedtothememorydevicesinaT branchtopology.Thisarchitecturebalancesthedelaytoeachmemorydevice,but introducesadditionalskewduetothemultiplestubsandthestublength.

Figure1:DDR2MemoryModuleArchitecture ADDR2memorycontrollerislocatedonthechipdrivingtheDIMMmodule.Atypical DDR2memorycontrollerisshowintheblockdiagraminFigure2.ThePHYis responsibleforthephysicalinterfacebetweentheDDRDRAMandtherestofthe system.Timingiscontrolledpreciselytoinsuredataiscapturedorpresentedinjustthe rightrelationshipwiththeDRAMclockingsignals.DatareadfromtheDRAMis optionallycorrectedbytheECCblockandthenprovidedtothependingwriteandread modifywriteFIFO.IfECCisbeingused,theECCcheckbitsarecomputedpriortothe writetomemorybyanotheroptionalECCblockinthewritepath.

Figure2:DDR2FunctionalBlockDiagram Theschedulerprioritizesthecurrentlistofcommandsanddetermineswhichcommandis themosturgentandissuesthatcommandtotheDRAM.Dataisreadorwrittentothe memorybasedonthescheduler'scomputationofaccesspriority.Thescheduler constantlyworkstowardsthegoalofmaximizingoverallsystembandwidthwhileissuing allhighprioritycommandasquicklyaspossible. CommandsareoptionallypipelinedandaddedtothependingFIFO.Ifthecommandis mosturgent(directread)itbypassesthependingFIFOandisissueddirectlytothe memory.RegularpriorityaccessesmaketheirwaythroughthependingreadFIFOorthe readtokenFIFOforcommandcompletion. 2.2DDR3Description ThemainthrustoftheDDR3memorystandardistoincreasebandwidthwhilemakingit relativelyeasyforthedesignertotakeadvantageofthisbandwidthincrease.Innovations inthephysicallayer(PHY)portionoftheDDR3interfacesupportthisincreasein bandwidth.OneoftheseinnovationsistheuseofaLevelingtechniquethatadjustsfor thedelaybetweenDDR3memories. TheDDR3specificationcansupportaflybyarchitectureeitheronamemorymoduleor onaboard.Inthisarchitecture,illustratedinFigure3below,thesignalsfromthe memorycontrollerareconnectedinseriestoeachmemorycomponent.Inthisexample,a memorymodule,thesignalsfromtheDDR3PHYcomeintothemiddleofthemodule andconnecttoeachmemorychipsequentially.Thisreducedthenumberofstubsandthe stublengths.Terminationisplacedjustattheendofthesignal.Thisimprovesthesignal characteristicsoverthetraditionalDDR2topology.

Figure3:FlybyTopologyforDDR3UnbufferedDIMM ThedrawbacktothisapproachisthatthedelayfromthePHYoutputsignalstoeach memoryisslightlydifferent,dependingonwherethememorychipisinthesequence. ThisdelaydifferenceneedstobecompensatedforbytheDDR3PHYandusesthenew LevelingfeaturerequiredbytheDDR3specification.Thereisadifferenttechniquefor bothwriteandreadleveling. 2.2.1WriteLeveling DuringWriteLevelingthememorycontrollerneedstocompensatefortheadditional flighttimeskewdelayintroducedbytheflybytopologywithrespecttostrobeandclock. Inparticular,thetDQSS,tDSSandtDSHtimingrequirementswouldbeverydifficultto meet.Thesetimingparameterscanbemetbyusingaprogrammabledelayelementon DQSwithfineenoughgranularitysothattheproperdelaycanbeinsertedtocompensate fortheadditionalskewdelay.Thefigurebelowshowstheneededtimingrelationship. ThesourceCKandDQSsignalsaredelayedingettingtothedestinationasillustratedby arrow#1andarrow#2respectively.(Thisdelaycanbedifferentforeachmemory componentonthememorymoduleandwillbeadjustedonachipbychipbasisandeven onabytebasisifthechiphasmorethanonebyteofdata.Thediagramillustratesjustone instanceofamemorycomponent).ThememorycontrollerrepeatedlydelaysDQS,astep atatime,untilatransitionfromazerotoaoneisdetectedonthedestinationCKsignal. ThiswillrealignDQSandCLsothatthedestinationdataontheDQbuscanbecaptured reliably.Becauseallthisisdoneautomaticallybythecontrollertheboarddesignerneed notworryaboutthedetailsoftheimplementationheorshejustbenefitsfromthe additionalmargincreatedbytheWriteLevelingfeatureintheDDR3memorycontroller.

Figure4.TimingDiagramforWriteLeveling 2.2.2ReadLeveling DuringReadLevelingthememorycontrolleradjustsforthedelaysintroducedbythefly bymemorytopologythatimpactthereadcycle.Thisisdoneviatheadditionofaspecial MultiPurposeRegister(MPR)intheDDR3memorydevice.TheMPRcanbeloaded withpredefineddatavaluesviaaspecialcommandfromthememorycontroller.These datavaluescanbeusedforsystemtimingcalibrationbythememorycontroller. AsshowninFigure5below,theMPRcanbeselected,bysettingabitinanothermemory register(EMRS3,bitA2),toswitchthesourceofdataformemoryreadtocomefromthe MPR,notthenormalmemoryarray.TheMPRdataissubstitutedfortheDQ,DM,DQS and/DQSpadsonthememorydevice.Thisfeatureallowsthememorycontrollerto calibratethetimingofthereadpathtoadjustforanyadditionaldelaysintroducedbythe DDR3flybyarchitecture.

Figure5.ReadLevelingUsingMPR 2.2.3OtherDDR3Features DDR3hasadditionalfeaturestoimproveperformanceandreliability.Theseincludea Resetpin,an8bitprefetch,andZQcalibration.AnewResetpinisusedtoclearallstate informationintheDDR3memorydevicewithouttheneedtoindividuallyreseteach controlregisterorpowerdownthedevice.Thissavestimeandpowerwhenbringingthe devicetoaknownstate.The8bitprefetchisusedinconjunctionwithburstlengthof4 or8.Thisimprovesperformanceforsequentialaccesses.ThenewZQcalibrationfeature allowsthememorydevicetotakealongertimeforcalibrationatstartupandasmaller timeduringperiodiccalibrationactivities.Thetablebelowshowsafeaturebyfeature

comparisonofDDR,DDR2andDDR3memorydevices. DDR DataRate Interface SourceSync 200400Mbps SSTL_2 DDR2 400800Mbps SSTL_18 DDR3 8001600Mbps SSTL_15

Bidirectional Bidirectional Bidirectional DQS DQS DQS (Singleendeddefault) (Single/DiffOption) (Differentialdefault) BL=2,4,8 (2bitprefetch) 15nseach No No No No BL=4,8 (4bitprefetch) 15nseach No Yes OffChip No BL=4,8 (8bitprefetch) 12nseach Yes Yes OnChipwithZQpin Yes

BurstLength CL/tRCD/tRP Reset ODT DriverCalibration Leveling

Table1:DDR,DDR2andDDR3FeatureComparison 3.0PlanningForMigrationanExampleDesign InordertoexplorehowtoprepareaDDR2designformigrationtoaDDR3designitwill helptoestablishanexamplesystem.Let'sassumethatthesystemwillrequireaDIMM interfaceforDDR2andwillwanttouseasimilartypeofmemorymoduleintheDDR3 implementation.Performanceisincreasinglyimportantformanyapplicationssothe decisionistoinitiallydesignthecontrollerasaDDR2design,buttoallowfuture migrationtoDDR3.Asmuchaspossible,wewanttomakeiteasytomodifytheboard andthememorycontrollertomigratefromtheDDR2implementationtoDDR3. 3.1BoardLevelIssues OneofthebiggestissueswhenthinkingofmigratingfromDDR2toDDR3isthatthe DIMMhavedifferentpinoutsandsizes.Thismeansthatitwillbeverydifficult,atthe boardleveltojustpluginanewmemorymodule.Thebestyoucanhopeforistotake intoaccountsomeoftheotherkeycharacteristicsandmakeiteasytospintheboardfora DDR3module.Probablythemostimportantitemstotakecareofattheboardlevelwill beDQS,theResetpin. 3.1.1DQS InDDR3DQSisspecifiedasdifferentialwhileinDDR2itcanbesingleendedor

optionallydifferential.ClearlyifthedifferentialversionisusedinDDR2itwillmakethe transitiontoDDR3easier.Thismayrequireadditionalpinsinthememorycontroller,but ifupwardcompatibilityisimportanttheextrapinswillbeworthit.YourDDR2 implementationwillbemorerobustaswell. InDDR3theDQSissourcedbyeachmemorydeviceinordertoaccountforthe additionaldelayfromtheflybytopology.ThenumberofDQSsignalsisthuslargerin theDDR3implementationthattheDDR2version.Again,iftheadditionalpinsarenota bigissueitwillhelpwiththemigrationtoDDR3toimplementtheadditionalDQS signalsintheDDR2implementation. 3.1.2Reset TheResetpinpresentinDDR3wouldbeeasytoaddtoDDR2.Thepinwouldn'tdo anythingintheDDR2implementation,butincludingitwouldinsurethatthepinis availablewhenitstimetomigratetoDDR3. 3.2MemoryControllerIssues OtheraspectsoftheDDR2toDDR3migrationwillrequiresomeimpacttothememory controller.IftheDDR2memorycontrollerisdesignedwithsomeoftheseissuesinmind itcansimplifytheprocessconsiderably.Someofthemostimportantissuesaretheoutput drivers,DLLsforwritelaunch,andReadLeveling. 3.2.1OutputDrivers TheDDR2standardcallsfor1.8VSSTLIOs.DDR3callsfor1.5VSSTLIOs.Itmaybe difficulttofindanIObufferthatcansupportbothstandards.Itmightrequirea programmableIO,similartothosefoundonFPGAs,tosupportbothstandards.Achange inIObufferswouldrequireaspinofthechipdrivingtheDDR3memory,butperhapsa metalmaskoptioncouldbeusedtomakethischangelessexpensive. 3.2.2DLLsforWriteLaunch TypicalDDR2memorycontrollerscangetawaywithoneDLLforseveraldataoutputs. InDDR3,duetotheflybytopology,itwillbemoreusualtoseeaDDLforevery8bits orso.ThiswouldrequirealargernumberofDLLtobeincludedintheDDR2designin ordertoprovidetheresourcesrequiredfortheDDR3migration.AdigitalDLL implementationcanbeverycompactindiesizeandcanminimizetheoverhead associatedwiththeDDR3requirement. 3.2.3ReadLeveling TypicalDDR2memorycontrollersuseanextrapairofIOpinstocalibratethecontroller readtiming.Thesepinsareusedtohelpadjusttheincomingdatawithrespecttothe strobe.Othercontrollersuseatrainingsequencebywritingandreadingdatafrom memoryandadjustingthestrobetooptimizethedatacapturepoint.InDDR3theRead Levelingfeatureisusedtodothisandrequiresnoadditionalpins.Ifthememory controllercanbedesignedtoincludetheReadLevelingfeature,evenifnotusedin DDR2,itwouldhelpwithDDR3migration.

4.0Conclusion DDR3offersasubstantialperformanceimprovementoverpreviousDDR2memory systems.NewDDR3features,alltransparentlyimplementedinthememorycontroller, improvethesignalintegritycharacteristicsofDDR3designssothathigherperformance isachievedwithoutanundueburdenforthesystemdesigner.Ifproperconsiderationis giventoanynewDDR2memorydesign,itcanbearelativelyeasyupgradetosupport DDR3inthenextgenerationdesign.Thispaperidentifiedthekeydifferencesbetween DDR2andDDR3andillustratedsomeofthekeyissuesthatneedtobeaddressedtoeasy migrationtoDDR3.