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UNIVERSIDAD TECNICA DEL NORTE FACULTAD DE INGENIERIA EN CIENCIAS APLICADAS LABORATORY 1

BASIC PARAMETERS OF LOGICAL GATES

Ic

1. With Q1(transistor 2N3707 or similar) working in the cutoff and saturation regions, design an inverter as in the figure. Apply inV1 a variable voltage from -0,2V. to 5 V. in suitable steps (0,2 V), measure Ic,Ib,V2,Vbe for each value. Repeat the procedure from 5V. to -0,2V.

Sketch: V1 vs Ib Ib Vbe vs Ib V2 vs V1

2. Now using a quad 2-input TTL NAND gate (7400). Implement one inverter in two different ways. As was made above, take suitable measurements to sketch the transfer characteristic of this gate. 3. With the NAND gate as inverter, and using a square wave signal of 5 V. peak, 100 kHz as input, find for this gate: propagation delay times (tpHL, tpLH), rise time ( tR) and fall time (tF). Plot the input and output waves in a common scale.

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