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  • ECEN3233 Exam2 Makeup Fall2010

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    A 4-bit counter and D latch/register are provided with clock and D input signals. The summary must describe the output waveforms for the latch and register when the counter counts from 0110 to 0000. For a level-high sensitive latch, the output would remain at 1 until the counter reaches 0000, then change to 0. For a positive edge-sensitive register, the output would change values on each rising edge of the clock, matching the changing D input signal as the counter counts down.

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    Digital Logic

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    A 4-bit counter and D latch/register are provided with clock and D input signals. The summary must describe the output waveforms for the latch and register when the counter counts from 0110 to 0000. For a level-high sensitive latch, the output would remain at 1 until the counter reaches 0000, then change to 0. For a positive edge-sensitive register, the output would change values on each rising edge of the clock, matching the changing D input signal as the counter counts down.

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    19 views5 pages

    ECEN3233 Exam2 Makeup Fall2010

    Uploaded by

    cebuano88
    A 4-bit counter and D latch/register are provided with clock and D input signals. The summary must describe the output waveforms for the latch and register when the counter counts from 0110 to 0000. For a level-high sensitive latch, the output would remain at 1 until the counter reaches 0000, then change to 0. For a positive edge-sensitive register, the output would change values on each rising edge of the clock, matching the changing D input signal as the counter counts down.

    Copyright:

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    Download as PDF, TXT or read online from Scribd
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    of 5

    ECEN 3233 Digital Logic Design Fall 2010 Exam 2 (Make up) 40 minutes

    WRITE YOUR NAME HERE ___________________________


    All questions must be answered on test paper!

    1. (25 pts) A 4 bit counter (CD4CE) and a clocked D register or latch are provided. Clock (CLK) and D_input inputs are shown below. Draw the waveforms for the output Q_output when the clocked element is a level high (1) sensitive latch, or when the clocked element is positive (rising) edge sensitive register. Assume that the Q[3:0] are initially set to 0110, and Q_output is initially at 1.

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    CLK

    t D_input

    t Q_output level high (1) sensitive latch

    t Q_output positive edge sensitive register

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    2. (50 pts) Pete (The same Pete who got kidnapped by the aliens) has to program his Spartan-3E board to help Shoot the Bunnies game development team.

    Television

    Game Console

    The purpose of this game is to shoot 5 pink bunnies, 5 red bunnies, and 5 blue bunnies and each bunny is worth 10 points. Shooting 5 bunnies of a same color in sequence will add 100 extra points to the players current score. For example: killing pink bunny, pink bunny, pink bunny, pink bunny, and pink bunny will add 150 points to the players current score. Killing pink bunny, pink bunny, red bunny, pink bunny, pink bunny and pink bunny will add 60 points to the players current score. When all of the bunnies are dead, output the players score and end the game. Player will initially start with a score of 50. Player needs to be careful not to shoot any of the 5 pandas. Killing one panda will reduce your points by 20. Killing all of the pandas will end the game. Having a score less than or equal to 0 will end the game. You may assume that you have inputs called, but not limited to, pinkbunny, redbunny, bluebunny, panda, and clock. You may assume that you have an output called, but not limited to, userscore. Go help Pete by writing an efficient Verilog code. You do not need to write down the code for UCF.

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